Note: Descriptions are shown in the official language in which they were submitted.
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B~ÇKGROUNP OF THE INVENTION
- This invention relates to a method for manufacturing dense,
fine line printed circuit boards and multiple layer printed
circuit board packages.
There are many methods of manufacturing printed circuit
boards used extensively throughout the electronics industry.
The advent of very large scale integrated circuits ("VLSIn) has
created an ever increasing demand for higher component density
per unit of printed circuit board area. To meet this growing
demand, printed circuit boards must be fabricated having
extremely narrow conductor line widths and spacings. Because
of the limitations inherent in the prior art methods, they cannot
successfully meet the industry demands for high yield, multilayer
printed circuit boards possessing good dimensional stability and
ever-smaller line widths and spacings.
Although there are many methods known and used in the
fabrication of printed circuit boards, the most widely accepted
methods employ an etching technique. Typically, these methods
include the steps of cladding a base of an electrically
insulating matecial with a conductive copper foil, placing a
photoresist material in intimate contact therewith, developing
the photoresist material to define a conductive circuit pattern
thereonr and etching away any exposed foil which is not covered
with photoresist to provide a raised conductive circuit patternO
This prior art method creates several problems since the
conductor patterns are`not flush with the surface of the circuit
board, a conductor line can be easily scratched during handling,
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resulting in an open circuit. Also, the copper conductor may
sliver and bridge across adjacent conductors, causing short
circuits.
Furthermore, the etching step in the prior art method may
also create a variety of irregularities and defects in the
printed circuitry. ~tching may result in a conductor being over-
etched near its base, thereby undercutting the conductor causing
a nonuniform, mushroom-shaped cross-sectionO Also, photoresist
may become trapped beneath the mushroom ledges~ preventing foil
hidden beneath the trapped photoresist from being etched away.
Over-etching, therefore, makes fine line stability and line width
control extremely difficult to achieve as line and spacing widths
and tolerances grow smaller. Thus, etchlng fabrication methods
can result in multiple conductor line defectsr slgnificantly
reducing board yields, with a consequent upsurge in rejected
printed circuitry which increases final production costs.
Board flatness and dimensional stability are important
characteristics for insuring that printed circuitry maintains
continuous conductive interconnection with component leads and
adjacent boards. However, temperature and pressure fluctuations
that occur during lamination cause the board to warp creating
considerable stresses to develop in printed circuitry mounted on
equipment rails. These stresses cause conductors to break and/or
to ~swim" off the substrate fabricated by prior art methods
because they have poor ductility and do not lay flush with the
circuit board.
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Quality and stability of multiple layer circuit board
packages is also limited by prior art fabrication methods. To
make such packages, lamination bonding layers of insulation must
be sandwiched between circuit board layers to fill voids between
the raised conductor lines and the circuit board substrate.
Filling the voids requires high pressures during the lamination
process which can destructively distort the conductor lines.
Also, even very high pressures cannot insure that the laminate
will fill all of the voids. Ultimately, many voids may remain
within the finished multilayered package which become a
depository of impurities. Such impurities can cause electrical
shorts. Further, the lamination bonding layers and board
substrates may be of different material composition since they
are often supplied by different manufacturers, may be made of
different resins, or come from different manufacturing runs.
- Consequently, the finished multilayer package is not homogeneous.
Lack of homogeneity makes it difficult to set proper drili
speeds, and drill angles in the fabrication of holes through the
multilayers. In some cases the drill speed will be too fast to
cut through the copper causing it to tear, but will be the proper
speed to cut through the insulation. Thus, some of the layers
will have tears, and others will be smooth and some will be
extremely uneven, contributing to degraded board quality while
increasing unit cost.
Achieving high density in printed circuitry also requires
that a uniform, continuous conductive coating be placed on small
diameter holes that are drilled through multilayer packages for
component leads and interconnects. One technique widely known in
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the art for making hole walls conductive is electroless plating,
whereby an electroless metal deposit, usually of copper, is
uniformily coated on the dielectric board substrate. This
technique has the disadvantage of depositing a coating that
has poor adhesion qualities so that additional steps to insure
adequate adhesion are required. Another technique is the
application of a thin electroless coating to the hole wall,
then eletroplating to further build up the conductive surface.
Conventional electroplating techniques, however, cannot access
holes having small diameters and large depths demanded by fine
line, high density printed circuitry. Therefore the prior art
teaches coating very small diameter holes, such as .0115 or less
to~ally by electroless processing which takes a substantial
amount of processing time - 24 hours or more.
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SUMMARY OF THE INVENTION
The present invention includes a method of manufacturing flne
line, high density printed circuit boards and printed circuit
board packages and the circuit boards and packages formed
according to the method. A flash layer of conductive ma~erial,
preferably copper, is electrodeposited onto a rigid metal or
metallized substrate that has a low coefficient of thermal
expansion. A thickness of photosensitive resist is deposited
onto the first layer by silkscreening or other methods known
in the art. A mask is placed over the resist to define a
conductive circuit pattern on the surface of the resist. The
mask is exposed to light, and the resist is developed. Channels
having straight and parallel walls of resist will be formed
defining the conductive circuit pattern duplicating the photo-
mask thereby exposing ~he flash layer.
A second layer of conductive material is built up on the
physically exposed portions of the flash layer of conductive
material within the channels, forming a raised conductive circuit
pattern having a thickness not exceeding the depth of the
channels. The remaining photosensitive resist is then removed
from the flash layer.
The flash layer and the second layer defining a raised
conductive circuit pattern are completely covered with a uniform
layer of insulator laminate material. Pressure is applied to
fully embed the raised conductors in the insular material, such
that the flash layer of conductive material remains in intimate
~nd continuous contaot with the insulator material.
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The flash layer, integrated with the raised conductive
circuit pattern and the insulator material, is separated from the
rigid substrate. The flash conductive layer is then etched away,
so that the conductive circuit pattern embedded in the insulator
material is exposed as laying flush and coplanar with the surface
of the insulator material.
Printed circui~ boards may be formed having embedded
conductors exposed on a single slde. However, a double sided
board may be fabricated if desired, by heat presseing two such
printed circuit boards toge~her, back to back or by embedding
the conductors on both sides of a single boardO
The completed circuit boards are stacked with a layer of
insulator laminate bonding material interposed between each
printed circuit board layerO The multiple layers of printed
circuitry and interposed insulator material are heat-pressed
together to form a homogeneous package of insulator mate.ial
with conductive circuit patterns embedded therein.
To prepare the boards for components and interconnects,
holes are drilled through ~he homogeneous package. The holes
are coated with a thin layer of conductive material, preferably
copper, using an electroless coating method so as to provide
a conductive substrate for electrodepositing additional
conductive material thereon. Using a high impingement speed
electrodepositing apparatus, a continuous and uniform thickness
of conductive material is plated onto the walls of the holes.
A primary object of this invention is to provide a method
for manufacturing fine line, high density printed circuitry
whereby the conductive circuit pattern lays flush and aligned
with its insul~ti~e substrate.
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It is a further object of this invention to provide a method
for manufacturing fine line, high density printed circuitry whereby
the conductor lines have improved ductility characteristics.
It is a further object of this invention to provide a method
for manufacturing fine line, high density printed circuitry that
has improved dimensional stability.
It is a further obiect of this invention to provide a method
for manufacturing fine line, high density printed circuitry
whereby the conductive circuits have a uniform width along its
cross-section.
It is a further object of this invention to provide a method
for manufacturing fine line, high density multiple layer printe
circuit board packages of uniform insulator material which have
flat, stable, warp-free, and void-free characteristics.
It is still a further object of this invention to provide
a method for fabricating fine line, high density printed circuit
board packages having small diameter through-holes of uniform and
continuous conductive wall thickness.
Other objects of the invention will become more apparent
upon a reading of the following description together with the
accompanying drawing in which like reference numerals refer to
like parts throughout.
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BRIEF I)ESCRIpTIO~ OF' THE l)RAWIN~S
Figure 1 is a side view of a substrate with a flash layer
deposited thereon.
Figure 2 is a side view of the substrate in Figure 1, having
a layer of photoresist deposited thereon.
Figure 3 is a perspective view of the assembly in Figure 2
with a photomask aligned thereon.
Figure 4 is a perspective view taken along line 4-4 of
Figure 3 illustrating rectangular channels defining a conductive
circuit pattern developed in the photoresist layer after the
photomask is removed.
Figure 5 is a side view of raised conductor lines deposited
within the photoresist channels onto the flash layer taken along line
4-4 of Figure 3.
Figure 6 is a perspective view of the raised conductive
circuit pattern of Figure 5 after the remaining photoresist is
removed.
Figure 7 is a view taken along line 4 4 of Figure 3 showing
a insulator laminate layer covering the raised conductive circuit
pattern and flash layer of Figure 6.
Figure 8 is a view taken along line 4-4 of Figure 3 showing
the assembly of Figure 7 removed from the rigid substrate.
Figure 9 is a top plan view of the printed circuit board
assembly of Figure 8 with the flash layer etched away thereby
exposing the conductive circuit pattern embedded in and aligned
flush with the insulator laminate.
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Figure lO is a cross-section of the printed circuit board
assembly taken along lines 9-9 of Figure 9.
- Figure ll is a side view of a printed circuit board assembly
with registration holes drilled therethrough;
Figure 12 is a perspective cross-sectional view illustrating
multiple printed circuit boards and insulator laminate layers
interposed therebetween stacked upon a conventional press.
Figure 13 is a perspective view illustrating a homogenous
multi-layer printed circuit board package of the present
invention.
Figure 14 is a partial perspective view illustrating
electrodeposited and electroless plating layers built up on
a interconnect or lead hole of the present invention.
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2S'7~1L
~TAILED DESC~I~TION 0F ~ VENTTON
Referring first to Figure 1, a substrate 10 is comprised of
a material such as stainless steel having a metallized surface
for receiving a flash layer of electrodeposited material. In the
preferred ~x~Lment the substrate is of a rigid me~ or a metallized plate.
However, many other rigid material compositions having sui~able
characteristics may be used~ such as a metallized glass material
for example metallized Pyrex, having a very low coefficient of
thermal expansion. The substrate must a low coefficient of
thermal expansion to insure that when a conductor is placed
thereon, it will not shift or float from its design posit~ons
due to the thermal expansion of the substrate caused during a
subsequent pressing step.
A flash of electrically cor.ducting material 12, preferably
copper, is electroplated onto the substrate 10. The copper flash
12 serves as a base layer upon which further electroplating of
conductor lines may be applied. It also serves as a releasing
material for separating the printed circuitry from the stainless
steel substrate 10 after formation of the printed circuit board
is complete, as will be described in detail hereinbelow.
The flash layer is as thin as can be since h~at transfer
characteristics of a very thin layer tend to rapid heat
dissipation during heating, causing improved conductor line
stability. Consequently, a flash layer of only .0001~ to ~0002"
is deposited onto the substrate in the preferred embodiment.
Furthermore a very thin layer is less wasteful of copper. The
thin electroplated coating is achieved by utilizing an
~22ZS74
electroplating apparatus commonly known as a high impingement
speed plating apparatus, such as is taught in United States
Patent Number 4,174,261 known as RISP, available from Economics
Laboratory, Inc., Osborn Building, St. Paul, Minnesota, 55102.
Alternatively, any conventional electroplating appara~us may be
used for applying the copper flash to the substrate. However, kncwn
oonventional electroplating apparatus generally cannot plate the extremely
thin coating contemplated in the present invention without
causing pinholes and other imperfections, and therefore is not
preferred.
A low contact pressure is desired at the interface bètween
the flash layer and the substrate to facilitate separating the
flash layer from the substrate. Low contact pressure may be
accomplished by using dissimilar materials for the flash and for
the substrate, such as, but not limited to, using a copper flash
with a stainless steel substrate as in the preferred embodiment.
Alternatively, material having similar surfaces may be used if
either material is coated with an impurity for reducing adhesion
at their interface.
In the preferred method of the invention, the printed
circuitry may be fabricated on one side of the stainless steel
substrate, but for multilayer applications may be fabricated on
both sides of the substrate. This facilitates maximum production
output, and allows optimal utilization of electroplating and
other apparatus used in the method.
Referring genei-ally to Figures 2 through 5, a layer of
photosensitive resist material l4, such as Dryfilm, manufactured
by Dupont, is applied to tne copper flash surface 12 of the
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substrate 10 using techniques well known in the art. The
photoresist will be either positive, such that it dissolves when
exposed to light, or negative, i.eO, :it will not dissolve when
exposed to light. A photomask 16 defining a conductive circuit
pattern 18, is placed on top of the photoresist layer 14, by-
techniques widely known in the art. The photomask 16 is aligned
and brought into continuous contact with the surface of the
photoresist 14 to insure a high resolution of the conductive
circuit pattern on the surface of the photoresist 14~ The
photomask masks the surface of the photoresist such that when
it is exposed to light only the areas .n which the conductors
are to be defined are left exposed.
After the photomask 16 is exposed to light, it is removed,
and the photoresist 14 is developed using a commercially available
developer such as Resist Stripper manufactured by Dupont. As a
result, cavities 20, are formed in the areas where the photoresist
14 dissolved exposing the copper flash 12 previously covered by
said photoresist 14 in the defined conductive circuit pattern 18
The walls of cavities 20 are parallel to each other and perpendicular
to the substrate 10, amounting to essentially rectangular channels
running throughout the remaining undissolved photoresist 14
according to the original conductive circuit pattern 18 defined
by the photomask 16.
The entire assembly is placed in a high impingement speed
plating apparatus which in the preferred method is the RISP
apparatus manufactured by Economics Laboratory, Inc., St. Paul,
Minnesota. A conduc:tive material 26, such as copper, is
electrodeposited ont:o the exposed copper flash 12 at the bottom
of the rectangular channels 20, rather than utilizing the
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subtractive etching method as taught in the prior art. The
electrodeposited material 26 is accumulated within the channels
to a desired thickness of about 1.2 to about 15 mils (1.2 mils
thickness of copper per sq. ft. to 15 mil thickness of copper per
sq. ft.), the thickness being selected to prevent mushrooming of
the electrodeposited material as happened in the prior art. ~t
no time, however, should the thickness exceed the depth of the
channels. The additive electroplating step produces conductor
lines 26 having stralght and perpendicular side walls of uniform
cross-sectional width, facilitating fine line resolution, and
making it possible to easily control line widths and densities of
extremely narrow dimension. The use of the RISP apparatus enables
the conductor lines to be plated with speed and unifor~.ity that
is considerably better than can be achieved with conventional
electroplating techniques. Additionally, rapid impingement speed
electroplating produces a very ductile conductor which is critical
in preventing defects and failures in very narrow cross-sectioned
conductor lines.
Referring generally to Figures 5 through 8, the photoresist
layer 14 is chemically stripped away from the copper flash
surface 12 exposing the raised electroplated conductive circuit
lines 26 arranged in pattern 18. A layer of insulating material
32, such as epoxy coated fiberglass, is laminated to the
copper flash layer 12 completely covering the copper flash
12 and the raised conductive circuit pattern 18. Thermosetting
insulator materials such as epoxy coated fiberglass
are utilized because of their low cost
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and good temperature characteristics. If epoxy coated fiberglass
is not used, alternative materials, such as polypropylene,
phenolics, or Teflon material manufactured by Dupont may be used.
The insulating layer 32 is laminated over the conductive
circuit pattern 18 and the copper flash layer 12 by the
application of heat and pressure as required for laminate
material chosen, accomplished with a rigid pattern laminating
press such as manufactured by Pasadena Hydraulic of El Monte,
California. When epoxy coated fiberglass is used this lamination
step can be performed at a pressure of approximately 50-250
pounds per square inch depending on the weave of the glass
fabric. ~Thicker glass requires more pressure to set the epoxy
into the weave) and at a temperature of approximately 425 degrees
Fahrenheit. The insulating material 32 will thereby flow and
completely fill all the voids between the raised conductor lines 26
and will also achieve a strong bond with the conductors. The
insulator material 32 should be of uniform thickness so that the
conductor lines 26 of the circuit pattern 18 will be completely
covered by the insulator material.
The insulator material 32~ in which the conductive circuit
pattern 18 is molded and embedded and which is bonded to the
copper flash layer 12, is manually separated from the surface of
the substrate 10. The copper flash layer 12 is then removed from
the insulator material 32 using conventional etching techniques
or a rapid impingment speed etching apparatus, thereby exposing
the conductors 26 of the circuit pattern 1~ embedded in the
insulator material. Figures 9 and 10 show the resulting printed
circuit bord genera:Lly referred to at 36. As illustrated in
Figure 10, the conductors 26 of circuit
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pattern 18 lays flush and coplanar with the surface 34 of the
insulator material 32, having no abutting edges or protruding
surfaces. Thus, the conductive circuit pattern is totally
restricted and cannot move. This contrasts with the floating
or or shif~ing tendencies that commonly plague printed circui-try
which have been fabricated using prior art methods, having the
conductive circuit patterns raised above an insulator material
base. The embedded conductor configuration that results from
the present inventive method provides a durable and highly stable
assembly, enabling large continuous sheets of printed circuitry
to be manufactured at extremely close tolerances.
The oxide created on the copper conductors does not bond
well to the insulation material. There~ore, the whole board 36
of the conductive circuit pattern 18 is immersed in a chemical
bathl such as commercially available under the trademark Macublack
from McDermott of Waterbury, Connecticut. The chemical coating
improves the adhesion qualities of the laminate, further insuring
that, if the board is stacked, the copper surface of one board
will adhere to the the laminate surface o~ an adjacent board.
This is particularly important for boards with surfaces exposing
mostly copper and thus very little laminate, such as in ground
and power boards.
At this stage of the invented process, a single layer 36
printed circuitry is complete. Having thus manufactured printed
circuitry with the desired conductor patterns, multiple layer
printed circuit packagès may be fabricated. A layer of insulator
material 44 is sand~iched between each layer of printed circuitry
36. This insulator material 44 is of the same composition as
that used in the laminate structure of the printed circuitry.
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Thus, a multiplicity of printed circuit board layers 36 are stacked
atop one another, with interposed laylers of insulator material 4
sandwiched therebetween.
Referring generally to Figures 9 through 13, registration
holes 38 are drilled through each printed circuit board 3~ and
insulation layer 44 that will be included in the multiple layer
printed circuit package. An optically guided sightin~ system,
such as that made by Sportonics, of Rockford, Illinois sites the
target at which the hole should be made and then drills through
the targets such that there is one hole per target. The
registration holes 38 provide mounting means for stacking the
printed circuit boards 36 and insulation layers 44 on mounting posts
4~ so that the multiple layers of printed circuitry will align
securely between a pair of pressure plates 48~(only one illustrated).
The multiple printed circuit board layers 36, with insulator
material 44 sandwiched therebetween, are pressed together between
the pair of pressure plates 48 in a conve~tional press at a
temperature of 375 to 425 degrees Fahrenheit at a pressure of
approximately 250 pounds per square inch to form a multi-layer
package 54. However, in the preferred embodiment, when 50 psi
is used to press a single layer, the same pressure will be used
throughout the process.
Prior art multiple printed circuit packages often have
layers that use insulator materials of different composition, or
made in different manufacturing runs. Fabricating multiple-layer
printed circuit board packages in accordance with the present
method, however, enables the sandwiched insulator material
layers, as well as the laminate base of the printed circuit board
layers, to be composed of the same material. This results in a
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homogenous and continuous material structure when the layers are
heat-pressed together to form a multila~er printed circuit board
packages 54. Also, since the printed circuit board layers of the
present method are flush, having no protrusions or indentations,
fabrication of the multilayer package is accomplished without
voids or other irregularities occurring in the package structure.
Further, because the surface of the each circuit board layer is
flush, lower pressure may be used to form the multilayer package.
The advantage of such low pressure is that warpage or distortion
of the package is avoided during the pressing s~e~.
In the prior art, internal shifting and floating that
results from the use of high pressure during the multilayer
package fabrication step places significant limitations on the
number of circuit board layers that could comprise a single
multilayer package. In the present invention, the combination
of developing a homogenous insul2tor material in the package,
along with eliminating voids through the use of flush printed
circuitry, substantially increases the number of printed circuit
board layers that can be pressed into a single package. The
present method has been regularly practiced on a maximum of 22
board layersr and on a maximum of 40 layers on a more limited
basis. However, the method is not thereby limited, and it is
possible that packages with even a greater number of bo2rds may
be fabricated using the inventive method.
Referring to Fig. 14, interconnect and component lead holes 58
are then drilled through the multilayer package 44 using conventional
drilling means. The holes are generally between .0115 and .093 inches in
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diameter. The holes are then cleaned to removed drill smear
using cleaning means well known in the art or by the rapid
impingement speed plating apparatus.
As generally illustrated in Figure 14, a .000050 inch
thickness of copper 56 is deposited on the hole walls 58 using
a conventional electroless plating process. The copper deposit
serves as a base for providing sufficient conductivity to carry
substantial current for electrolysis. It should be noted that if
this copper layer is too thin, it will simply burn away due to
the heat generated during electrolysis.
Once again, the holes are cleaned and rinsed to remGve
impurities and surface dirt. A ~ond thickness of oopper 60 is then
added electrolytically using the rapid impingement speed plating
apparatus, to build up the desired conductive coating thickness
along the walls of the hole 58. It is critical to this step that
rapid impingement speed plating be used since conventional
electroplating means cannot access the long and narrow diameter
holes to provide a good conductive coating. Further, the use of
the rapid impingement speed electroplating apparatus provides a
copper coating having improved ductility characteristics. Thus,
thermal or other expansion along the vertical axis o~ the hole
will not cause a break in the conductor surface which could
nterrupting current flow.
The present invention is capable of fabricating line
conductor widths and spaces as narrow as 2 mils, package layers
numbering 40 or more having through holes as small as 5 mils in
diameter.
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While certain embodiments of the present invention have
been shown and described above, it will be appreciated that
the invention is not limited thereto. Accordingly, it will be
understood by those skilled in the art that various changes in
form and detail may be made therein without departing from the
spirit of the invention.
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