Note: Descriptions are shown in the official language in which they were submitted.
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ELECTRICAL CIRCUITRY
Back round of the Invention
The present invention relates to electrical circuits
for interconnecting components such as microchips and also
electrical circuits for the microchips themselves.
Background Art
Circuit boards in mass production for consumer and
commercial needs can be printed using silkscreen tech-
piques. Even with routing programs and computer aided
engineering, much time is needed to design, set up
production lines for, and build such boards the design
and set up time requirement means that such boards can only
be produced at competitive prices for orders of thousands
and hundreds of thousands. The costs and time required for
multi-layer board arrangements are even larger.
Accordingly, for custom orders of circuit boards a
wire-wrap technique is generally used. In the wire wrap
technique, a base circuit board is produced which has a
matrix of pins upstanding from one surface thereof and a
matrix of connectors communicating with the pins and
usually upstanding from the other surface of the board.
The matrix of connectors are generally for mounting chip
packages or carriers. The board may have certain basic
electrical pathways redesigned therein which connect
- 25 selected chip packages to each other or to terminals on the
board for purposes of powering, grounding or signal
communication requirements.
To develop a custom board using this arrangement, a
circuit builder would use a wire-wrapping tool which would
; 30 tightly wind a connecting wire around the appropriately
selected pins to provide electric communication
there between. Such a process is quite naturally slow and
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must be done with painstaking skill, otherwise incorrect
pins may be communicated during the wire-wrap procedure.
It has been found that if pins are incorrectly
communicated, many wire must be removed prior to reaching
the incorrectly positioned wire. Also it has been found
that during the wire-wrap procedure, the wire-wrap tool
places stress on the wires such that in some instances the
wire breaks inside the insulation making it impossible to
find the break with visual inspection. Further as even the
same operator will never wire two functionally identical
custom boards in exactly the same manner, visual inspection
is time consuming.
To assist in this wire-wrap process, there are some
semi- automatic wire-wrap machines which provide pointers
which move between the pins which are to be connected with
the wires. The person who is using the wire-wrap tool will
then appropriately communicate the pins with a wire. With
this semiautomatic wire-wrap machine, up to four hundred
wires per hours can be connected between appropriate pins.
A standard five-inch by seven-inch board contains
approximately a thousand pins of which seven hundred are
generally connected during the wire-wrap operation. Thus,
approximately two hours is required to wire the board.
, Fully automatic wire-wrap machines do exist which make up
to twelve hundred connections per hour. Such machines are
considerably more costly than the semi-automatic machines.
On a smaller but not less significant scale, the
design and manufacturer of small orders of custom chips can
be accomplished through the application of, for example,
circuitry to gate array chips during the final metalization
steps. with no more than one or two metalization layers
are placed on the chip, the surface becomes rough and the
electrical pathways themselves can become quite convoluted.
As more layers are put on the chip, the roughness or
three-dimensional effect of the surfaces becomes greater
causing increased difficulty in properly focusing the
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various deposits which are placed on the chip so that they
stay within the bounds intended by the circuit design.
- Thus generally there is a need to provide electrical
circuitry which can be easily fabricated for use with
custom and small order designs both for circuit boards and
chips.
; The present invention is directed to overcoming these
difficulties.
Summary of the Invention
In one aspect of the invention an electrical circuit
comprises a plurality of layers, each including one or more
electrical pathways, each layer including insulating means
for insulating at least part of any one layer from another,
layer, with at least some of the electrical pathways having
substantially repeating patterns and with at asset the
first and second layers having substantially Tao same
repeating patterns. Each pathway of each layer comprises
means for communicating with the pathways of the next
adjacent layer. Some portions of the patterns, including
the communication means, of one layer are at least
partially aligned with some portions of the pattern
including the communication means of another layer with the
one layer moved and repositioned relative to the another
layer and with other portions of the pattern remaining
unaligned.
In yet another aspect of the invention, the electrical
circuit can comprise a single layer including electrical
pathways with repeating patterns.
The method of the invention includes providing an
insulation base and then providing electrical pathways
thereon which are comprised of regular and repealing
patterns. The method further includes the step of
selectively severing portions of the pathways to provide
the desired circuit.
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In another aspect of the invention, the pathways are
severed by the use of a laser. The design of the patterns
themselves is such that at points where it would be
desirable to have the pathway severed, the pathways which
are located on several layers are unaligned. Thus no
matter what layer the pathway is on, the laser can easily
access the pathway without interrupting any other pathway.
In another aspect of the invention, the electrical
pathways include means for receiving pins of wire-wrap
circuit boards. These moans can accept the pins and
provide a proper electrical contact with the pins.
In yet another aspect of the invention, first and
second layers can be interconnected by a third layer of
discrete nodes with communicating means. on this aspect,
the positioning ox the nodes is selected by a programmed
photo plotter so that the appropriate thus are
communicated between the first and second layer. If all
the nodes were selected, a regular grid would be en-
tablished which would communicate with each communication
means of the first and second layers. The photo plotter
selects the appropriate nodes to complete the electrical
circuit and only those are deposited on the third layer.
The present invention can be used with conventional
wire-wrap printed circuit boards without the necessity of
actually wire-wrapping the connections. The circuits are
made using the severing technique indicated above and then
one or more the layers are urged onto the pins of the
wire-wrap board. Thus the circuits are completed in a
minimum of time as compared with the conventional
wire-wrapping technique. Also it should be understood that
if required, after the circuit of the invention is urged
onto the wire-wrap board, that further connections can be
made with the conventional wire-wrap techniques. The
problems associated with wire-wraps such as the time
involved in removing wires when a terminal is incorrectly
connected, and the time involved in locating breaks hidden
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by the insulation due to the stress placed on the wire by
the wire-wrap tool, are solved by this invention.
It should also be understood that the present
invention can be used to replace conventional circuit
boards which are used in other than a wire-wrap
environment.
It is also to be understood that the present invention
can be used for customizing microchips and for other chip
carrier and chip package manufacture. With microchips, the
various layers of the invention are laid down and then a
laser used to sever the pathways as desired to create the
desired electrical circuitry. As the layers are comprised
of substantially repeating patterns, each layer is
substantially level and thus there is less of a resolution
problem or focusing problem which leads to improperly
deposited materials. Also, there kenc1s to be a reduction
in the number of convoluted pathways which cross
excessively between layers.
By f Description of the Drawings
Figure 1 depicts a layer of an embodiment of the in-
mention with repeating electrical pathways.
Figure 2 depicts the electrical pathways of Figure 1
with a laser path described thereon.
Figure 3 depicts the electrical pathway of Figure 1
with select pathways severed.
Figure 4 depicts the electrical pathways of Figure 1
moved one position to the right and superimposed on a
second layer which is identical to the pathway con fig-
unction in Figure 1.
Figure 5 depicts eight layers superimposed on each
other, the two layer set of Figure 4 providing the base
with three similar sets being rotated 90, 180 and 270
with reference to the base and aligned under the base.
Figure pa through oh depict several methods of
severing the pathways.
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Figure 7 depicts pins of a wire-wrap circuit board
positioned above the electrical circuitry of the invention.
Figure 8 depicts several layers of the electrical
circuitry of the invention being in engagement with a pin
5 of the wire-wrap circuit board.
Figure 9 depicts an another embodiment of the pathway
of the electrical circuit with several of the pathways
persevered
Figure 10 depicts a different configuration of the
pathway of the embodiment of Figure 9.
Figure 11 depicts the alignment of the layer of Figure
9 over the layer of Figure 10.
Figure lo depicts a matrix of electrical shunts which
are used with the invention of Figure 11.
Lo Figure 13 depicts a layer ox electrical pathways in
accordance with another embodiment of the invention.
Figure 14 depicts a layer of a plurality of nodes in
accordance with the embodiment of Figure 13.
Figure 15 depicts a perspective view of the electrical
circuit comprised of the layers such as depicted in Figures
13 and 14.
Figure 16 is yet another embodiment of the present
invention.
Figure 17 depicts the layer of the invention of Figure
16 translated and superimposed over a similar layer.
Figure 18 depicts the two-layer configuration of
Figure 17 used as a base with a separate two-layer
configuration rotated by 90 and aligned with the base
configuration.
Figure 19 depicts another embodiment of the invention
wherein a single layer has pathways which are somewhat
similar to the two-layer combination of pathways in Figure
17.
Figure 20 is a combination of two layers, a base layer
similar to Figure 19 which is superimposed over a similar
layer which has been rotated by 90.
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Figure 21 is yet another embodiment of the present
invention.
Figure 22 it an embodiment of the present invention
with the pathways of Figure 21 superimposed over a layer of
pathways which are comprised of a mirror image of the
pathways of Figure 21.
Detailed Description of the Preferred Embodiment
With reference to the figures and in particular to
Figure 1, layer 30 of the electrical circuit 32 of the
invention is depicted. Layer 30 is comprised of an
insulation substrate 34 which can be comprised of a plastic
as, for example, kitten which it a pol~imlda of the
thermo-settlng variety which can be between only and
five miss thick. This particular plastic was selected as
it can be used during a soldering operation and will not
melt, although it does tend to char. Electrical pathways
36, 38 defined on substrate 34. In a preferred embodiment,
the electrical pathways 36, 38 are comprised of copper and
are from one-and-one-eiqhth to one-and-one-half miss thick.
In a preferred embodiment, these electrical pathways are
configured by making a uniform deposit of copper onto the
substrate 34 and then, using photo mask and etching
techniques, removing the undesired copper to leave the
electrical paths 36 and 38. As can be seen in Figure 1,
these electrical paths are comprised of repeating patterns
which include different patterns 40 and 42. Pattern 40 is
similar to pattern 42, however, it includes several more
electrical traces such as traces 44 and 46 Han does the
pattern 42. In fact, a substantial amount of the pattern
40 can be superimposed over and aligned with the pattern
42, with only some of the patterns being nonalignable, such
as for example, the traces 44 and 46 and the traces that
are located on either side thereof. As is evident from
Figure 1, electrical path 36 it first composed of pattern
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40, then pattern 42, and then repeats pattern 40 and can
continue in that arrangement. Pathway 38 is first composed
of pattern 42, then pattern 40, and then repeats pattern 42
and can continue in that arrangement.
Pattern 40 is comprised of a center 1Ower-shaped
communication means 48 through which a pin of, for example,
a wire-wrap circuit board can be inserted so as to expand
the flower without breaking any of the traces and allow for
electrical communication between the pathway and the pin.
As can be seen in Figure 1, the flower is composed of eight
substantially identical wedge-shaped sections 50, pairs of
which are joined together at the center to form quarter
sections of the flower, with the quarter sections of the
flower being joined together at the periphery of the flower
IS to form the entire slower. Due to this w~dge-shaped
arrangement, the center ox the slower can be pushed out or
expanded without disturbing the electrical connection
between the wedge-shaped sections. The pattern 42 further
includes other communication means which include nodes or
junctions 52, 54, 56 and 58. These nodes are placed at 90
intervals about the flower-shaped communication means 48.
Pattern 40 further includes a baseline trace 60 which
communicates with nodes 52 and 58 by previously indicated
traces 44 and 46. Nodes 54 an 56 communicate with
baseline trace 60 by traces 62 and 64, which are accurate
in nature and extend about the flower-shaped communication
means 48, but which are substantially parallel to the
traces 44 and 46 as traces 62, 64 approach the baseline
trace 60. Further, traces Ç6 and 68 communicate the
flower-shaped communication means 48 with the baseline
trace 60. As Will be discussed further hexebelow, nodes 52
through 58 include blind vies which provide communication
between the various layers of the electrical circuit of the
invention, which layers may be situated above or below the
layer as depicted in Figure 1. Plated through holes can be
substituted for the blind vies. It is to be understood
that the flower-shaped communication means do not
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communicate with the other side of the insulation substrate
material as the nodes with the Yip as do.
Further, pattern 40 includes interconnecting means,
such as traces 70, 72, 74 and 76 which interconnect pattern
40 with the other adjacent patterns 42 form a matrix of
patterns 40 and 42.
Pattern 42 is comprised of a similar flower-shaped
communication means 78 with nodes 80 through 86 and base-
line trace 88. Nodes 80, 82, 84 and 86 all communicate
with a common trace 90 which is described about the flower-
shaped communication means 78 and which communicates with
baseline trace 88. The Elower-shaped communication means
78 also communicates with baseline trace 88 through traces
92, 94 and 96. As is evident from the figures, traces 92,
I and 96 of pattern are substantially parallel, as are
traces 44, 46, 66, 68, 61 and portions of traces 62 and 64
of pattern 40. The traces of pattern 40, live along a laser
cut path such as cut path 91 in Figure 2. These traces are
substantially perpendicular to this cut path 92. The same
is true with the parallel traces of pattern 42. They lie
along a laser cut path 93.
As will be more fully described hereinbelow, the
electrical circuitry of the invention can be fabricated
from the pathways 36 and 38 by selectively severing one or
more of the portions of the traces which fall within the
laser cut paths 91 and 93 by using a programmed and pulsing
laser. As for example, in Figure 3 and in pathway 36, and
pattern 40, if it is desired to communicate node 56 with
interconnecting trace 70, the laser would sever traces 44,
62, 68 and 46 and interconnecting trace 76. This altered
pathway is shown by dotted line 98 which is included for
clarity only and does not comprise a portion of the
circuit. Similarly, if it is desired to communicate a
node such as node 56 with node 84, the appropriate traces
are severed, as shown in Figure 3, and line 97, which
again is not part of this circuit but which is included for
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clarity only, shows the pathway which connects node I with
node I
While it is to be understood that single layers be
used for the complete electrical circuitry, it is also the
intent of the invention to use multiple layers such as
layer 30 to comprise the electrical circuitry of the
invention. Thus multiple parallel layers, although
identical in pattern and pattern arrangement, can be moved
with respect to each other to form circuits in the third
dimension. The movement of the layers with respect to each
other can be by translational or notational or mirror image
moves with mirror imaging the electrical patterns would be
produced on the reverse side of the layer. The moves can
also be combinations of all three of these types of moves.
Figure 4 depict a translational movement of the elect
tribal pathways 36 and 38 of the layer 30 ox Figure 1 to
the right and positioned over a second layer 100 which
includes pathway 102 and 104 which are identical to
pathways 38 and 36 respectively. Thus in effect, a pathway
similar to pathway 36 is placed over a pathway similarly to
pathway 38. As can be seen in Figure 4, a great majority
or the patterns of the two pathways are substantially
aligned with, for the most part, the traces which are
parallel and communicate directly with baseline trace 60
and baseline trace 88 being nonaligned. In fact, there is
no overlapping or aligning of the parallel traces which are
directly connected to these baseline trace 50 and 88. The
reason for this is that these traces lie on the laser cut
paths such as cut paths 92 and 94 in Figure 2, and thus the
laser can be pulsed to selectively sever any one of these
traces without severing a trace lying thereunder.
For the pattern in the upper left hand corner of the
electric circuitry in Figure 4, pattern 40 is imposed upon
pattern 42. Nodes 52, 54, 56 and 58 of pattern 40
communicate with nodes 80, 82, 84 and 86 of pattern 42.
Again these nodes include blind vies which communicate the
nodes of the adjacent layer.
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For purposes of identification, the set of first layer
30 and second layer 100 in Figure 4 is identified as 110
and is so indicated in Figure S. Figure S includes eight
layers of pathways which are identical to the first layer
which is shown in Figure 1. Each of these layers is
rotated or translated with respect to the first layer 30.
To more conveniently describe Figure 5, the set of layers
110 in Figure 4 is so identified in Figure 5 and similarly
position. The other six layers are comprised of two layer
sets which are similar to Figure 4 but which have been
rotated 90, 180 and 270 from the first two layer set
110. These sets are identified as 112, 114 and 116
respectively.
The electric circuitry of the invention can be
~abrlcated in one of several ways. As shown in Figure pa ,
and b, the circuitry is composed ox four layer, 113
through 132. The cross-section shown it to be taken along
a laser cut path. The traces in the laser cut path are
identified by the number 111, 113, 115 and 117.
These traces are parallel and unaligned. In this
arrangement, the layers which are located above each of the
traces have a window provided therein so that there is an
open column above each of the traces. A laser such as
laser 134 can be positioned above the appropriate trace and
used to sever that trace, as is indicated in Figure 6b.
The laser is controlled by a writing program which can
be selectively programmed according to the circuitry
requirements so that the laser pulses and severs the
appropriate traces.
The same arrangement is shown in Figure 6c with no
windows provided above the traces to be severed. In this
situation, the substrate would be transparent to the laser
emission which would selectively sever the appropriate
trace as shown in Ed. It is also possible to have a laser
of one wavelength used to burn a hole in the substrate and
then have a laser of a different wavelength used to sever
the trace. With respect to Figures ye and f, a laser is
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provided for simply burning through the substrate and the
trace with one blast. Again it is to be remembered that
circuitry including a single layer can be made in the above
manner .
Once one or more layers of the the circuitry is
completed and appropriate traces are severed, a circuit
board which is used for wire wrapping purposes, such as
board 140 in Figure 7, is positioned over the first layer
142 of this circuit with the pins 144, 146 positioned above
the centers of the flower-shaped communication means such
as means 48. A backer board 148 is positioned underneath
the layer 142 or can be initially associated with the
layer. The pins are forced down into communication with
and pierce the flower-shaped communication means so that
good contact is made (Fugue). this simple process
eliminates the entire need for using the prior art
wire-warp technique. However, it is to 'ye unrated that
should additional circuits be required in the hoard, that
the traditional wire-wrap technique can be used in
combination with circuit board 142 by simply wrapping the
wires around the pins 144 and 146 which extend beyond layer
142.
It is to be understood that the backer board can be
removed and additional layers can be forced onto the
wire-wrap pins with the backer board left on with the last
layer. Also the backer board can be left on with each
layer. Further it is to be understood that the fit between
the backer board and the pin is essentially a forced fit
with the pin being rectangular or circular and larger than
a circular hole being provided through the backer board.
As the cover deposit 150 is on the upper surface of each
layer 142 the pathways are placed in intimate contact with
the pin during this force fit.
It is to be understood that this embodiment can be
used to provide electrical circuitry without the use of
wire-wrap boards as is contemplated by some of the
following embodiments.
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Another embodiment of the invention is shown in
Figures 9 through 12. This embodiment includes a first
pattern 200 which is similar to pattern 40 in Figure 1
except for the fact that the parallel traces 202 through
218 are severed or have a discontinuity with nodes such as
nodes 220 and 222 defining each end of the discontinuity.
These nodes include plated through holes which communicate
with the other side of the insulating material. Blind vies
could also be used. This pattern additionally includes
free nodes such as nodes 224, 225, and 226 which relay
communication with other patterns of other layers. Figure
10 depicts a pattern 230 which is substantially similar to
pattern 42 of Figure 2. Pattern 230 includes traces 232,
234, and 236 which are discontinuous and which have nodes
such as nodes 238 and 240 which include plated through
holes. With the pattern of Figure 9 imposed upon the
pattern ox Figure 10 a depicted in Figure 11, a
substantial amount of the patterns are aligned, with the
unaligned portions remaining the traces as in the previous
embodiments. It is to be understood that the free nodes
224 and 225 of the pattern 200 in Figure 9 align with the
nodes 238 and 240 at the end of the discontinuous trace
232. The nodes at the discontinuous traces and the free
nodes form columns which communicate to the upper surface
of the last layer. The final layer, which includes a
plurality of discreet shunts such as shunt 242 (Figure 12)
and which included blind vies or plated through holes, is
then placed on top of the upper layer of the previous
layers of patterns in order to complete the circuitry. A
laser such as laser 244 can selectively sever the isolated
shunts such as shunt 242 without having to penetrate the
remaining layers as shown in Figure oh.
With the exception of the above indicated discrete
shunts, the construction and method of use of this
embodiment of the invention is identical to the embodiment
shown in Figures 1 through 5.
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- It is to be understood that in both of these embody-
mints, the layers can perform if disarrayed a separate
function. For example, one layer can be essentially
provide voltage while another layer can be a ground plane.
Other layers can be exclusively signal layers. Further it
is to be understood that as the layers are relatively thin
and as the electric circuit which is comprised of one or
more layers is itself relatively thin, redundant circuitry
can be built into a system with relatively little cost and
small space requirements, simply by adding redundant
layers.
Another embodiment of the invention is shown in
Figures 13, 14 and 15. This embodiment includes a first
layer which has a substrate ox a isolation material upon
which is deposited discreet isolated pathways, such as
pathways 246, 248, 250, 252, 254 and 256. Pathways 243,
252, 254 and 256 are essentially straight parallel
pathways, and pathways 246 and 250 are straight parallel
pathways, with pathways 246 and 250 substantially
perpendicular to the above pathways. Interspersed between
the pathways are nodes which include node 258 and 260 with
are shown as blind vies but which could be plated through
holes. It is to be understood that many other patterns of
pathways can be constructed for ~11 or some of the layers
of multi layer circuitry, as for example, having each
discrete pathway be replaced by two similar and parallel
isolated pathways and be within the scope and meaning of
the invention. All of the other layers which comprise the
circuitry of this embodiment can be comprised of the
identical same pattern as is provided on the layer in
Figure 13, but which have been displaced through
translation, rotation, or mirror imaging relative to the
layer shown in Figure 13~
In this embodiment, an intermediate layer between any
two layers such as constructed in accordance with Figure 13
is provided to communicate between these two layers. Such
an intermediate layer is shown in Figure 14. Figure 14 is
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essentially comprised of a matrix of potential locations
which can have copper deposited thereon through use of a
masks made from a photo plotter, which are used to
communicate the layer immediately there above with the layer
immediately there below. The dotted lines indicate areas
where no copper was deposited but where copper could be
deposited in order to make the various communications. The
solid squares indicate where copper was deposited.
Figure 15 shows a circuit comprised of three layers,
the upper layer 270 being identical to the layer of Figure
13, and the lower layer 272 hying identical to the layer
270, but translated and repositioned with respect to upper
layer 272 to form, with the cooperation of thy pattern of
Figure 14, which forms the intermediate layer, certain
pathways. A can be seen in Figure 15, two separate and
discreet pathways are wormed. The first pathway I
includes a first trace 276 r which through node 278 acts as
a junction and fans out to three traces, 280, 282 and 2R4.
Nodes 286 and 288 and also 290 and 292 which are defined in
the pattern of Figure 14 provide the necessary
communications between the upper layer 270 and the lower
layer 272 to accomplish the fan-out from a single trace to
three traces. In this embodiment, as is evident, no laser
cutting is required. ;
A second pathway 292 crosses the pathway 274. This
second pathway 2g2 is formed in the same way as pathway 274
in that the isolated shunts of each of the upper and lower
layers are connected through the nodes of the intermediate
layer. Where the pathway 274 and 292 cross, no node is
formed immediately between the discrete shunts 294 and 296.
Thus second pathway 292 does not communicate with pathway
274.
- As is evident from Figure 15, the nodes, which are
located between the shunts, only communicate with the nodes
I of other layers. These nodes can be all communicated
through a common ground plane and can form shields between
the various circuits.
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An electronic circuit of the invention using this
embodiment can be fabricated in the following way. First,
layers similar to the layer in Figure 13 are made much in
the same way the layers in Figure 1 are made. Then a
photo plotter is used to provide the necessary mask to make
the layer in Figure 14, according to the circuitry desired,
which is then fabricated similarly to Figure 1. The layers
are then mated, and the mated layers forming the electrical
circuits are in turn mated to a circuit board to which can
be mounted the chips and other components of the circuit.
Additionally if the required, the chips, or packages or
carriers can ye mounted directly to the upper layer of the
electrical circuitry.
Further it it to be understood that layers similar to
those in Figures 13, 14 and 15 can be used for producing
the final metallization layers of or example a gate array.
As each layer is substantially uniform, these me~allization
layers are less rough than those currently used in gate
array technology, and thus the focusing and deposition
problems which occur after two metallization layers have
been deposited on the gate array are of little
significance. Further there is less likelihood that any of
the circuits will have to snake around excessively in order
to provide the necessary connections. These layers would
be made using standard fabrication techniques known n the
industry.
In another embodiment of the invention as shown in
Figures 16, 17 and 18, the first layer is comprised of a
plurality of identical and continuous but isolated pathways
302 through 308. Each of these pathways is comprised of
repeating S-shaped patterns. Each pathway includes a
projecting trace such as traces 310 and 312, which include
at the end thereof nodes such as 314 and 316 with plated
through holes which communicate with the other surface of
the layer. Located opposite each of the projecting traces
such as traces 310 and 312 are isolated nodes such as nodes
318 and 320. Each of these nodes includes a plated through
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hole which communicates with the other surface of the
layer.
figure 17 includes a composite of a first layer 322,
which is composed of traces which are oriented in a manner
similar to those in Figure 16, which is superimposed on a
second layer 324 which is similar to the layer of Figure 16
but which has been translated over and up in order to form
substantially hourglass patterns between the two layers.
It is noted that the projecting traces 326 and 328 with the
associated nodes 327 and 329 of the pathway 325 of the
first layer 222 communicate with the isolated nodes 330,
332 of the pathway 334 of the second layer 324.
In Figure 18 a two-layer configuration of Figure 17 is
used as a base configuration 340 with projecting traces 310
and 312. This configuration it superimposed over another
configuration which is similar to Figure 17 but which has
been rotated by 90 and includes projecting traces 342 and
344 which communicate with the other traces 310 and 312
with the appropriate nodes such as nodes 320. 322. This
arrangement of four layers of pathways such as pathway 30
in Figure 16 produces an alternating pattern of large
octagons 346 and adjacent squares 348.
As depicted in Figure 18, no two traces such as traces
310, 312, 342 and 344 are located under or over another
trace, and all these traces describe laser cut paths such
as cut path 348. Thus a laser can be used to selectively
sever the traces to form the appropriate electrical
circuitry. Also it should be understood that the sections
of the pathways which form the squares such as square 348
are all on separate layers and also that they are not
aligned within the other pathway which is located above or
below. Thus these portions of the pathways are prime for
being severed, if required, by a laser.
Such circuitry is principally used in non-wire-wrap
situations, although with the addition of the lower shaped
communication means located in the octagonal portions,
wire-wrap board usage is made possible. gain, as with the
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previous embodiment, this embodiment can be used to
construct the metallization layers of a gate array.
Figure 19 is similar to Figure 17 except for the path-
ways 400, 402, 404 and 406 that are all located on the same
S layer. Further nodes which include plated through holes
are located at every position where the pathways change
direction. As, for example, one S-shaped portion 408 of
pathway 400 includes nodes 410, 412, 414 and 416.
The configuration of Figure 20 is quite similar to
that of Figure 18, with each square configuration, such as
configuration 418, having a node, such as nodes 420 through
426, at each corner, which allow these two layers to
communicate with each other. As in the embodiment in
Figure 18, laser cut pus, such as 428 and 430, can
lo selectively sever the portions of the pathways which are
located between the nodes to create the various desired
electrical circuitry. Again it should be noted that none
of the portion of the pathways which are located between
these nodes are aligned with any other pathways. Thus the
laser can conveniently sever that portion of a pathway
without interrupting any other pathway.
Finally the embodiment as shown in Figures 21 and 22
includes a first layer 500 which has pathways 502, 506 and
508. Each pathway includes selected nodes such as nodes
510, 512 and 514 which occur on the slanted portions of the
S-shaped pattern. This type of an arrangement is
especially useful for mirror imaging, as is shown in Figure
22. In Figure 22, the first layer 500 is superimposed upon
a second layer which is comprised of a mirror image of a
first layer. The nodes, with plated through holes,
communicate the first layer 500 with the second layer 514.
It is to be understood that in a mirror image situation, a
mirror image of the layer must be produced on a second
layer, and that the second layer cannot be merely flipped
over. In this arrangement, the mirror image effect can be
acquired be simply rotating one pathway be 180 with
JOHN/PATENT ASP
JOHN-3726 SUM
10/31/83
. . .
~l223~
-19-
respect to a second pathway to produce the mirror image
effect.
Again the electrical circuitry depicted in Figure 22
can be fabricated and used in much the same manner as the
circuitry depicted in Figures 16 through 20.
It is further to be understood that during the step
where a laser is used to sever the pathways, the laser can
be appropriately defocused and used to burn or char the
isolation material so that the appropriate identifiers can
lo be placed on the circuitry to locate where components are
to be mounted and connections are to be made.
Other aspects, objects and advantages of the invention
can be discerned from a study of the figures and the
appended claims.
JOHN/PATENT ASP
JOHN-3726 SUM
10/31/83
