Note: Descriptions are shown in the official language in which they were submitted.
RD-13175
IN~-ERSION-MODE INSULATED-GATE GALLI~M ARSENIDE
FIELD-EF~ECT TRANSISTORS
_ .
BACKGROUND OF THE INVENTION
-
The present invention relates to
inversion-mode (i.e. normally-off) insulated-gate
field-effect transistor devices employing gallium
arsenide, which is a high-voltage, low-resistance
semiconductor material having a number of desirable
charateristics. The invention more particularly relates
to such devices for power switching applications.
Insulated-gate field-effect transistors
(IGFETs) are advantageous in many applications due to
their rapid switching speed and the fact they can be
fabricated to have a high breakdown voltage (e.g. 500
volts), particularly in various vertical-channel
configurations such as vertical-channel ~MOS and
vertical-channel VMOS. Moreover, a normally-off
characteristic may readily be realized. Particular
forms of these devices are known as metal insulator-
semiconductor field-effect transistors (MISFETs) and
metal-oxide-semiconductor field-effect transistors
(MOSFETs). Nearly all power MOSFETs employ silicon ~Si)
as the device semiconductor material.
Gallium arsenide (GaAs) is an alternative
semiconductor material attractive for several reasons.
For example, gallium arsenide has an electron mobility
~5 five times higher than that of silicon, a higher
saturation velocity t and a wider energy gap. In short,
gallium arsenide may be characterized as a high-voltage,
low resistance semiconductor material.
It may be noted that GaAs i5 a Group III-V
semiconductor inasmuch, in the periodic table of the
elements, Ga is in Group III and As is in Group V. It
may further be noted that there are other Group III-V
~ ~23g~
RD-13175
semiconductors having charac~eristics related in some
res~ects.
However, certain characteristics of gallium
arsenide, discussed next below, make the fabrication of
practical GaAs devices difficult. As a result, despi'e
the above-noted advantageous characteristics of gallium
arsenide, its actual use has primarily been limited to
Schottky-gate metal-semiconductor field-effect
transistors (MESFETs). MESFETs, like junction
field-effect trànsistors (3FETs), are primarily
depletion-mode (normally-on) devices. In
depletion-mode FETs, a conduction channel exists between
source and drain in the absence of gate voltage. To
turn the device off requires the application of
gate-voltage of the appropriate polarity to induce a
depletion region to pinch off the channel. This
normally-on characteristic is a disadvantage in many
circuit applications.
On the other hand, an inversion-mode
(normally-off) FET has a channel layer which is normally
not conducting. This channel layer is defined in a
semiconductor region of opposite conductivity type
compared to the source and drain regions, which region
of opposite conductivity type may be termed a shield
base or, simply, base region. The channel layer is
actually deined only when induced under the influence
of gate voltage, which produces an inversion region. In
an inversion-mode FET the gate electrode must be
insulated from the semiconductor body of the FET.
As noted above, insulated-gate FET technology
is well-developed in the case of silicon devices. In
such devices, native oxide, i e. SiO2 f serves very
well as a gate insulating layer.
On the other hand, while it is possible to
form inversion layers in gallium arsenide under
--2--
~L2~3~7~
RD-13175
insulators, obtaining good interface properties (low
surface state densities) between insulators and gallium
arsenide has proven to be difficult. Thus, the
conduction properties of such inversion layers are poor.
These problems are addressed, for example, in T. Ito and
Y. Sakai, "The GaAs Inversion-Type MXS Transistors",
Solid-State Electronics, Vol. 17, ppO 751-759 (1974),
which discusses interface properties between GaAs and
various insulators such as SiO2, Si3N4 and
Al2O3 films. All of these interfaces show
instabilitles, i.e., hysteresis and time drift of
capacitance-voltage curves, and further, abnormal
frequency dispersion of the capacitances. The solution
proposed by Ito and Sakai is to employl as the gate
insulator, a chemically vapor deposited double layer
film of Al2O3 and SiO2. For further background,
reference may be had to the following literature
reference which identifies several reports of the
fabrication of GaAs MOSFETs: C.W. Wilmsen and S. Szpak,
"MOS Processing for III-V Compound Semiconductors:
Overview and Bibliography", Thin Solid Films, Vol. 46,
pp. 17-45 (1977)-
~ here are other III-V semiconductors which
have interface properties superior to GaAs and in which
inversion regions under gate insulators may more readily
be formed. For example, see D.L. Lile, D.A. Collins,
L~G. Meiners and L. Messick, "n-Channel Inversion-Mode
InP M.I.S.F.E.T.", Electronics Letters, Vol. 14, No. 20,
pp. 657-659 t20 September 1978). Lile et al. discuss
the great potential of microwave transistors based on
III-V compounds, and point to several problems in the
use of GaAs. Lile et al. propose and report on the
performance of InP as an alternative 5emiconductor
material. InP has interface properties superior to
--3--
RD-13175
those of GaAs, and shares some of the advantageous
characteristics of GaAs.
Similarly, another InP inversion-mode device
is reported by T. Kawakami and M. Okamura,
"InP/Al2O3 n-channel Inversion-Mode M.I.S.F.E.T.S
~sing S~lfur-Diffused Source and Drain", lectronics
Letters, Vol. 15, No. 16, pp. 502-504 (2 ~ugust 1979).
Another III-V semiconductor material is
proposed in A.S.H. Liao, R.F. Leheny, R.I. Nahory and
J.C. DeWinter, "An InO 53Gao 47As/Si3N4
n-Channel Inversion Mode MISFET", IEEE Electron ~evice
Letters, Vol. EDL-2, No. 11, pp. 288-290 (1981). Liao
et al demonstrate that inversion layers under a gate
insulator can be formed in GaxInl_xAs where x =
0.47.
While InP and GaxIn1_xAs have the
property that inversion layers may more readily be
formed, they are not as good as GaAs in terms of being
high-voltage, low resistance semiconductor materials
when all three contributing factors are considered-
electron mobility, saturation velocity, and energy gap.
In particular, the electron mobility of ~nP, while
greater than that of Si, is only about half that of
GaAs. Also, the bandgap of InP is somewhat less than
that of GaAs, although it is greater than the~bandgap of
Si. The on-resistance of a GaAs device is lower than
the on-resistance of an InP device by a factor of about
2.5.
The on-resistance of Ga~s is lower than that
of GaxIn1_xAs, in particular where x = 0.47, by a
factor of about 3.5. This is primarily due to the lower
bandgap of GaxIn1_xAs, which is only about
two-thirds of that of Ga~s, although the election
mobility of GaxIn1_xAs (x -- 0.47) is sligntly
higher than that of GaAs.
--4--
.
RD-13175
SUMMARY O~ THE INVENTION
_ _ _ _ _
Accordingly, it is an object of the inventio:~
to provide high-voltage power MISFET semiconductor
structures employing gallium arsenide, with its
S relatively high electron mobility, high saturation
velocity, and wide energy gap.
Briefly, and in accordance wi~h an overall
concept of the invention, inversion-mode insulated-gate
field-effect transistor structures are provided wherein
the drain region comprises gallium arsenide and wherein
the gate-controlled channel structure comprises another
semiconductor material in which it is easier to form
suitable inversion regions. In a power MISFET, the
drain region more particularly comprises a relatively
thick ~e.g., 10 microns), lightly-doped (e.g. N )
drift region and a separate heavily-doped (e.g. N+)
drain terminal region. Significantly, the properties of
the N drift region largely determine the breakdown
and conduction characteristics of the overall device.
The N- drift reyion supports the relatively high
voltages across a MISFET device when it is not
conducting and, during forward conduction, the N-
drift region minimizes the voltage drop across the
device by maintaining a uniform field to achieve
velocity saturation. Saturation velocity varies for
semiconductor materials, and is particularly high for
Ga~s.
Thus, the lightly-doped GaAs drift region is
combined with a gate-controlled channel structure
comprising an easily inverted semiconductor film formed
over the GaAs high voltage drift region. Typically,
this film or layer is about 5 microns thick. In
particular, t~e gate-controlled channel structure of the
subject devices comprises InP or GaInAs. Presently
preferred is a graded GaInAs layer.
--5--
, .
RD-13175
More particularly, an inversion-mode
ins~lated-gate field-effect transistor in accordance
with the invention comprises so~rce and drain regions of
one cond~ctivity type, for example, of N conductivity
type, separated by a shield base region of the opposite
conductivity type, in this example, P conductivity type.
The drain region in turn further comprises a relatively
lightly doped ~e.g. N ~ drift region defining a PN
junction with the shield base region, and a relatively
heavily-doped (e.g. N+) drain ter~inal region
contiguous with the drift region and spaced from the
shield base region by the drift region.
The shield base region includes a channel
layer extending between the source and drain regions. A
gate electrode is insulatively spaced from the channel
layer and configured for inducing in the channel layer,
when gate voltage is applied~ an inversion channel
conductively coupling the source and drain regions.
At least a portion of the drain region
comprises gallium arsenide, and at least a
channel-supporting portion of the shield base region
comprises a semiconductor material other than gallium
arsenide and within which inversion regions may more
readily be formed. The channel layer is accordingly
included in the channel-supporting portion. As noted
above, the shield base region, or at least the
channel-supporting portion therof, may comprise InP or
GaInAs.
In one particular device structure of the
invention, which may be described as a vertical-channel
recessed-gate structure, a semiconductor body has a pair
of opposed principal surfaces, and the drain, shield
base and source regions constitute successive layers of
alternate conductivity type within the semiconductor
body. The drain region extends to one of the principal
--6--
~3~7~
RD-13175
surfaces (e.g. lower surface) and the source region
extends to the other of the principal surfaces (e.g.
upper surface). The drai~ region in turn further
comprises a heavily-doped N+ terminal règion
immediately adjacent the one principal surface, and
a lightly-doped M- drift region extending between the
N+ drain terminal region and the P type shield base
layer.
At least one recess is formed in the body
extending from the other principal surface through the
source and shield base regions. In accordance with
usual "VMOS" fabrication techniques, the recess may
comprise a "V"-shaped or a "U"-shaped groove.
Alternatively, in the case of InP source and shield base
regions, an inverted trape~oidal groove may be formed
employing appropriate preferential etching techniques.
To provide a gate-controlled structure within
the non-GaAs p~rtion of the device, the channel layer is
defined in the shield base region adjacent the sidewalls
of the recess. The gate electrode is thus located in
the recess and insulatively spaced from the recess
sidewalls.
Another particular device structure, and one
which is presently preferred, is of double-diffused MOS
~MOS) configuration. This device structure also
comprises a semiconductor body having a pair of opposed
principal surfaces In this case, the semiconductor
body includes first and second layers. However, these
first and second layers are of different semiconductor
materials, and are not necessarily co extensive with any
of the drain, shield base and source regions of the
device.
The first layer comprises gallium arsenide and
extends into the body from one of the principal
surfaces, e.g., from tne lower principal surface. The
--7--
,
~z~
RD-13175
second layer comprises a graded semiconductor layer
extending from an interface with said first layer within
the body to the other of the principal surfaces e.g., to
the upper principal surface. In particular, the graded
second layer comprises gallium arsenide at the interface
and comprises gallium indium arsenide (GaInP) at the
other principal surface, with the percentage of indium
increasing from substantially zero at the interface to a
maximum concentration at the other principal surface.
More specifically, the graded second layer comprises
GaxIn1_xAs, wherein x ranges from about 1.0 at
the interface to about 0.47 at the other principal
surface.
The W conductivity type drain region compriseC
at least a portion of the first layer and also comprises
a portion of the graded second Iayer. The lightly-doped
drift region of the drain region extends to the other
principal surface, and is not co-extensive with either
the first GaAs layer or the graded second layer.
The P conductivity type shield base region is
formed within the drain region, for example, by
conventional diffusion techniques, and extends at least
into the graded second layerO In a preferred device
form, the P conductivity type shield base region extends
completely through the graded second layer and slightly
into the Ga~s first layer. In either case, the shield
base region has a periphery terminating at the other
~upper) principal surface.
The M+ source region is conventionally
formed within the shield base region and has a periphery
terminating at the other (upper) principal surface
within and spaced fro~ the periphery of the shield base
region so as to define the extent o~ the channel layer.
The channel layer accordingly terminates a~ the other
~8--
36~;2
RD-13175
(upper) ~rincipal surface, where the concentration of In
is the highest.
Finally, the insulated gate electrode is
formed over the channel layer. Thus, the interface
between the gate insulator and the semiconductor
material is with GaInAs, i.e. GaO 53InO 47AS.
BRIEF DESCRIPTION OF THE DRAWINGS
While the novel features of the invention are
set forth with particularity in the appended claims,
the invention, both as to organization and content, will
be better understood and appreciated, along with other
objects and features thereof, from the followiny
detailed description, taken in conjunction with the
drawingsl in which:
FIG. 1 is a diagrammatic cross-sectional view
of the active portion of a vertical-channel VMOS device
in accordance with the invention and employing InP in
the gate-controlled channel structure;
FIG. 2 is a cross-sectional of a similar
device wherein, rather than "V"-grooves, grooves of
inverted trapezoidal shape are employed;
FIG. 3 is a cross-sectional view of a DMOS
device structure in accordance with the invention
employing a first layer of GaAs and a second layer of
graded GaxIn1_xAs; and
FIG. 4 is a cross-sectional view of a device
similar to the FIG. 3 device but wherein the P
conductivity type shield base region does not extend all
the way through the graded second GaxIn1_xAs
layer.
DETAILED DESCRIPTION
Described next below with reference to FIGS. 1
and 2 are device structures combining a GaAs drift
RD-13175
region a~d a gate-controlled s~ructure comprising InP.
Thereafter, certain shortcomings of the GaAs/InP devices
are noted, and device structures combining a Ga~s drift
region and a gate-controlled struc~ure comprising
GaxIn1_xAs are described with reference to FIGS.
3 and 4.
GaAs/InP Embodiments
Referring now to FIG. 1, an N-channel,
"V"-groove enhancement-mode gallium arsenide
field-effect transistor in accordance with the invention
comprises a semiconductor body 10 having a pair of
opposed principal surfaces 12 and 14. Formed within the
body 10 are so~rce and drain re~ions 16 and 18 doped
with appropriate N-type impurities and separated by a
shield base region 20 doped with appropriate P-type
impurities. More particuarly, the source region 16
comprises an N+ (heavily-doped to N conductivity type)
source region. The drain region 18 in turn comprises an
N (lightly-doped to N conductivity type) drift region
22 defining a PN junction 24 with the shield base region
20, and an N+ (heavily-doped to N conductivity type)
drain terminal region 26 contiguous with the drift
region 22 and spaced from the P shield base region 20 by
the N drift region 22. Source 28 and drain 30 device
main terminals are respectively connected to source and
drain metallization layers 32 and 34 which are
respectively preferably in ohmic electrical contact with
the device N+ source region 16 and the device N+
drain region 26.
It will be appreciated that the FIG. 1 device
comprises a plurality of substantially identical unit
cells, preferably elongated unit cells defined by
suitably-etched recesses in the form of grooves 36
extending into the body 10 from the upper principal
--10--
3~
RD-13175
surface 14, as is generally conventional practice in
V~OS devices. The grooves 36 extend completely through
the N source 16 and P base 20 regions; and
channel-supporting portions 38 of the P base 20 regions
intersect sidewalls 40 of the grooves 36. The unit
cells have individual source and gate terminal
metallization layers connected electrically in parallel
among the various unit cells, and share a common drain
terminal metallization layer 34.
For selectively inducing an inversion channel
region 42 conductively co~pling the N+ source 16 and
the N drift 22 regions, a gate electrode 44,
typically of metal such as aluminum or gold, is provided
and spaced from the semiconductor material comprising
the channel region 42 by an insulating layer 46. When
the device is off, the channel region 42 i5
indistinguishable from the bulk of the P base region 20.
When positive gate voltage is applied (with reference to
the source and for the representative N-channel device),
an N conductivity type inversion region is formed in the
channel layer 42 from the sidewall 40 surface facing the
insulated gate electrode 44.
At least a portion of the drain region 18
comprises gallium arsenide. (In the case of the FIG. 1
device, this portion comprises substantially the entire
drain region 18.) In cont~rast, at least the channel
supporting portion 38 of the P conductivity type shield
base region 20 comprises a semiconductor material other
than gallium arsenide and within which inversion regions
may more readily be formed. The channel layer 42 is
included in the channel-supporting portion 38. In the
case of the FIG. 1 device, the entire shield base region
20 comprises a semiconductor material other than gallium
arsenide, but this is not an essential aspect of the
invention. What is essential is that at least the
~;2236 7Z
RD-13175
portion 38 of the shield base region 20 which supports
the conduction channel 42 induced by inversion under the
influence of gate voltage is not gallium arsenide.
In FIG. 1, the shield base re~ion 20 comprises
S either InP or GaInAs. As noted above, it is easier to
form inversion regions in both of these materials
compared to GaAs.
The nature of the FIG. 1 device may be further
understood in view of an exemplary process for
fabricating the device.
Device fabrication begins with an N+ GaAs
substrate which corresponds to the drain terminal region
- 26 in the completed device. A typical impurity
concentration is 1018 dopant atoms per cm3. To
enable subsequent preferential etching, the substrate
has a (100) crystalographic orientation.
Next, an N or N type GaAs layer is
expitaxially grown, this epitaxial layer corresponding
to the N- drift region 22 in the completed device of
FIG. 1. A typical doping concentration is 1017
dopant atoms per cm3, although a lower concentration
is required to achieve high breakdown voltages. This
N- epitaxial layer comprising the drift region 22
contributes significantly to the relatively low
on-resistance of the device due to its low electrical
resistance. A typical thickness of the epitaxial layer
22 is 10 microns.
Next, a P-type epitaxial layer is grown which,
after a subsequent etching step, comprises the P
conductivity type shield base regions 20. This P-type
layer, however, does not comprise GaAs. Rather, as
noted above, the P-type layer comprises a different
material within which inversion layers may more readily
be formed. A typical example is InP, with a doping
concentration ranging from about 10l5 to 10
-12-
36~Z
RD-13175
dopant atoms per cm3. A typical doping concentration
is 5 x 1015 cm3. A typical thickness is about 10
microns. It may be noted that InP has a lattice
constant of 5.869 Angstrom~ and GaAs has a lattice
constant of 5.654 Angstrom. This difference in lattice
constant does not prevent epitaxial growth of InP over
GaAs. It does, however, result in the generation of
some dislocations in the InP layer.
As a final epitaxial growth step, a
heavily-doped N+ layer comprising InP is grown over
the P-type layer 20 to ultimately form the device source
regions 16. Doping concentration for this layer is
preferably in excess of 1018 dopant atoms per
cm3.
At this point in the fabrication process, the
device simply comprises multi layered wafer with a PN
hetrojunction 24 within tne device.
The remaining masking, preferential etching,
and electrode-forming steps proceed in a relatively
conventional manner as follows.
In particular, the wafer is first coated with
an insulating layer 48 such as silicon nitride or
phosphosilicate glass. Elongated windows 50 are opened
in this insulating layer by a suitable masking and
etching step. To form the groove 36 configuration of
FIG. 1, these windows 50 must be oriented perpendi~ular
to the (110) flat. ~ext, the InP layers are
preferentially etched with a mixture of H2SO4,
H2O2 and H2O to create the groove configuration
depicted in FIG. 1, which may be described variously as
a flat-bottomed "V"-groove, a "U"-groove, or a
trapezoidal groove. So that the ultimate gate electrode
44 can induce an inversion channel region along the
entire length of the channel layer 42 between the source
16 and drain 18 regions, the grooved recesses 36 must
-13-
RD-13175
extend entirely throu~h the upper InP N+ and P layers"
i.e., entirely through the N+ source 16 and P base 20
regions. It may be noted that the preferential etch
step undercuts the upper insulating layer 43 to form
overhangs 52.
Next, a suitable gate insulator film 46 is
grown or deposited on the interior surface of the
groove, in particular, on the sidewalls 40 thereofO As
described hereinabove, inversion of InP can be
accomplished through gate insulator films of SiO2 and
Al2O3 deposit~d by chemical vapor deposition.
Suitable techniques are described in the literature:
for example, see a~L. Lile, D.A. Collins, L.G. Meiners
and L. Mesnick, "n-Channel Inversion-Mode InP
M.I.S.~.E.T.", Electronics Letters, Vol. 14, No. 20 (28
_ _ _
September 1978); and T. Kawakami, and M. Okamura
"InP/AI2O3 n-Channel Inversion-Mode M~I.S.F.E.T.S
Using Sulphur-Diffused Source and Drain", Electronics
Letters, Vol. 15, No. 16, pp. 502-504 (2 August 1979).
.
Next, source windows 54 are opened in the
upper insulating layer 48, and a metal film, s~ch as
aluminum, is evaporated onto the upper surface of the
wafer to form, at the same time, both the source
metallization 32 and the gate metallization 44. The
source 32 and gate 44 metalli~ations are a~tomatically
separated during the evaportion process by the
insulating o~erhang 52.
Finally, metal 34 is evaporated onto the lower
surface 12 of the wafer to serve as the drain contact.
In order to reference the potential of the P
layer 20 so as to obtain surface inversion of the P
layer 20, the N~ source region 16 and P base region 20
must at some point be shorted together by an electrical
connection, such as conductor 56, depicted5 schematically. In practice conductor 56 can be
l4-
~ ~6~2
RD-13175
implemented by localized etching of the N+ layer prior
to metallization to open windows (not shown) where the
source rnetallization 32 can contact the P base layer
16.
In the operation of the FIG. 1 device, when
the device drain terminal 30 is biased positively with
respect to the device source terminal 28, the PN
heterojunction 24 is reverse-biased and blocks current
flow. This is the normally-off, forward blocking
condition. For biasing the device into conduction, a
positive voltage is applied to the gate terminal, and an
inversion channel is formed in the channel layer 42
under the gate electrode 44.
The FIG. 1 device, in general, operates in a
manner substantially identical to that of a conventional
vertical-channel power MOSFET. That is, with gate
electrode 44 sufficiently biased with a positive voltage
(with respect to source terminal 28)~ a conduction
channel 42, conductive to electrons, is formed by
inversion of P base region 20. Electron current (not
shown), whic~ can flow through N-conductivity type
semiconductor material, can thus flow between the source
and drain terminals 28 and 30, respectively, via the
conduction channel 42 In contrast to a conventional
vertical-channel power MOSFET, however, the relatively
low on-resistance of the GaAs N drift region 2~ is
combined with the relative ease of inversion of the InP
channel 42 surface and its superior inversion layer
conduction properties to result in a device with
superior electrical properties.
FIGo 2 depicts a similar device structure
differing, however, in that channels 36' in FIG. 2 are
of inverted trapezoidal shape. This structure can be
achieved by preferential etching wi~h the grooves
oriented in a direction perpendicular to that of FIG. 1,
15-
3~
RD-13175
i.e., perpendic~lar to a (110) flat, at least where
re~ions 16 and 20 comprise indium phosphide.
GaAs~Graded GaxIn1_xAs Devices
. .
The device structures of FIGS. 1 and 2
satisfy the objectives of the invention of achieving
high voltage, power MISFET devices by advantageously
combining the charac~eristic of low resistance due to
the high electron mobility and band gap of GaAs, with
the characteristic of easier inversion of another
material. Thus, the difficulty of achieving an
inversion layer on a GaAs surface under an insulator is
avoided by the invention. Mevertheless~ there are
drawbacks to the embodiments of FIGS. 1 and 2.
There are two drawbacks in particular. First
lattice mismatch between the two semiconductors (GaAs
and InP) may create defects in the InP layer. Second,
the unequal bandgaps ~Eg) can cause a small potential
barrier at the InP/GaAs interface, and this potential
barrier can increase the on-resistance of the device.
For InP, the bandgap Eg is 1.35 eV; for GaAs, the
bandgap Eg is 1.42 eV.
The device structures of FIGS 3 and 4
~5 effectively overcome these two drawbacks, while at the
same time at least a portion of the N- drift region
comprises gallium arsenide, and at least a
channel-supporting portion of the shield base region
com?rises a semiconductor material other than gallium
arsenide within which inversion regions may more readily
be formed.
In overview, the device embodiments of FIGS. 3
and 4 are of vertical-channel DMOS configuration. As in
the previous embodiments, at least a portion of the
drain region comprises GaAs. However, rather than InP
-16-
36~7~
RD-13175
for Lhe device portions including the gate-controlled
conduction~channel, a graded composition layer of
GaxIn1_xAs is employed, grown directly over the
GaAs laye r .
This techniq~e effectively overcomes both of
the drawbacks noted aboveO First I the grading
accommodate~ lattice misma~ch. Second, the grading
results in a grad~al change in the bandgap. Thus, no
discontinuity in the conduction band can occur, and no
potential barrier is formed. Still another advantage is
ease of fabrication employing known techniques.
~ n advantage, compared to a MISFET formed
entirely of GaAs, is that GaxIn1_xAs has higher
electron mobilities than pure GaAs. Thus, the inversion
channel resistance is reduced in comparison to that of a
MISFET.
Referring in detail to FIG. 3, a gallium
arsenide MISFET includes a semiconductor body 110 having
a pair of opposed principal surfaces, a lower surface
20 112 and an upper surface 114. The body 110 includes a
first layer 116 comprising GaAs and extending from one
of the principal surfaces, for example, from the lower
principal surface 112 into the body 110. The body 110
includes a second layer 118 comprising a graded
~S semiconductor layer extending from an interface 119
with the first layer 116 to the other of the principal
surfaces, i.e. to the upper principal surface 114. The
graded second layer 118 comprises GaAs at the interface
119 and comprises GaInAs at the upper principal surface
114, with the percentage of indium increasing from
substantially zero at the interface 119 to a maximum
concentration at the principal surface 114. More
particularly, the graded second layer 118 comprises a
graded composition layer of GaxIn1_xAs, wherein x
-17~
RD-13175
ranges ~rom ~bout 1.0 at the interface 119 to 0.47 at
the ~pper principal surface 114.
In the FIG. 3 device structure, it is
sigr;ificant that the two semiconductor layers 116 and
118 comprise diferent semicondu~tor materials, i.e.
GaAs and graded GaxIn1 xAs, respectively. It
will be appreciated that these layers are not
coextensive with (i.e. do not directly correspond to)
the drain, shield base and source regions of the
ultimate MISFET. Sepa~ate considerations are involved
in the device regions of the two conductivity types
(i.e. P and N conductivity type and of different
conductivities), on the one hand, and in the layers
formed of different semicond~ctor materials, on the
other hand.
Considering the actual FIG. 3 device regions,
the device includes a drain region 120, which, in turn,
comprises a relatively lightly-doped N- drift region
122 and a relatively highly-doped N~ drain terminal
region 124 in contact with drain metallization 126 and
connected to a representative device drain terminal 128~
The drain region 120 comprises at least a portion of the
GaAs first layer 116, and also comprises a portion 150
of the graded GaxIn1_xAs second layer 118. As in
~5 a conventional DMOS structure, part of the drain region
120 (or~ more particularly, the portion 150 of N
drift region 122 thereof) extends to the device upper
principal surface 114.
P conductivity type shield base regions 130
are formed, such as by diffusion, within the drain
region 120, more particularly within the N drift
region 122, and extend at least into the
GaxInl_xAs graded second layer 118. Preferably,
for best device performance, the P shield base regions
130 extend completely through the Ga.,Inl_,As
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graded second layer 11~ and slightly into the GaAs-first
layer 116. In either case, the P field base re~ion 13D
has a periphery 132 terminating at ~he upper principal.
surface 114.
The Einal semiconductor region is an N~
source region 134, formed such as by diffusion, within
the 2 conductivity type shield base region 130 and
having a periphery 136 terminating at the upper
principal surface 114. The periphery 136 of the N+
source regiorl 134 is spaced from the periphery 132 of
the P base region 130 to aefine the extent of a channel
lay~r 138, the channel layer 138 terminating at the
upper principal surface 114.
A metal gate electrode 140 is spaced from the
channel layer 138 by a gate insulating layer 142 which,
it will be appreciated, forms an interface at 144 with
the channel layer 138. The channel layer 138
preferablY comprises GaO.47InO.53As at the
actual interface 144.
To complete the FIG. 3 device structure,
source metallization 146 is provided in preferably ohmic
contact with the N+ source reyion 134. In order to
achieve the source-to-base shorts required in power
MISFET structures to avoid parasitic bipolar transistor
action, a shorting extension 148 of the P base region
130 extends up through the N+ source region 134 to the
principal surface 114 in preferably ohmic contact with
the source terminal metallization 144.
In the fabrication of the PIG. 3 device, the
GaAs first layer 116 is formed by starting with an N+
substrate which ultimately becomes the device drain
terminal re~ion 124. The N drift region 120 i9 then
epitaxially grown. When the top of the GaAs first layer
116 is reached, epitaxial growth continues, but with the
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gradual introduction of In to result in the growth in
the graded ~omposition layer 118 of GaxIn1_xAs.
Thereafter, the actual upper electrode
structure of the device is formed employing conventional
ma~king and double diff~sion techniques.
With regard to the Eabrication of the FIG. 3
device, it may be noted that the successful growth of
a graded composition layer of GaxInl_xAs on GaAs
has been demonstrated, (see, for example, R.E. Enstrom,
D. Richman, M.S. Abrahams, J.R. Appert, D.G. Fisher,
A.H. Sommers and B~F. Williams, "Vapour ~rowth of
GaxIn1_xA As Alloys for Infrared Photocathode
Applications", 1970 Symposium on Ga~s, paper 3, pp.
30 40~. Moreover, it has been demonstrated that
15 GaO 47InO 53As can be inverted using SiO2,
Al2O3 and Si3N4 as the gate insulator. (See,
for example~ A.S.H. Liao, R.F. Leheny, K.E. Nahory and
J.C. DeWinter, "An Ino.s3GaO.47DAs/Si3N4
n-Channel Inversion Mode ~ISFET", IEEE Electron Device
20 Letters, Vol. EDL-2, pp. 288-290 (11 November 1981) jo
The operation of the FIG. 3 device is
substantially identical to the operation of the FIG. 1
device, as discussed above, with the relatively low
on-resistance of the GaAs drift region 122 being
combined with the relative ease of inversion of the
GaInAs channel 138 and its superior inversion layer
conduction properties.
Finally, FIG. 4 depicts a slight variation in
device structure wherein the P conductivity type shield
base region 130 does not extend all the way through the
GaxIn1_xAs graded second layer 118. While the
performance of this device is somewhat less than that
that of the FIG. 3 device, it nevertheless effectively
addresses the problems to which the invention is
directed. It will be appreciated that in either the
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FIG~ 3 or the FIG. 4 case, the channel-supporting
portion of the P base region, comprises
GaxIn1-xAsl preferably GaO 47InO 53As-
The foregoing describes high-voltage power
MISFET semiconductor structures possessing low
on-resistance resulting from the use of gallium arsenide
drift regions, while exhibiting good inversion
ch~racteristics in a different type of semiconductor
material implementing the shield base regions.
While specific embodiments of the invention
have been illustrated and described herein, it is
realized that numerous modifications and ch~nges will
occur to those skilled in the art. For example, the
devices of FIGSo 1 and 2, shown with VMOS (grooved)
construction, could instead be implemented with DMOS
lnon-grooved) construction; similarly, the devices of
FIGS. 3 and 4, shown with DMOS construction, could be
instead implemented with -~MOS construction, with the
entire channel-supporting region of the shield base
region preferably comprising homogeneous
GaxIn1_xAs where x = 0.47. It is therefore to be
understood that the appended claims are intended to
cover all such modifications and changes as fall within
the true spirit and scope of the invention.
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