Note: Descriptions are shown in the official language in which they were submitted.
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his invention relates to systems and apparatus for
proYidinp announce~entC for telecon~,unicatior,s net~orkc.
lhe tern announcement is intended to include not only
conventional verbal announce~entC but also any other audic
material such as music or nodulated data.
raditional~y announcementC for a telephone network
have been provided by replayina messaaes recorded on a
movinp napnetic surface such as a continuous tape. Such
techniques make use of analogue recordinp and replay
equipment which has a nuder of disadvantaoec. Wear and
tear of tape, head and ~echanis~ result in steady
depradatior of sound quality and general unreliahility ir
hiah usaae applications. Analogue editino is difficult art
most chanpe reouire tb~ entire announcer,ent to be
re-recorded. A major disadvantage of aralopue systems is
that a caller is connected to an announcer)ent at whatever
point it happens to be in its cycle.
Iecbriiouec for dicitclly encodinp audiG material uc~
as speech have no been developed principally fol
2n trans~iscior, applications but they have alsc let to the
development of stcred-voice services because they permit
speech sinr,als to be stored and processed using digital
techniques. the three pair, classes of digital speech
coding techniques hhiC~ have been developed are waveforr
codina, speech synthesis and synthesis-by-rule. ln
addition, new customeI sianal~ina techriques have been
developed so that in addition to the traditional diallin~
method, sipnalling by Sipna~linp Syster ~ulti-Frequency
Number 4 (MF4) is no available. Another alternative is
sianallina by use of Automatic Speech RPcornition.
US Patent 4 371 7r2, assianed to ECS lelecom~unicaticr^
Inc., relates to a syster for the depocit, storage and
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delivery of audio messages. The system includes an
administrative subsystem, call processor subsystems end a
data storage subsystem, with a block transfer bus and data
storage buses providing for communication between the
subsystems. Various interfaces and disk adapters are
implemented with units referred to as "universal control
boards" each of which comprises a microprocessor, PRAM and
TOM memory devices with internal address and control
buses. An Intel Multibus connects all the universal
control boards.
In an article in The Bell System Technical Journal,
Vol. 60 (1581) July-August, No. 6, Part 2, pages 1083 to
1108, a mass announcement subsystem (MAS) is described.
The MAS includes an ES~ processor, a peripheral unit
control (PUC) and a mass announcement subsystem (MAS). A
peripheral unit bus (PUB) is used as the interface between
the ~SS processor, the switching network and transmission
interface equipment and the PUC. This bus and an extended
internal bus (EIB) carry control data.
The present invention provides a system for providing
announcements which makes use of digital techniques and
whose structure is sufficiently flexible to permit use of
any of the speech coding and signalling methods referred
to above.
According to the present invention there is provided
a system for providing announcements comprising, storage
means for storing digital signals representing
announcements, a first signal bus connec-ted to the storage
means, processing means connected to and associated with
the first bus for controlling the storage means to
transfer digital signals to/from the first signal bus, a
second signal bus for carrying digitally encoded audio
signals in a synchronous time divided manner, and control
means connected between the first and second signal buses
for efEecting bi-directional transfer of signals between
the first and second buses.
ho sy ' ter adv~ntaoecucly inclu~ec mouritir~ Hans such
as a back plane for the two buses.
The second buy may, for example, carry thirty-two
channels of time divided pulse code modulatiori signals
which car be very easily interfaced to a standard PC~
system. The two bus structure allows the system to operate
with a range of different codina and si~nallinc methods.
The provision of the second bus for speech signals permits
speech procescino circuits of the system tc co~lunicate Yic
that bus and releases the first bus for carrying
instructions from and data to the processino means. The
second bus may be interfaced in a simple manner to digital
net~or~s such as PC~ systers or to standard codecs. The
bus provides a flexible interconnection for various speech
procescina modules of the system.
As indicated above the two buses may be on a single
back plane. Sinale card processino modules such as MF4
receivers can connect to both buses simultaneously and
receive and transmit dioitally encoded audio data from the
2Q second bus, process the data under instructionC and data
received on the firct bus, and transfer the results to the
second bus. the two buses car be standard mechanical and
electrical interfaces, to hhich a variety of standard
modules may be connected.
Whilst PC~ coding is convenient for speech or audio
sionai transmission, other forms of coding, with lower bit
ratec, are preferable for storaoe purposes.
The control means is connected between the buses, and
may include code conversion means for converting bet~eer a
first form of coding used on the second bus and a second
form of codinc used by said storage means.
Advantageously the conversion means includes a third
bus. chic enables different or improved form of codina
for storage to be used if desired. Also, a variety of
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codinas could be used simultaneously fol signals on
different channels of the se.ond hJs. the contrcl ~eanC
can be arranged to alloh the system to operate with, for
example, waveform encodino or speech synthesis techrioue~.
the processing means may be a microprocessor and
associate system memory.
the storage means may com?rise a conventional disc
store which is accessible via said first bus.
Alternatively the storaee meane may comorise a maanetic
bubble store, a semiconductol memory or an optical disc.
The syste~l may include interface means for providing an
interface between the second bus and external telephone
linec .
The syctem may include a signalling subsystem for
transferring telephone signalling information between the
second buy and the processino means. the signallin~
subsysten may incorporate a microprocessor. The signallino
subsystem can be appropriately designed for operation hith
conventional dialling signalling, MF4 signalling or
automatic speech recognition.
Ihe syctem may include a watchdog or moritorino circuit
for monitoring operation of one or more of the system
circuits .
An e~kodiment of the invention will now be described,
by Jay of example, with particular reference to the
accompanying drawings. In the drahings:
Figure 1 is a block diagram showing apparatus used by a
system for providing verbal announcements in accordance
with the present invention;
Figure 2 is a block schematic diagram illustrating the
manner in which the apparatus of Figure 1 operates;
Figure 3 is a block schematic diagram showino in more
detail part of the system of Figures 1 and 2; and
; Figure 4 shows, diagramm2tically, a cabinet for
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mountino a sycter accordino tc the invertion, such ac tha'
shown in the preceding Figures.
he present system for providina verbal announcements
is a processor based system. The system can be considered
as comprisinc a number of co-operatina subsystemc, wtich
communicate with one another but are functionally
independent. venal control of the system is provided hy
a processor subsystem which includes a 16 bit
; microprncesssr 1~l havina an associated terminal or
lo terminals 11. The processor subsystem 1 has a random
access memory 12 which serves as the system memory and
which can be accessed via a bus 14. In the particular
embodiment the microprocessor 10 is an Intel 8û8~ device
and the bus 14 is an Intel Multibus. The subsystem has
associated thereh~ith a watchdog circuit 17 for carryino out
periodic monitoring of the operation of the system. The
syster also includes a data control subsystem 2 which
provides the main data storage for encoded announcements.
The data control system includes a disc arrangement ~5
which can be accessed via the Multibus 14 under the control
of a disc cortrol unit lo. The disc arranoement 15
consists of a moving head magnetic disc and the control
unit is an IS~C 220 disc controller. this unit can provide
an interface for up to four disc drives.
; 2~ the syster includes a second bus 2C which will
hereafter be referred to as a PC~ bus. This bus is a time
divided highway that can carry 32 full duplex 64 Kbit per
second channels. A number of subsystems can communicate
via this bus. A network interface subsystem 3 provides ar
interface between the system and the telephone network.
- The subsyster 3 includes a plurality of line units which
terminate incoming lines from the telephone network. The
line units 22 operate to separate DC sionalling informatior
from speech signals and to send the sigr,alling information
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on the PC~ tuc O to a r~t~ork cignalling sutsyC~er L, if
speech sianals are output onto a particular bus speech
channel or the bus 2C which is associated with that
particulaI incomino line. The network interface subsystem
also includes a PC~ buy controller 2~ which generates the
necessary control, address and clock signals for ur,its
which cor~unicate via the PC~ bUC 2G.
he system also includes a speech input/output
subsyster 5 hhict, includes two bus transfer cortro~ ~odulec
and a code conversion logic device, 30, showr, in more
detail in Fiaure 3 and described below, and connected
between the buses 14 and 20. The speech input/output
subsyster is the hardware and software responsible for
controlling transfer of speech data between the system
; 15 memory 12 associated with the processor and the PC~ bus
20. Each bus transfer module includes an intellioent DMA
controller which can take speech samples from l channels
of the PC~ bus 2C, recode them to reduce the bit rate and
then transfer them onto the bus l and subsequently into
the system memory 12. The code convert logic operates to
recode speech samples from A-lah PC~ which is used on the
PCM bus 20 into adaptive differential PC~ (ADPC~') which is
used for storage purposes. ADPC~ is a form of differential
encoding which makes use of the fact that successive
samplec of speech are often highly correlated; the data
rate can therefore be reduced by using the difference
betweer successive samples, rather than the actual values
of the samples. ADPC~ at 32 kbit/sec can produce speech
quality which is difficult to distinguish from PC~ used for
telephone transmission and switching at 32 kbit/sec. ûther
coding techniques could be used to reduce the data rate for
storage my taking advantage of redundancy in the sional or
other characteristics of speech (for example the fact that
the human ear is less sensitive to high freauency
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distortiorj. ye oding at lower bit rat- er,able stcragC
to be saved.
he syster operate to provide an anr~uncement
oenerally as follows. The various verbal annou~ce~entC
which car be output to the telephone network are stored Gf
the disc 15. When the processor 10 receives informatior,
kid it recognises as a request for a particular vernal
announcement that announcement is transferred from the disc
l into the memory 12. The data is then transferred from
the memory 12 under the control of the module 3û art placed
irl the appropriate channel on the PC~ bus 2G. From the PC~
bus 2C the data is fed to the appropriate line unit 22 art
output to the network.
Recordins of an announcement takes place in a similar
manner but the operations are reversed.
The detailed way in which this is achieved wily no be
described with reference to Figures 1 to 3. Figure 2 show
in addition to the hardware of Figure 1 the software
processes operated by the various subsystems.
The processor subcystem 1 includinc the processor lC,
system memory 12 and watchdog circuit 17, operates the
m2~iority of the system software. The processor lC~ operates
Intel's proprietary real time operating system which
provides facilitiec for task scheduling, interrupt
management, message passing, inter-task synchronisation,
device independent input/output and file handlino.
The netwcrk interface subsystem 3 which includes the
line units or cards 22 and the bus controller 26 operatec
to translate between the electrical and logical
requirements of the particular point in the telephone
network to which the system is connected and the variouC
speech processing and signallino modules which make up the
system. The line cards 22 interface speech and signallina
to the PC~' bus 2C and carry out any necessary analooue to
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di5itô~ conversion. the PC~ bus it a tire divided hig~aj
that carries 32 full-duplex 64 K bits pe. second channelc.
It is use to distribute the speech data tc appropriate
ones of up to 32 speech channels encoded in Ala PC~
provided on the bus 2G. It also distributes associated
signalling information to the network signalling module Zb
and transnits outaoing sianalling states to the fir cards
22.
Use of the 32 channel PC~ 2û bus for carrying audio
data is advantageous in that interfacing to 32 channel PC~
systers and standard codecs is straightforward. The PCM
bus 2û forms a standard flexible interconnection point for
thy various speech processina modules which make up the
system and to decouple these modules fror variations in the
network interface 3 which often arise. Wave form encodinc
nodules, MF4 detector modules, synthesisers, word
ecognisers etc can be interfaced hith the bus 20 and
freely mixed to suit a particular application. The other
modules that process signals on the PC~ bus connect to it
using standard interface circuits.
he network interface subsystem includes its own
monitoring circuit, or watchdoa. A line card watchdog
sion21 is generated by the network signalling module 24 and
is transmitted separately for each line card on the
signalling channel of the PCM bus 20. If this signal does
not change state at the correct frequency, the line card
interprets this as ar, indication that a channel of the Pi'
bus corresponding to that particular line card has failed.
The line card ther automatically places a busy condition or
that line to prevent faulty equipment accepting calls.
he network signalling subsystem 4 includes the module
24 which is connected between buses 14 and 20 and is a
hardware and software subsystem that trarsfers network
sianalling conditions between the PCM bus 2û and a call
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control subsystem 4~ ~hic~ is softhare held ir the cyste~
r,e~ory 12. the network signallino module 24 comprises a
sinole card microprocessor based ur,it that handles
signallino for the 32 speech channels on the PC~ bus 2G.
It reduces the load on the main processor lC by peIsistence
checking incoming signalling and reporting only changes of
state to the processor lC. It also applies outQoinc
signalling conditions on instruction from the processor l
The speech input/output subsystem 5 comprises the
hardware and software responsible for transfer of speech
data between the system 12 and the PC~ bus 2C.
Speech data is taken from the PCM bus 20 and placed in
the system memory by the speech input/output subsystem 5
and it is then transferred to the disc arrangement 15 under
1, the control of the data control subsystem 32. this
nperation is reversed to replay a recorded announcement.
he bus transfer control module 3C which forms the
hardware part of the speech input~output subsystem is an
intellioer,t DMA controller that takes speech samples from
16 channels of the PCM bus, recodes the to reduce the bit
rate and then transfers them onto the bUC 14 and
; subsequently into the system memory. the hardware of the
speech input/output subsystem 5 is shown in Figure 3. It
includes code convert logic for recoding speech samples
from Ala PCM which is used on the PC~ bus 20 into
adaptive differential PCM which is used for storage
purposes. the interface to the code convert logic is
designed as a bus so that it is possible for this system tc
cater for other types of speech codino as they are
developed-
As shown in Fioure 3, module O is connected betweenthe Multibus 14 and the F~ bus 20, and comprises two bUC
transfer modules 56, code convert loaic sn and a speech
code bus 51. Modules 56 include a half-duplex bus transfer
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control unit 6n and speech irterface logic I. Each ~dule
can handle data being transferred to and from sixteen
channels of the PC~ bus, and it is connected to bus 2C vim
a line 63 carrying timing signals from the PC~ bus.
the code convert looic 50 has arithmetic unit 52 an
sequence board 53, and operates to convert PC~ samples from
bus 20 into adaptive differential PC~ samples and vice
versa. PC~ bus 20 is connected to the bus transfer module
50 by a line 65 which carrieC timing signals only and a
line 67 which carries speech signals only. The lines 69 to
the speech code bus 51 and Multibus 14 carry both speech
and timing signals.
In operation, speech signals from a particular channel
of the PC~ bus are recoded by the code convert logic 50,
under the direction of one of the bus transfer nodules 5t.
; nodule 56 receives thy necessary timing signals directly
from the PCM bus. An encoded byte of data from a single
time slot in a PCM channel is put onto the speech code bus
51 by loaic device 5C and transferred to bus transfer
nodule 56, where it is stored. Bytes of data from
succeedino channels are encoded in turn and stored in
respective memories of the modules 56. ûne of the modules
stores data from odd-numbered channels of the PC~ bus and
the other module stores data from even-numbered channels.
128 bytes from a particular channel are encoded in turr,
each byte of 8 bits beino reduced to 4 bits and thy data
stored in the appropriate memory. 128 bytes of data from
the PC~ bus 2û, after encoding, fill a memory and the
filing of a second memory is then begun, with 12~ bytes
from the same channel of the PCM bus being encoded and
stored.
In order to encode the speech signals from all channels
of the PC~ bus with a type of encoding other than ADPC~,
code convert logic 50 could be replaced or altered as
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12~:~39~6
necessa.y. Ic encode seek data or, or or more c~arlr,elc
of PC~ bus 20 differently from the coding on other
channels, two or more code convert logic devices 5C could
be provided, accordino to the number of different types of
encoding renuired, between PC~ bus 20 via two further firs
65 and 67 and speech code bus 51 via an additional line 6~.
If the same encoding is acceptable for the PC~ Gus art
for storaee, then the code convert logic 50 and speech code
bus 5~ can be omitted, and each bus transfer module 5
connected directly, via paths for speech and timino
signals, to the PC~ bus 2G.
The call control subsystem shown at 4C in Figure 2 is a
software only subsystem operated by the processor lû. this
controls ano coordinates speech input and output, and data
control to realise the service specified by a service
control subsystem 41 on a particular channel. The
subsystem 40 receives information relating to call arrival
from the network signalling subsystem 4 and refers to
service control 41 for instructions as to how to handle a
call. It can report back to service control with call
details at the end of a call. The service control system
shown at 41 is also a software only subsystem operated by
the processor 10. This subsystem determines which service
is to be offered when a call arrives from the network.
Call control 40 informs the service control subsystem 41 of
a call arrival which specifies the service to be offered
and any parameters such as the number of repeats of an
announcement. ûn clear down it passes call statistics to
an administrative and maintenance subsystem 43 which is
software only.
ThUc the present system can provide up to 32 output
channels of verbal announcements with each channel hearino
its announcement from the start. the data control subsyte~
2 can provide up to 4 hours of speech storaoe on the disc
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and thiC may by in the fGrm of cnC lonG annnunce~ent or 3'
many as 250 shorter announce~entC. Various combinations of
announcement replay and reccrd actions can be arranoed for
each channel. For example, one channel may be arranoed to
replay a single announce~ert file ~ereas the next channel
might be set to replay three announcement files in seouence
and a further channel may replay one annnucement fix, ther,
record into another and then replay a third. the
announcement associated with a channel and comkinationc of
record and replay actions may be changed either by command
fIom the terminal 11 or at predetermined times undel toe
control of a system clock. Announcements can also be
recorded and edited by command from the terminal. the
terminal can be located remotely and linked to the system
by a modem. the manner in which announcements are replayed
is such that the start of announcement coincides with the
arrival of a call. the maximum delay between the call
arrival and the announcement start is of the order of two
seconds .
A feature of the present system is the provisior cf the
two buses 14 and 20. This arrangement mazes it possicle tc
plua into the system a wide range of different modules
thereby making a very flexible structure. the processol 10
can send instructions to and receive data from those
modules over the control bus 14 and the modules can perform
speech processing functions as instructec by the processor
on the signals they receive over the F~ bus 20. Exa~les
of modules which can be connected betweer the two buse- are
the bus transfer module and the network signalling ~od~le.
Other possible modules which could be provided are speech
synthesising modules, automatic speech recognition mcdules
and multi-frequency (~F4) signalling detectinn modules.
Data transfer between the buses 14 and 2C is controlled by
the module 30 and this relieves thF load ori the procescor
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122~3946
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1~1. h'~n the system ic provided with ~$4 sigr,allinp
detectinr, nodules or automatic speech recopnitirJn modu]e~,
the terminal fur,ctions can be carried out front a suitahly
equipped telephone.
Figure 4 shows a cabinet 71 which can accon~odate a
number of cards carrying cicuits for a systenl accordinQ tc
the present invention. Cabinet 71 has a back plane 73 on
which the wirings for a PCM bus 20 and a Multibus 14 are
provided. the back plane alsn carries edae cnnnectors 7~
for the cardc. sinale card 79 (eg an Mf 4 receiver) is
showr, in the cabinet, in broken Hines, supported by twc
edge connectors 75, which bring the card into contact wit
the uses 14 and 2û. the card 75 is therefore connecter to
both buses simultaneously to operate as described above.
Standard catinets have a ~ulti~u~ on the back plane; the
PC~ bus can be provided on a part of the back plane not
normally used.
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