Note: Descriptions are shown in the official language in which they were submitted.
AUTOMATIC OPTICAL INSPECTION SYSTEM ~ 8
The invention relates to automatic inspection systems,
especially for inspecting articles such as photomasks for making
printed circuit boards (PCBs) or semiconductor devices, the circuit
boards or semiconductor devices themselves (particularly
interconnection patterns of integrated circuits), and like articles
having a pattern of lines of predetermined configuration.
Generally, known automatic optical inspection sys-tems
comprise means for acquiring an image of the article being inspected,
the acquired image usually being represented digitally, and processing
means for evaluating the image to de-termine whether or not the article
is defective. In some systems the image-ac~uisition means comprises an
array oF sensors, for example CCD sensors, arranged to receive
radiation transmitted through or reflected from the article from a
remote source. The article is scanned, conveniently by moving it
across a row of the sensors and scanning the sensors electronically.
The analogue outputs of the sensors,~hich are proportional to light
intensity, are then digiti~ed and bilevel coded.
A typical such scanning system is disclosed by W.M.
Sterling in a paper entitled "Automatic Non-reference Inspection of
Printed ~iring Boards", Proc. PRIP79-Computer Soc. on Pattern
Recognition and Image Processing, 1979 pp 93-100.
An alternative scanning system, wherein a stationary
article is scanned by a laser beam, is disclosed by R.C. Restrick in
a paper en-titled "An Automatic Optical Printed Circuit Inspect10n
System", SPIE Vol. 116, Solid State Imaging Devices, 1977.
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The processing of -the image data is then usually done by
either of two procedures depending upon whether the system is of the
"reference" or "non-reference/local" kind. Reference systems compare
the pattern of the entire article with a reFerence template obtained
froml -for example, computer-aided design (CAD) data or a master or
reference article. Such reference systems are not entirely
satisfactory because, when micrometer resolutions are involved~ it is
dif-ficult and time-consuming to align the respective images o~f the
template and the ar-ticle being inspected, whether this is done
physically or by signal processing.
In non-reference systems, only a small area of the
article is examined at any particular time and such examination is for
local consistency with predetermined design rules or characteristics.
In the case of, for example9 a PCB photornask created using CAD, -the
design rules will be specific and relatively few in nurnber. For
example, line orientation might be limited to orthogonal and 45
thereto, and pads to rectangular (usually square~ or elliptical
(usually circular), Lines also would have constant width and at least
a prescribed minimurn spacing between them. Accordingly~ such
non-reference systems not only are simpler than the reference kind, but
also require less storage capacity.
The present invention is directed particularly to such
"non-reference/local" systems.
Known inspection systems of the non-reference type use
either dimensiondl verification ~gauging) or pattern recognition to
determine consistency between the art-icle under test dnd the design
rules or characteristics. A system uslng dimensiondl ver-ific~tion is
disclosed in the aforementioned paper by R.C. Restrick and involves
detecting successive edges of either the same line, or adjacent lines,
and gauging the distance between them, A defect is signalled if this
distance is wrong when compared with the design rules. Dimensional
verification systems can readily detect pinholes in, or excess material
between, in-terconnection conductors because the edges of the plnhole or
excess material occur within the prescribed minimum distance be-tween
the aforementioned successive edges. They are not entirely
sa-tisFactory, however, for de-tecting pinholes in large areas such as
ground planes or, conversely, small conductive blemishes in large
subs-trate areas. It is, of course, desirable to deteGt such defects,
if only because they imply poor quality control.
The alternative non-reference technique, pattern
recognition, primarily involves wa-tching for irregularities in the
shape of an edge. This rnay involve "tracking" the edge, for example,
as disclosed by P.E. Danielson and B. Kruse in a paper entitled
"Distance Checking Algorithms", Computer Graphics and Ima~e Processing,
Vol. 11, pp. 349-376, 1979, or by -template matching, for example as
disclosed by J.F. Jarvis in a paper entitled "A Method for Automating
the Visual Inspection of Printed Wiring ~30ards", I.E.E.E. Transactions
on Pa-ttern Analysis and Machine Intelligence, Vol. PA~ 2, No. 1,
January 1980. Such known pattern recognition techniques are generally
adequate for detecting small, abrupt changes, but not suitable for
detec-ting locally-consistent defects, such as a gradual narrowing of a
conductor. Also -they might not detect a conlplete cut or bridging if it
is regular after digitization and follo~s the design rules.
An object of the present invention is to eliminate, or
at least mi-tiga-te the aforementioned problem of the non-reference kind
o-F inspection system. To this end, according to one aspect of the
present invention, there is provided an automatic inspection system of
the non-reference kind wherein both dimensional verifica-tion and
pattern recognition are employed.
According -to one aspect oF the invention, apparatus for
automatically inspecting a patterned article comprises:-
(i) image acquisition means for acquiring an image of atleast part of said article and providing a binary signal, each bit of
such binary signal representing a picture element of said image;
(ii) means for storing temporarily a number of bits of
said binary signal;
(iii) means -for accessing the stored bi-ts and
determining the logical states of t~o sets of such bits;
one set comprising at least one pair of bits
corresponding, in said image, to a respective pair of picture elements
that are spaced apart by a distance equivalent -to the spacing be-t~een
successive line edges of the pattern on said patterned article;
the other se-t comprising a plurality of bits
corresponding, in said image, to a predetermined array of picture
elements;
(iv) dimensional verification means responsive to the
means for accessing the stored bits ~or providing a dimensional
veriFication Fault signal in dependence upon ~hether or not the states
of said one set of bits indicate that successive line edges are said
predetermined dimension apar-t;
(v) edge detection means responsive to the means for
,. ~.
~22~ 8
accessing the stored bits for providing, in dependence upon the sta-tes
of a plurality of bits of said other set, an edge signal indicating
-that said array oF adjacent picture elemen-ts straddles a line edge;
(vi) pattern recognition means responsive to the state
of said other set oF bits and to said edge signal for providing a
pat-tern recognition fault signal indicating whether or not the pattern
formed by said array of picture elements corresponds to an acceptable
edge profile; and
(vii) output means responsive to said dimensional
verification means and said pattern recognition means -for providing a
-fault signal indication,
The means for accessing the stored bi-ts may be tapped
delay means arranged so that the taps form a matrix or "window"
corresponding to a relatively small portion of the area of the image,
the "window" being arranged to scan the image as the binary signal
passes through the tapped delay means.
Pre-Ferably, the output means is arranged to collate or
"cluster" a plurality of outputs from the D'J and PR means, determine
whether they are so spatially grouped as to imply the presence of a
true defect and, if so, signal a defect. To take into account that the
outputs of the dimensional veri-fication means and pattern recognition
means, respectively, will have a different probability o-f representing
a true fault, the outputs of the dimensional verificdtion means and
pattern recognition means may be weighted and a defect indicated ~Ihen
either individually or in combination, they reach a predetermined
number. For example, iF, as is likely, the D~ means output is more
probably correct than the PR means, a defect ma~ be sign~lled either
for a single DV defect indication or -for a plurali-ty o-f spatially
neighbouring PR indications.
The said one and said other set of picture elements/bits
are preferably, but not necessarily, mutually exclusive. The second
set (PR) may be circumscribed by the first se-t (DV).
Preferably the two sets of elements have one in common,
serving as a datum for DV and PR measurements. Then the respective DV
and PR outputs, especially when "clustered", will not need to be offset
rela-tive to each other. The one or outer set may be configured in
dependence upon the expected orientations of the lines making up the
pattern. For exarnple, the points may be disposed about an
approximation to a circle. One element may be at the centre of the
circle and serve -to determine whether the pair of elements/bits under
consideration straddles a conductor/line or a space between lines.
This centre element may be the common picture element (or tap~ -for both
DV and PR sets of elements. The remaining elements may then be located
in diametrically opposite pairs located at 45 intervals. Such an
arrangement is particularly suited to articles having patterns laid out
by computer-aided design (CAD), with lines or conductors hori~ontal,
ver-tical or oblique. The diameter of the circle will be determined in
dependence upon the edge spacings of lines or conductors in the innage
of the particular article to be tested.
A second ring of elements, similarly disposed but closer
to the datum than the first ring may be provided. The diametrical
spacings of the different ring sets may then correspond to line spacing
and line width, respectively. The condition of the centre element may
then be used in selecting whether to carry out a spacing check on the
I
~P~9~
appropriate ring of elements or a line width check on the other ring~
The said other set of elements, i.e. that used for
pattern recognition, may comprise a rectangular array. This is
preferred for rectilinear edges. An oblong array might be preferred if
lines were predominantly in one direction.
An embodiment of the invention will now be described, by
way of example only, wi-th reference to the accompanying drawings, in
which:-
Figure 1 is a schematic representation of an optical
printed circuit board inspection system;
Figure 2 is a block diagram of a pre-processing and
camera control means of the system represented in Figure l;
Figure 3 is a block diagram of a line delay and window
generation means of the system represented in Figure li
Figure 4 is a schematic diagram of dimensional
verifica-tion means of the system;
Figure 5 is a block diagram of pattern recognition means
of the system;
Figure 6 is a block diagrdm of clustering means for
clustering the outputs of the dimensional verification means and
pa-t-tern recognition means of Figures 4 and S, respectively;
Figure 7 is d diagram oF the window or picture element
array sho~ing the elernents used by the dimensional verification means
and the pattern recognition means;
Fi~ure 8 is a representation of the cell-partitioning of
the surface being scanned; and
Figure ~ represents a modified partitioning scheme with
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overlapping cell arrays.
Referring to Figure 1, a printed circuit board (PCB)
inspection system comprises image acquisition means in the form of two
cameras 10 and 12, respectively. The cameras are mounted above, and
aimed at, the uppermost surface of a printed circuit board (PC8) 14
suppor-ted by a table 16. The table 16 is movable to and Fro in the
direction of arrow A by suitable drive means (not shown) which may be
of conventional construction.
Also, a translation mechanism (no-t shown) is provided to
displace -the cameras 10 and 12 and -the circuit board 14 relative to
each other in a direction transverse to the arrow A. The translation
mechanism is actuated between each longitudinal scdn of the circuit
board 14, so that the entire width of the circui-t board 14 is scanned
in a series of parallel strips.
Although two cameras are shown, one or more could be
used, with appropriate adjustment of the translation mechanism. If
desired, a row of cameras could span the entire width of the circuit
board, in which case the translation mechanism would not be needed.
A light source 18, positioned above the table 16,
irradiates the uppermos-t surface of the PCB 14. A second light source
20, positioned beneath the table 16, irradiates the underside of the
PCB 14 through a sli-t 22 in the table 16. In the case of an opaque
article, such as the PC~ illustrated, the cameras 10 and 12 receive
reflected light from the first source 18. In addition, they receive
some transmittecl light from second source 20, which reaches the cameras
via any through-holes in the PCB. The intensity of the second light
source 20 is such that the light transmitted throuyh the holes will be
the same intensity as the light reflec-ted -From the conduc~or pad
surrounding the hole. Then the hole will appear "invisible" to the
cameras. When the article transmits light, as in the case of a
phototool or mask, light source 20 alone suFfices.
The cameras 10 and 12 are positioned along, and directly
above, the slit 22. Embodiments of the inven-tion could store and
process the entire image o-f a PCB or other ar-ticle as a two-dimensional
"snapshot". However, in view of the vast amounts of information that
would be involved, it is preferred to use a line camera and scanning.
Thus, each of the cameras 10 and 12 is a line camera, specifically a
linear CCD array camera, arranged to view a strip of the PCB. Each
strip comprises 2048 picture elements and is one inch wide @ 0.5 mil
resolution or 2 inches wide @ 1 mil resolution. Adjacent strips
overlap slightly, for example by about ten percent, to ensure complete
coverage of the article.
~ Other scanning arrangements are possible, o-F course,
for example using an ~-Y table.)
The image information signal from each camera is passed
line-by-line to image analysing circuitry ~Yhich determines the
locations of apparent faults or defects. Since the circuitry is -the
same ~or both cameras, only that associated with camera 10 will be
described.
The analogue output from camera lO is applied to a
signal preprocessor 30 which converts it into a binary signal for
application to a line delay and window generator 32. In the window
generator 32, consecutive lines of the image scan are stored and access
is provided to a window comprising an array of 32 x 32 picture elements
(pels). One prede-termined set of these elements (a pair of concentric
rings) is accessed by dimensional veriFication (DV) means 3~, and a
second set (a central rectan31e) is accessed by pattern recognition
(PR) means 36. The dimensional verification means 3~ and pattern
recognition means 3~ determine, in a manner to be described later, -the
existence o-f an apparent fault or defect in the array of elements and
supply corresponding DV fault signals and PR ~ault signals to ~he
clustering means 38. The clus-tering means 38 clusters and weights the
two signals and supplies the resulting data to a control processor 40,
which signals the occurrence of a fault.
The processor 40 also controls, by way of reset signal
means 42, the generation of a reset signal -For application to ~indo~
genera-tor 32 and clustering means 38, respectively. Also, by way of
line 44, the processor 40 controls c~mera control means 46, which
genera-tes a clock signal and exposure control signal ~or application to
camera 10.
For convenience, more detailed diacJrams o~ the
preprocessor 30, camera control 46 and reset signal means 42 are shown
-together in Figure 2. The camera control means 46 comprises a
programmable clock 50 which is loaded from processor ~10. The I ~l;iz
clock signal, yenerated by programmable clock SO, is applied directly
to the "clock" input of camera 10 alld controls removal of data from the
readout array o~ the camera 10. The output of the programlndble clock
50 is divided by means of a divide-by-20~18 device 52 and applied to the
exposllre control input of camerd 10. This "exposure" control
deterlnines the transfer of integratetl exposure chdrges from the
integrating arrdy to the readout array. This occurs every rl1illisecond
or 2048 pels. The clock echo signal from the camera 10 is applied to a
line driver 54 and used as a system-wide clock.
The reset signal generating means 42 comprises a control
register 56 to which is applied a control word ~rom the processor 40.
S One bi-t of the output of control register 56 is applied to a
mul-tivibrator trigger 58 which generates therefrom the system reset
signal a 1 millisecond pulse on a rising edge of the control bit. The
output of control register 56 is used for other control functions, for
example for selecting appropriate D\l rinys of elements.
In addition to line driver 54, which propagates the
system clock, the preprocessing means 30 includes a line driver 60 for
propagating the line sync output, for application to the window
generator 32 and clustering means 38.
As previously mentioned, the preprocessing means 30
converts the analogue signal from the camera 10 into a bilevel digital
signal. As shown in Figure 2, the analogue signal from camera 10 is
applied to an analogue/digital converter 60. The output oF the A/D
converter 60, which is a 6-bit word, is applied to a comparator 62,
together with a 6-bit video reference signal generated by video
reference means 64.
In the case of a PCB, the re-ference threshold is set so
as to discrimillate between the conductor material, which reflects
incident light well, and subs-trate or insulator material, wh-ich
re-flec-ts light to d lesser extent and so appears darker in the recorded
images. In the case of a phototool 9 the reference threshold will be
set to discriminate between substantially opaque and transparent parts
of the photo-tool. A signal level of "1" represents conductor area of a
3~8
PCB or opaque area of a phototool and a signal level of "0" represents
substrate area of a PCB or transparent area oF a phototool.
For phototools, the camera output signal may be quite
clean, in which case a "fixed" threshold will usually be adequate. The
conversion can then be implemented convenien-tly using an A/D conver-ter
followed by a comparator as illustrated. The video reference means 64
then comprises a 6-bit register written into by the processor 40.
In the specific embodiment, the threshold was determined
using a mode-seeking method per-formed off-line. A number, e.g. 40, oF
images were pre-recorded and their global his-togram analyzed. It had
two prominent peaks with a valley in between. The midpoint of the
valley was determined and the final threshold was set to correspond to
the midpoint of the valley.
For good resul-ts with PCBs, an adaptive thresholding
technique may be preferred. Then, instead of a 6-bi-t constant, the
threshold would be a variable level generated by the video reference
means 64 and adapted in accorclance with local illumination and contrast
parameters.
Re-ferring now to Figure 3, the thresholded or bilevel
signal from comparator 62 (Figure 2) and the s~stem reset signal from
multivibrator 58 are supplied to window generator 32, which provides
individual bit-access to a 32 x 32 bi-t (pel) window. As the video
signal passes through the window generator, the window effectivel~
scans the entire surface to be inspected.
At the input to tile window generator 32, the bilevel
video signal and reset signal are applied to respective inp~lts of an
AN~ gdte 70. The output of AND ~ate 70 is applied to the input oF a
1~
38
fast random access memory (RAM) 72, which is connected in series with
three more fast random access memories (RAMs) 74, 76 and 78,
respectively. Each rast random access memory has storage -For eight 2~
lines. Therefore the four RAMs 72, 74, 75 and 78 serve as video delay
lines and provide storage for 32 scan lines of ima~e da-ta, each line
being 2048 picture elements (pels) wide. The AND gate 70 is used to
zero the contents of the video delay lines at system reset, usually at
the beginning of each strip of the scanning pattern.
The eigh-th or last data line of RAM 72 is connected to
the first data line of RAM 74 as indicated by link 80. Likewise the
last lines of RAMs 74 and 76 are connected to the firs-t lines of RAMs
76 and 78, respectively, as indicated by corresponding links 82 and 84.
All four RAMs 72-78 are addressed by a 20~8 counter 90,
which is clocked by the system clock and cleared by the line sync. In
opera-tion, successive read/modify/write cycles read a previous image
value from memory and store the next value. Each data line is
cross-connected to the next, so a bit appearing a-t -the end of the first
line will be loaded into the beginning of the next line of the RAM.
Thus, the image data passes serially through the Four RAMs which serve
as a long video delay line.
The "delay line" has 32 taps separated, in ef-Fect, by
one line scan or 2048 pels. The taps are implemented using the 32 data
ou-tput pins of the RAMs 72-78. In the diagram these data lines are
numbèred in four groups, vis. 101-107, 111-117, 121-127 and 131-137,
respectively, and each data line is connected to the input of the first
shift register in a row of four serially-connected 8-bit registers.
The shift registers, numbered 151-27~, are not all shown. Each shift
register has eight accessible outpu-ts or taps, one for each bi-t.
In operation, when a previous value from one line of a
RAM is transFerred to the next line of that RAM (or the next RAM), i-t
is also read into the associated shi-ft register. Thus, the image data
passes through the bank o-f shi-ft registers 151-278, with a delay
between rows of one line scan (2048 pels) so that bits in the shift
register have spa-tial positions corresponding to the points of the
image to which they correspond.
As the image data passes through the shift registers,
therefore, at each image point (clock cycle) a 32 x 32 element window
is available at the taps of the shi-ft registers.
Two sets of elements of the window are actually
accessed. The firs-t set is accessed by way of line 300 by the
dimensional verifica-tion means 34 and constitutes eight pels designated
A1 - A8 and eight designated B1 - B8, together wi~h a centre element
CE . As shown in Figure 7, elements Al - A8 are arranged each
equidistant from its neighbour in an approximately circular array of
diameter a. Taking the horizontal direction in Figure 7 as being the
direction of line scan, elements Al and A5 are diametrically opposed on
-the vertical axis and equidistant from the centre element CE. Elements
A3 and A7 are similarly disposed along the horizon-tal axis, elements A2
and A6 along -the +45 oblique axis and elements A4 and A8 along the
45 oblique axis.
Elements B1-88 are radially aligned with elements A1-A8,
respectively, but are further away from the centre element CE -to lie on
an approximate circle of diame-ter b.
The two circles of elements A1-A8 and B1-B8 constitute
14
r;D~
the first set of picture elements whlch are used for dimensional
verification.
The circle diameters a and b correspond to minimum
permissible conductor spacing and minimum permissible width,
respectively. The condition of the centre element CE will determine
whether a conductor width verification or a spacing verification is to
be made. Thus, in the specific exarnple, if the centre element CE is on
substra-te, a conductor spacing verification is per-formed on each pair
of diametrically opposed elements and the pair of elements on the
diameter that is perpendicular thereto. Then a minimum conductor
spacing fault, i.e. conductor spacing less than minimum in any of the
four orientations, is indicated if the centre element CE is on the
substrate and A * CE is true where:
A = Al * A5 * A3 * A7 +
A2 * A6 -* A4 * A~ +
A3 * A7 * A5 * A1 -~
A4 * A~ * A2 * A6 ....... 1
where * = AND
-~ = OR
An = conductor
An = substrate
Similarly, a minimum conductor width flaw, i.e, the
width of the conductor less than -the prescribed minimum, will be
indicated if, when the centre element CE is above conductor and B * CE
is true, ~here:
B = B1 k BS `k B3 * B7 +
B2 * B6 * B4 * B~
38
B3 * B7 * B5 * B1 -~
B4 * B8 * B2 * B6 ....... 2
If either of these conditions occurs, the X-Y
coordinates of the indicated flaw (the centre element CE) are
transmitted to the clustering means 38.
Implementation of the analysis of the condition of the
D~/ elements is conveniently achieved by means of a logic array as shown
in Figure 4. Elements A1 - A8 are applied in accordance with equation
1 above to the appropria-te inputs of Four AND gates 320, 322, 324 and
326, respectively, the outputs of which are applied to an OR gate 328.
The output of OR gate 328 is applied to one input of an AND gate 330,
which has an inverting input to which the value of centre element CE is
applied.
The logic for processing elements B1 - B8 is similare
comprising four AND gates 332, 334, 336 and 338, respectively, an OR
gate 3~!0 and an AND gate 342. However, in this case the centre element
value CE is applied to the corresponding AND gate 342 without
inversion (to enable the test only above conductor material).
The outputs of AND gates 330 and 342 are applied to an
OR gate 344, the output of which indicates the presence of a
dimensional verification violation of either kind and is fed to the
clustering means 38 via the pattern recognition means 36.
In addi-tion to -the dimensional verification, if the
centre elemen-t is at the edge of a conductor, a pattern recognition
check is carried out. Only patterns of elements centered on an edge
are examined because that is how PR-recognizable defects will manifest
themselves in the binarized image. An edge point is defined as a point
16
for which the centre element CE lies above a conductor and at leas-t one
of its four nearest neighbour pels is on substrate. Obviously, the
edge could be de-tected by decreeing that when the cen-tre element is on
substrate at least one of its nearest neighbour pels is on conductor.
Elements not corresponding to an edge point are not
e~amined. Once an edge has been detected in this way, the pattern
recognition check is carried out on the 5 x 5 matrix of pels centered
on the centre element CE (see Figure 7). The sets of 5 x 5 elements
are compared with successive ones of a set of templates representing
valid pa-tterns. If a match is -Found, the pattern or 5 x S matrix is
deemed "good" and discarded, the next one then being compared. On the
other hand, if the pattern is not found in the bank of valid patterns,
a pattern recognition type of flaw is indicated.
The pattern recognition procedure is conveniently
implemented using the circui-try shown in Figure 5.
Pat-tern recognition means 36 cornprises a comparator 168,
to which the elements WO-W23 of the 5 x 5 matrix are applied by way of
a FIFO 152 which acts as a bu-Ffer (CE is not comp-lred so only 24-bit
words are required). The centre element CE is one input of an AND gate
154, the ou-tput of which is applied to the FIFO 152. The "nearest
neighbour" elements, numbers W7, Wll, W12 and W1~ are applied to the
four inpu-ts of an AND gate 156, the outpu-t o~ which is applied,
inverted, to the second input o-f AND gate 154. Thus, i-f the centre
element CE is on conduc-tor and any one of elements W7, Wll, W12 and W16
is not, the output of ga-te 154 ~oes high, ~hich causes the pattern of
elemen-ts WO-W23 to be loaded into FIFO 152. It s not necessary ~or
the cen-tre element CE to be compared ~ith the valid patterns since its
state is already known, i.e. "1". The ou-tput of gate 154 represents
-the edge point signal. Once an edge is detected, seYeral ~up to 9
clock cycles are needed to compare the 24 element pattern with the
templates (512). Only nine cycles are needed using successive
approximation, i.e. cutting the range in hal-f each time the cornparison
is made.
The corresponding output of FIFO 152 is applied to
control logic 160, which controls reset and clock func-tions of
successive approximations register 162. The control logic l60 derives
its clock signal from the system clock on line 164 and receives a
"found" signal via line 166 from a comparator 168. The successive
approximations register 162 generates addresses Ao~A8 For a
read-only memory 164 (conveniently three EPROMS). These EPROMS 164
contain the list of valid patterns arranged in increasing order of
magnitude/ i.e. the 24-bit templates are arranged in such an order
that, if they were interpreted as unsigned integers, they would be
increasing in magnltude. In the specific example, the EPROM 164
contains 51Z templates, each comprising 24 elements. The EPROMs 16
are connected to the comparator 1~8, together with the 24-bit output o~
FIFO 152. Thus, the templates can be compared, in Curn, with the 24
elements W0-'.~23 of the 5 x 5 matrix in question. The comparator 168 is
coupled via line 164 to the reset input of successive approximatioll
register 160. If a match is founcl between the patterrl in question and
one of the valid templates, the successive approxirnations registnr 162
is reset via line 164 from the comparator 168. The pattern under test
is therefor~ a valid p~ttern, so it is disc~lrded in response to an
unload signal to FIFO 152 froln cuntrol logic bloc~ l60, Yid the
1~3
3~
"unload" line, A new edge pattern is then applied to the comparator
168, by the FIFO 152, and the comparison process repeated. The
successive approximations register 162 starts with the mid-point
address of the EPROM 164. The comparator 168 signals whether the
"unknown" is greater than, equal to, or less than the mid-point
template. The regis-ter 162 selects the mid-point of the appropriate
half and -the process repeats. If no match has been found and all nine
cycles have been used, the successive approximation register signals
"no match" on line 170, i.e. an apparent PR fault, and signals the
control logic 160 to unload the pa-ttern.
The "no match" output 170 of register 162, which
is actually the 10th bit (A9) of the successive approximations register
(assuming 512 templates) is also applied to one input of an OR gate
172 (see Figure 6), the other input of which receives the DV fault
signal from dimensional veriFication means 34. The output of OR gate
172 on line 17~ is applied to the clustering means 38, shown in more
detail in Figure 6.
As mentioned previously, -the clustering means 38 serves
to cluster and weight the "fault" signals from the dimensional
verification means 34 and the pattern recognition means 36,
respectively. Thus, the circuit accumulates the D~ and PR faults
detected and assigns a relative weight or degree of confidence to them.
Referring to Figure 6, the relative weights of the DV
and PR faults are applied to respec-tive inputs of a multiplexer 180.
Switching of the multiplexer 180 is controlled by the output signal
-from OR gate 172 in the pattern recogni-tion means 36 (see Figure 5).
The 4-bit output o-f-the multiplexer 180 is applied to one input of
19
summing means 182. The outpu-t oF summing means 1~2 is latched by latch
184. The 8-bi-t output of latch 184 is applied to the second input of
summing means 182 and to the inpu-t of a 8K x 8 random access memory
(RAM) 186. When a DV or PR fault is detected, the appropriate weight
(a 4-bit integer selected by MUX 180) is accumulated by the la-tch
184 and summer 182. The ~unction of the latch 184 and summing means
182 is to accumulate weighted PR and DV faults for individual cells or
discrete areas of the printed circuit board being scanned.
The strip being inspected is divided into cells eacn 128
x 128 pixels, as illustrated in Figure 8. Such division is performed
by four counters 190, 192, 194 and 196. Counter 190 is a 128-pixel
counter clocked by the system clock and reset by the reset signal. Its
output is applied to counter 192 which counts the number of such cells
in the "X" or line scan direc-tion, ~Ihich in the specific example
comprises 2048 pixels, or 16 cells.
Coun-ter 194 is clocked by the line sync signal from the
camera via line driver 60 (Figure 2) and reset by the reset signal. lt
counts the number o~ lines in the "Y" direction or PCB travel direction
up to a maximum of 128 lines. Its output is applied to counter 196
~hich counts the number o-f 128-line cells in the "Y" direction i.e.
along -the length o-f the PC8. Typically this is the 24 inch dimension
of the usual 18 inch x 24 inch board and is equal to 24,000 pels or 190
cells at 1 mil resolution. Thus each strip scanned in one pass by the
respective camera comprises 2048 x 24,000 pixels (~ 0.001 inch
resolution) or 16 ~ 190 cells. ~he outputs of X-cell counter 192 and
Y-cell counter 196, respectively, are applied to the address input of
RAM 186. They prnvide the address o~ each cell for ~Ihich PR/D`I fault
indications or "counts" are being accumulated in RAM 186.
Thus~ in opera-tion of the clustering means 38, -the
coun-ters 190-196 generate cell addresses for the RAM 1~6 and keep a
running record of to which cell the current centre elemen-t (CE)
belongs. When a DV or PR fault is found, its corresponding "weight" is
added -to the count at the appropriate location in the RA~ 186.
Providing that the RAM 186 has been cleared at the outset, when the
entire strip of the PCB has been scanned, the total weight or score for
each cell will be stored in the RAM 186. The contents of the RAM 186,
outputted to the host processor 40 on line 198, can be read by the
processor 40, which checks the "scores" of the different cells and
notifies -the operator of any cells with an excessive "score".
The weighting of the DV and PR fault indications can be
done conveniently by a data multiplexer 180. The relative
contributions will need to be selected according to the article being
inspected, In practical embodiments for -inspecting 18 inch x 24 inch
CAD-produced PCBs, relative contribution of 4 or 5 PR faults to l DV
fault was sa-tisfactory. Thus, every DV fault was multiplied five times
before being entered into the RAM 186 (giving it more importance).
Thus, if the 4-bit inputs to MUX 180 are 001(1) for PR and 0101(5) for
DV, then five near PR faults will be equivalent to a single DV fault.
Instead of clustering fault indications in cells, the
clustering means and processor may cluster on an individual basis,
Then each individual ~Ifault~ location is stored and d search made for
-fault indications in neighbouring locations. If a predetermined number
of such faul-ts are found within a predeterrnined radius (hence a
cluster), -they are deemed to indicate a true defect.
21
~;~2~ 3
A potential problem in cell-partitioning is that
clusters occurring at the boundary of a cell may be divided into
different cells. In such a case, the individual cells concerned might
not have enough fault indications to initiate a defect report by -the
processor 40. The problem may be resolved by generating slightly
overlapping cell arrays as illustrated in Figure 9. The overlap
illustrated is one half of the cell si7e in each direction. Possible
ambiguities are then limited to the circled poin-ts which are where the
boundary between two cells in one array intersects the boundary bet~een
two cells in -the other array. If elimination of these potential
ambiguities is desired, a third array of cells may be provided.
To implement these modifications requires, for each
additional cell array, extra random access memory and counters for the
appropriate cell sizes and offsets.
Various other modifications are comprehended by the
present invention. Thus the image-acquisition process could be carried
out by a laser scanner ra-ther than the cameras and conven-tional ligh-t
sources described herein.
Also, rather than have a plurality o-f cameras and one or
20 Inore passes of the PCB in the same direc-tion, a single camera might be
provided and the camera and PCB moved relative to each other to scan
the entire area. The positioning of these elements is particularly
suited to testing PCBs which are laid out using, for example,
computer-aided design. Generally such PCBs (and hence spaces
25 therebetween) -tending to have only four possible orientations, vis.
longitudinal, lateral and both oblique directions. The dimensions will
be determined by the particular artwork. If the minimum conductor
~;~2~
width is equal to -the minimum spacing only once circle need be used.
Bonversely, if more dimensions are to be monitored, additional circles
may be provided.
Where the elements used for dimensional verification
comprise two or more groups, they need not have -the same reference or
datum element (the centre element CE in the specific example).
Likewise, the set of elements used -for dimensional verification need
not have the same datum as the set of elements used for pattern
recogni-tion. However, if different datums are used, -the clustering
means will need to account for any offsets.
It will be appreciated that the described configuration
of -the dimensional verification set of elements is suited to PCBs laid
out using CAD rules, which specify that the conduc-tors be hori~ontal,
vertical, or at 45 (oblique) thereto. Accordingly, for other
layouts a different configuration might be used.
It 1s also envisaged tha-t clustering might be done by
the processor, using a software module, rather than the circuitry
described herein.
