Note: Descriptions are shown in the official language in which they were submitted.
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~XT~L~IAL INT~RFAC~ CONTROL ~'IRCUIT~Y
FOX ~IICROCO~I~UT~R SYSTEMS
B _ round ox the Invention
The present invention relates generally to external
interface circuitry for data processing systems, and more
particularly to a controlled interface for coupling
an external device to microcomputer systems.
In prior art computer systems, interface circuitry
and peripherals have been typically added to such systems
by means ot buffering interface signals including
address, data and control lines In such systems, the
interface circuitry is powered up when the computer
system is switched on. Specialized interfaces, such as
che ~S-232 incer~ace, have also been developed where
special devices are required and special data transfer
protocols are used however, none of these prior art
computer systems has a controlled interface which îs
powered up and powered down in an orderly fashion
depending on whether an external device or peripheral is
present.
sects and Summarv of the Invention
__._ _
Accordingly, it is an object of the present
invention to provide improved interface control circuitry
2~ for coupling data processing circuitry to an external
device
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It is the further object ox the present invention to
provide an improved interface control circuitry that
powers up and down an external device depending on the
presence and operating conditions thereof.
S Briefly described, the present invention encompasses
interface control circuitry for coupling data processing
circuitry to an external device. The external device
includes circuitry for producing an indication signal
when it is coupled to the interface control circuitry and
also circuitry for producing a ready signal in response
to the application of power to the external device. The
interface control circuitry comprises circuitry for
applying power to the external device in response to a
power control signal; and circuitry for applying
interface signals prom the data processing circuitry to
the external device in response to an interface control
signal. The data processing means is responsive to the
external device indication signal for producing the power
control signal and responsive to the external device
ready signal for producing the interface control signal.
Thusl both power and the interface signals from the data
processing circuitry are not applied co the external
device until both the external device indication signal
indicates that the external device is coupled to the
~5 interface control circuitry ana the external device
produces the ready signal.
Brief Description of the Drawings
inure 1 is a block diagram of an external device
an a microcomputer system embodying the present inven-
lion
~0 figure 2 is a detailed circuit diagram of the bus
control in tune 1.
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Figure 3 is a detailed circuit diagram of a typical
external device in Figure lo
Figure 4 is a flowchart of the process steps
executed by the microcomputer in Figure 1 for controlling
an external device.
igure 5 is a timing diagram for selected slgnals
coupled between the microcomputer system and external
device in figure 1.
retailed Description of the Preferred Embodiment
In Figure 1 there is illustrated a data processing
system including an external device ~00 which is coupled
to microcomputer system 100 embodying the present
invention, external device ~0 may be any of a number of
peripheral devices such as, for example, read only
memories, random-access memories, printers, light pens
IIODE~I~ and other data processing perlpherals. Hero
computer system 100 includes microcomputer 10~, bus
control 104, peripheral interface adapter 106 and power
switch 108.
In the preferred embodiment of the present
invention, microcomputer 102 is a Llotorola type il68Ul
single chip microcomputer, aithough any suitable computer
or microcomputer could be utilized in practicing the
present invention. Peripheral interface adapter 106 is a
~lotorola type tlCl 46823 PIA. Power switch 10~ is
preferably an Intersil type ICL7663 programmable voltage
re~ulacor which converts Vcc provided by a +7.5V
bactery flown to -TV of +5V.
Power switch 1~8 turns on or off in response to the
P~C* control signal Power switch 10~ produces a
swicched +V supply voltage from the Vcc supply
voltage of the microCOMpUter systern 100. The speciric
circuicry in bus control 104 is shown in Gore detail in
~'igure I. PIA 106 is coupled to microcomputer 1~2 by way
~L2~3~
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of address, data and control lines and produces the
peripheral disable signal PD* and peripheral control
signal PC and receives the ready/interrupt request signal
READY*/IR~* and the peripheral inserted signal PI* from
external device 800 by means of buffer gates. Pull up
resis-tors couple the READY*/IRQ* signal and the PI*
signal -to corresponding supply voltages for maintaining
these signals at preselected voltage states.
Referring next to Figure 2, there is illustrated a
detailed circuit diagram of bus control 104 in Figure 1.
Address signals A8-A17, address/data signals AD0-AD7 and
control signals AS, E, R/W*, AV*, SD0 and SDI from micro-
computer 102 are coupled by bus control 104 to external
device 800. All of the signals coupled by a Gus control
104 between microcomputer 102 and external device 800 are
gated with the PD* signal such that whenever the ex-ternal
device 800 is disabled, all signals applied by bus
control 104 to external device 800 are at a binary zero
state Since the preferred embodiment of bus control 104
is comprised of CMOS devices, it is preferable that all
interface signals applied to external device 800 be at a
binary zero state for preventing SCR latch-up of the CMOS
devices. Moreovex, the interface signals are not applied
to external dev.ice 800 unless the external device 800 is
present and has responded to microcomputer system 100 with
the READY* signal.
Referring more specifi.cally to Fi.gure 2, address
siynals A8-A17 are gated with the PD* signal and applied
to ex-ternal device 800 by means of eight gates, one of
which is shown in block 202. The address/data signals
AD0-AD7 are also gated with th.e PD* signal and applied to
the external device by way oE eight bidirectional gates,
one ox which is shown in block 206. Address signals
present on the AD0-AD7 signals are demultiplexed and
storecl in latch 20~ for application -to external device
800 as address signals A0-A7. The control signal or
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enabling latch 204 is supplied by gate 210, and the
control signal for controlling the tri-state buffers in
gates 206 is supplied by or yate 2Q8.
In-terface signals AS, En R/W* and AV are likewise
5 yated with the PD* signal by gates 212, 213, 214 and 215,
respectively and applied to external device 800. Serial
interface siynals S~0 and SDI are coupled by tri-state
buf:~ers 222 and 221, xespectively, which are controlled
by the PD* siynal. The serial interface signals SD0 and
SDI may be utilized with additional circuitry to provide
serial data interface, such as, for example an RS-232
interface.
Referring next to Figure 3, there is illustrated a
detailed circuit diagram of an external device 800 that
includes a random-access memory (RAM 302. R~ 302
together with address decode circuits 304 and delay gates
308 may be provided on a printed circuit board which is
insertable into a connector ox microcomputer system 100.
When inserted, signal PI* is coupled to ground for
providing a signal indicating that 302 has teen
inserted into microcomputer system 100. Delay circuit
308 is coupled to~the PC signal and the +V voltage, and
may consist of a number of cascaded buffer gates for
producing the READY* signal. address decode circuits 304
may include logic gates which are coupled to address
signals A13-A17 and control signals AV* and PC for
decoding a particular address assigned to R~ 302.
Address signals A0-A12 are applied to the A0-A12 inputs
oE RAM 302. Data signals AD0-AD7 are applied to data
inputs D0-D7 of Al 302. Control signals R/W* and E are
applied to inputs R/W* and CS2 of RAM 302. In addition
the control signal E is coupled to inverting gate 306 and
applied to input OE* of RUM 302. RAM 302 may be an
Hitachi HM6264 type 8KX8 JAM.
According to the present invention, JAM 302 is
powered up by microcomputer system 100 whenever the
microcomputer system requires the use of the memory
a3
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locations provided thcreby. Thus, for example, KA~I 302
may be powered up when a particular subroutine requiring
a large scratch pad memory is executed by microcomputer
102. Since it is desired to conserve current drain from
from the +V supply, RAM 302 need only be powered up when
that particular subroutine is executed. This unique
feature of the present invention minimizes current drain
from the TV supply, which is typically sourced from a
battery. ~1any other types of external devices ~0, such
as printers, read-only memories, telephone line ~1~D~Is,
RF ~1ODE~Is, light pens, and other data handling apparatus,
may be utilized with microcomputer system 100.
In Figure 4, there is illustrated a detailed flow-
chart of the process steps executed by microcomputer 102
whenever external device 800 is powered up and powered
down. ~Jhen external device ~00 is to be powered up, the
flowchart in ~`igure 4 is entered at START block 402. At
decision block 404, a check is maae to see if PI* signal
has a binary zero state. If not, JO branch is taken to
return. ~ihenever the I* signal has a binary one state,
an external device has not been inserted into micro-
computer system 100. If the I* signal has a binary zero
state, YES branch is taken to Dlock 41~ where che power
co the peripheral is turned on by producing a binary zero
~5 state of the ~S~* signal. Nexc, at block 412, a 0.5
second delay is produced to allow time for the external
device 800 to turn on and stabilize. Then, at block 413,
a 0.5 second timer is initialized. l'he LADY* signal is
checked at decision block 414 to determine if it is a
binary zero state. If not, RIO branch is taken co
decision block 415 where a check is made to determine ir
the 0.5 second timer has elapsed. Ir so, YES branch is
taken to block 4~ where the power is turned off by
producing a binary one state ox the ~S~* signal. Other-
wise, branch is taken back to decision block 414.
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If the READY* signal has a binary 2ero state, YESbranch is taken from decision block 414 in Figure 4, to
block 416 where the interface signals on the bus between
bus control 104 and external device 800 are enabled by
producing a binary one state of the PD* signal.
Thereafter, at block 41~ a binary one state is produced
on the O signal The PC signal is used to enable the
external device ~0~. In the case of KAM 3~ in ~'igure 3,
the O signal is part of the ~A~I address aecoded by
address decode circuits 304. At block 420, a two
microsecond timer is initialized. Then, at decision
block 422, a check is made to see if the RAY signal
has a binary one state. If so, YES branch is taken to
return indicating that the external device 800 has been
properly powered up. If not, JO branch is taken to
decision block 423 where a check is made to see if the
two microsecond timer has elapsed. If not, NO branch is
taken back to decision block 422. Otherwise, YES branch
is taken to block 424 for powering down the external
device.
Once external device 8~0 is properly powered up, the
R~A~Y*/IRQ* signal is treated as an IRK* signal for
interrupting microcomputer 1~2. The binary state of the
IRQ* signal is changed to a binary zero state by external
device 8~0 for requesting service. Once external device
800 is serviced, the IKQ* signal is changed back to a
binary one state.
Accoraing to an alternative embodiment of the
present invention, blocks 420, 422 and 423 may be
bypassed as indicated by dotter line 4~. In chis mode
ot operation, the R~ADY*/IR~* signal is treated as an
immediate request or service if the R~ADY~/L~* signal
remains at a binary Nero state after the O signal has
changed Jo a binary one state. Gnce serviced, the
external device ~00 wiLl change the R~ADY*/IR(~* signal to
a binary one stave. 'l'his unique mode of operation is
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utilized in the preferred embodiment of the present
invention.
Whenever external device 800 is to be powered down,
blocks 406, 4~4, 426 and 4~ are executed by
S microcomputer 102. External device 800 may be powered
down whenever it is not needed or whenever the external
device does not properly respona to the process steps
executed by microcomputer 102 during the power up
sequence. In other words, if external device 800 does not
properly sequence the binary states of the READY* signal,
the external device is powered down. The external device
is powered down if YES branch is taken from either
decision block 415 or decision block 423. During the
power down process, a binary zero state of the PC signal
is produced at block 4~4. text, at block 426, the bus
between bus control 104 and external device 800 is
disabled by producing a cinary zero state of the PD*
signal. Lastly, the power to external device ~00 is
turned of by producing a binary one state of the O
signal at block 4~8.
According to a further feature of the present
invention, the external device need not be powered down
when not in use but instead only disabled. This moae of
operacion is provided when microcompucer 102 executes
Dlocks 806, 824 and 826~ In chis lode, a binary zero
state of the PC signal is produced at block 824, ana a
binary zero state of the Pi* signal is produced at block
~26. If the external device 800 requires service, the
binary state of the R~A~Y*/IRQ* signal can be changea co
interrupt microcomputer 1~2. once interrupced,
microcompucer 102 executes the power-up rlowch~rc
be~innin~ at 8TA~T block 4U2.
The flowchart in Figure 4 provides a detailea
descripcion of the process steps executed by ulicro-
computer 1~2 ior powering up and powering down external
device ~00. The coding of tile process steps of the
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flowchart in Figure 4 into the appropriate instructionsof a suitable conventional microcomputer is a mere
mechanical step for one skilled in the art. By way of
analogy to an electrical circuit diagram, the detailed
flowcharts in Figure 4 are equivalent to a detailed
schematic for an electric circuit where provision of the
exact part values for the components of the electrical
circuit corresponds to provision of the actual computer
instructions for the blocks of the flowchart.
Referring next to Figure 5, there is illustrated a
tirning diagram of selected control signals coupled
between microcomputer system 100 and external device ~00.
waveform 504 illustrates the PSC* signal which turns on
and off power switch 108. then YSC* has a binary zero
state, +V is applied to external device ~00 by power
switch 108. Before the power up process, a binary zero
state is produced by external device ~00 on the PI*
signal, illustrated by waveform 510. Next, a binary zero
state is produced on the SO signal. The READY* signal
illustrated by waveform 512 then changes from a binary
one state to a binary zero state. Next, the YD* signal
changes fron1 a binary zero to a binary one state as
illustratea Dy waveform 506 Lor enabling the bus between
bus control 104 and external device ~0~. The Ye signal
as illustrated by waveform SUP then changes state from a
binary zero state to a binary one state for enabling
operation vf external device ~00. Iihenever it is desired
to power down external device ~00, the Y0` signal changes
from a binary one state to a binary zero state, followed
my change of the Pi* signal frorn a binary one state co a
binary zero scate and lastly, by a change of the YS~*
signal prom a binary zero state to a binary one state.
The changes in binary stave of the signals illustrated by
the waveforms in figure 5 take place in the order shown
~5 although the time between the changes in binary state may
l o
vary depending on actual delays in both the microcomputer
system 100 and external device ~00.
In sun~ary, unique interface control circuitry has
been described for coupling data processing circuitry to
an external device The external device is powered up
and down according to a unique process that insures that
the interface circuitry is only powered up when an
external device is present and that the state of the
interface sigrla1s is controlled to prevent destruction of
clevices in the interface control circuitry. The inter-
face control circuitry of the present invention can be
utilizecl in any application where data processing
circuitry interfaces to an external aevice.
