Note: Descriptions are shown in the official language in which they were submitted.
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The present invention relates to a dot-ma-trix
printer with a font cartridge which reads out character
pattern data stored in advance in a memory mounted in
the font cartridge, and prints in accordance with the
character pattern data.
In order to print a plurality of types of font of
characters, dot-matrix printers must have a read-only
memory (ROM) storing character pattern data of each
font. However, different fonts are usually used in
differen-t countries. For this reason, when dot-matrix
printers mount a ROM storing character pattern data for
each country, a ROM having a considerable memory
capacity is required, resulting in high cost. In order
to overcome such a drawback, a plurality of font
cartridges mouting ROMs or random-access memories ~RAMs )
storing a pluarlity of font of character pattern data
are prepared, and the desired font cartridge is mounted
on the dot-matrix printer so as to read out character
pattern da-ta of a desired font for printing. ~lowever,
with this method, when the font cartridge is mounted on
the dot-matrix printer, a control circuit of the printer
cannot recognize in which address area of the font
cartridge a memory is mounted, or whether a ROM or a RAM
is mounted. Therefore, it requires a complex operation
and extra time for this recognition.
It is an object of the present invention to
provide a dot-matrix printer with a font cartridge,
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in which a font cartridge mounting a memory storing
character pattern data of a plurality of fonts
is prepared, a memory mounting state in the font
cartridge can be easily recognized, and characters in
addition to standard characters of the printer can be
printed.
In order to achieve the above object, there is
provided a dot-matrix printer with a font cartridge unit
having the following arrangement. According to the
present invention, a dot-matrix printer with a font
cartridge unit comprises:
a font cartridge unit comprising a plurality of
read--only memories or read/write memories, having a
memory area divided into a plurality of page areasl for
storing various character pattern data in each page
area, and an input/output bus for inputting or
outputting the character pattern da-ta read out from the
read-only memories or the read/write memories;
detecting means for accessing a predetermined
address of each page area of the font cartridge unit
through the input/output bus so as to detect a mounting
state of the read only memories or the read/write
memories corresponding to the respective page areas in
accordance with a content of accessed specific read
data;
print control means for forming print data in
accordance with the character pattern data read out from
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the read-only memories or the read/write memories
mounted in the font cartridge unit in accordance with
the detection result of the detecting means;
connector means for connecting the input/output bus
of the font cartridge unit to the print control means
and the detecting means so as to transfer data between
the input/output bus and the print control means or to
transfer the specific read data between the input/output
bus and the detecting means; and
print means for executing a dot-print operation in
accordance with the print data formed by the print
control means.
With the above arrangement/ a dot-matrix printer
can detect a memory arrangement of a character pa-ttern
memory in a font cartridge unit. Therefore, the printer
main body can recognize a storage area corresponding to
predetermined character pattern data in the font
cartridge unit. Thus, characters in addition to
standard characters can be printed simply by loading the
font cartridge unit to the printer main body.
This invention can be more fully understood from
the following detailed description when taken in
conjunction with the accompanying drawings, in which:
Fig. 1 is a block diagram showing an arrangement o~
a dot-matrix printer with a font cartridge unit
according to the present invention;
Fig. 2 is a block diagram showing an arrangement of
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a printing mechanism controller of the presen-t
invention;
Fig. 3 is a memory map in the printer of the
presen-t invention;
Fig. 4 is a block diagram showing an arrangement
of a fon-t cartridge unit of the present invention;
and
Figs. 5A to 5C and Fig. 6 are flow charts for
explaining an operation of the present invention.
An embodiment of the present invention will be
described with reference to Figs. 1 to 6. As shown in
Fig. 1, a dot-matrix printer schematically comprises a
printing control unit 10 and a printing mechanism. The
printing mechanism comprises a print head 11, a carriage
motor 12 for driving a carriage on which the head 11 is
mounted, and a paper feed motor 13 for feeding paper.
The unit 10 comprises a microprocessor (CPU) 14, a
Eont ROM 15, a program ROM 16, a read/wri-te memory (RAM)
17, a printing mechanism controller 18 and a system bus
19. The CPU 14 is operated in accordance with a program
stored in the program ROM 16 in advance so as to control
the overall mechanism of the printer. The font ROM 15
stores character pattern data (font data) corresponding
to standard characters. The RAM 17 is a work memory
used when the CPU 14 forms print data. The controller
18 performs drive control of the print head 11, the
`; carriage motor 12 and the paper feed motor 13 in
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accordance with the print data and control data supplied
from the CPU 14.
A font cartridge unit 22 is connected to the unit
10 through a connector 21. The connector 21 is
detachable from the unit 10, and is connected to the
system bus 19 through a bus 20 when it is connected.
As shown in Fig. 2, the controller 18 comprises a
print data register 23 and a print head driver circuit
24 required for drive control of the print head 11. The
register 23 stores the print data transferred from the
RAM 17 through the system bus 19 under the control of
the CPU 14. The circuit 24 selectively drives dot pins
of the head 11 in accordance with the print data stored
in the register 23. Note that the print data consists
of character pattern data for one line.
Furthermore, the controller 18 comprises a phase
data register 25 and a carriage motor driver circuit 26
required for drive control of the motor 12~ and a phase
data register 27 and a paper feed motor driver circuit
28 required for drive control of the paper feed motor
13. The registers 25 and 27 store the various phase
data required for switching control of excitation phases
of the motors 12 and 13 as stepping motors. The circuit
26 supplies an excitation current to excitation coils o~
the motor 12 so as to drive it. The circuit 28 supplies
an excitation current to excitation coils of the motor
13 so as to drive it. The phase data is transmitted to
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the corresponding registers 25 and 27 through the system
bus 19.
Fig. 3 shows a memory map of the printer of the
present invention. A memory area accessed by the CPU 14
comprises the program ROM 16, the font ROM 1~, the RAM
17 and a page area 29. The page area 29 is constituted
by 8 pages, i.e., page 1 to 8 areas, and this portion is
mounted in the font cartridge. Each page area stores
character pattern data of one font. The CPU 14
designates pages so as to switch banks, thereby
accessing one of the eight page areas. The page 1 and 2
areas constitute a RAM area mounting a RAM, and the page
3 to 8 areas constitute a ROM area mounting a ROM. The
page 1 and 2 areas are used so that a central processing
unit of a system in which the printer of the present
invention is used transfers (down line loading) the
predetermined font of charac-ter pattern data ~o be
printed. The RAM area may or may not be backed up with
a battery. As shown in Fig. 4, the font cartridge unit
22 comprises a memory group consisting of RAMs 39 and 40
and ROMs 41 to 43, a page address register 30, a page
address decoder 31, and an I/O address decoder 32.
The RAMs 39 and 40 have a capacity sufficient to store
character pattern data of one font, respectively, and
correspond to the page 1 and 2 areas. The ROMs 41 to 43
each store character patterns of two types of fonts
.~; and correspond to the page 3 to 8 areas. In this
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embodiment, no memory chip is mounted in the ROMs 41 and
42.
The RAMs 39 and 40 are read/write memories storing
character pattern data corresponding to a predetermined
font. The register 30 stores a page address transferred
from the CPU 14 through the connector 21 when the
predetermined character pattern data is read out from
the ROMs 41 to 43 and the RAMs 39 and 40. The decoder
32 decodes an I/O address (direct address) transEerred
from the CPU 14 through the connector 21, and supplies a
clock pulse CK required for storage operation of the
register 30 to the register 30 in accordance with the
decoding result. The decoder 31 decodes the page
address supplied from the register 30, and supplies a
chip select signal CS to the ROMs 41 to 43 and the RAMs
39 and 40 in accordance with the decoding result. The
character pattern data is transferred from the ROMs 41
to 43 and the RAMs 39 and 40 to the unit 10 through an
I/O bus 35. The I/O bus 35 is connected to a pull-up
resistor 3B and a voltage Vcc is applied through the
resistor 38.
The operation of the dot-matrix printer with the
above arrangement will be described hereinaEter. When
the font cartridge unit 22 is loaded, a mountlng state
of memory elements in the entire memory area must be
recognlzed. The operation will be briefly described
with reference to the flow charts shown in Figs. 5A to
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5C. In step Sl, a counter variable N is set to "0".
The variable N indicates a page number being accessed.
In step S2, the variable N is incremented by one. In
step S3, in order to allow the CPU 14 to access a page
N, a page address A1 of the page N is set in the
register 30 through the buses 19 and 20, the connector
21 and the bus 35. In step S4, ID data is read out from
a specific address of the page N, e.g , a start address.
In this case, the CPU 14 transfers an address A2 for
designating an address in the corresponding page to the
decoder 32 through an address bus 36. The decoder 32
decodes the address A2 from the CPU 14 in accordance
with the I/O select signal from the CPU 14, and supplies
the clock pulse CK to the register 30 in accordance with
the decoding result. In synchronism with the clock
pulse CK, the register 30 stores the page address Al
from the CPU 14, and thereafter supplies it to the
decoder 31. The decoder 31 decodes the page address A1
from the register 30, and supplies the chip select
signal CS to, e.g.~ the RAM 39. Thus, the CPU 14 reads
out the ID data from the start address of the RAM 39
using the address A2. At a start address of each page,
data indicating that the page is the RAM or ROM, data
indicating the font stored in the page, and the like are
stored. It is checked in step S5 if the data read out
from the start address of the page is the ID data. That
is, since the RAM may or may not be backed up with
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a battery, it is checked in step S5 whether or not the
RAM is backed up with the battery. If YES in step S5,
i.e., if the readout data is the ID data, a flag "B"
indicating that the battery backed-up RAM is mounted
in the page 1 area is written in the RAM 17 in step S6,
and the flow returns to step S2. If WO in step S5,
predetermined data "F0" (excluding "FF" in sexadecimal
notation) is written at a predetermined address, e.g.,
the start address of the paqe 1 area, and thereafter the
data is read out, as shown in steps S7 through S9.
Then, it is checked if the readout data is the data "FF"
in sexadecimal notation. In other words, the CPU 14
supplies a write signal to the RAM 39 through a memory
read/write line 34 so as to write predetermined data
therein. The reason for checking in step S9 if the
readout data is "FF" is to check if a memory chip is
mounted in the RAM 39 corresponding to the paqe 1 area.
If data is read out from an address at which no memory
chip is mounted, since the ~us 35 is pulled up, data
"FF~ is obtained as if data "FF" were read out. If the
readout data in step S9 is "FF", it is determined that
the memory chip is not mounted. In step S10, a flag
"RO" indicating no RAM is mounted in the page 1 area is
written in the RAM 17. If NO in step S9, it is checked
in step Sll if the readout data coincides with the data
"F0'l written in step S7. If YES in step Sll, a flag
'IRl'' indicating that a RAM is mounted in the page 1 area
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is written in the RAM 17. If NO in step Sll, a fl.ag
"El" indicating that a RAM is mounted in the page 1 area
but is mal:Eunctioning is written in the RAM 17. When
the above-menkioned operation is repeated until YES in
step S14 is obtained, it can be detected whether or not
RAMs are mounted in the page 1 and 2 areas.
If YES in step S14, the flow advances to step S15.
In steps S15 through S24, it is detected whether or not
a ROM is mounted in the page 3 to 8 areas in the ROM
area. If YES in step Sl9 (if the ID data readout from
the page N is the data "FF"), the flag "M0" which
indicate that the ROM is no~ provided in the page N
area, is written in the RAM 17 in step 20. If NO in
step 21 (i~ the data readout from the page N is not the
ID data), the flag "E2", indicating that the ROM
provided in the page N operates erroneously, is written
in the R~M 17 in step 22. If YES in step 21, the Elag
"Ml", indicating that the ROM is provided in the page N
area, is written in the RAM 17 in step 23.
After the above-mentioned detection, the CPU 14
switches memory access to the unit 22 side in accordance
with a print character code supplied from the host
computer. As shown in step S30 of Fig. 6, the CPU 14
sets a predetermined page address Al corresponding to
the print character code in the register 30 through the
buses 19 and 20, the connector 21 and the bus 35. In
this case, the CPU 14 transfers a direct address A2 for
designating an address in the page to the decoder 32
through the bus 36. The decoder 32 decodes the direct
address ~rom the CPU 14 in accordance with an I/O select
signal received from the CPU 14 through the control
signal line 33, and supplies the clock pulse CK to the
register 30 in accordance with the decoding result. The
register 30 stores the page address Al from the CPU 14
in synchronism with the clock pulse CK, and thereafter
supplies it to the decoder 31. The decoder 31 decodes
the paye address Al from the register 30 and the direct
address A2 from the CPU 14, and supplies the chip select
signal CS to, e.g., the ROM 43. Thus, as shown in
Fig. 3, the ROM 43 having the storage area, e.g., page 7
and 8 areas storing high~density character pattern data
corresponding to the print character code is selected.
In step S31, the CPU 14 accesses the ROM 43 using
the page address Al, e.g., designating the page 7 and 8
areas and the direct address A2 designating the address
in the corresponding pages, thereby reading out
character pattern data constituting the predetermined
high-density dot character pattern from the ROM 43. The
CPU 14 supplies a read control signal RD to the ROM 43
through a memory read line 37, and reads out the
character pattern data from the ROM 43 through the bus
35, the connector 21 and the buses 20 and 19.
The CPU 14 writes the character pattern data read
out from the ROM 43 in the storage area of the RAM 17
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designated by the direct address A2, in step S32. The
CPU 14 repeats the read operation of the character
pattern data from the ROM 43 until the character pattern
data for one character is read out and is stored in the
RAM 17. This processing is repeated in accordance with
discrimination of step S33 until the character pattern
data for one character is read out from the ROM 43 and
is stored in the RAM 17. Furthermore, the CPU 14
repeats the read operation from the ROM 43 in accordance
with discrimination of step S34 until the character
pattern data for one line is developed in the RAM 17.
When the character pattern data for one line is
developed in the RAM 17, the CPU 14 switches page
addresses required for reading out the character
pattern data corresponding to the print chaarcter code
(step S36). The CPU 14 switches the page address
corresponding to, e.g., the page 7 area to that
corresponding to, e.g., the page 8 area, and sets it in
the register 30 shown in Fig. 4. Thus, the CPU 14 reads
out the character pattern data stored in the page 8 area
of the ROM 43, and stores it in the RAM 17.
In this manner, when a print character code
corresponding to characters other than standard
characters is transmitted from the host computer, the
CPU 14 reads out, e.g., the high-density character
pattern data corresponding to the print character code
from the ROM 43 of the unit 22. When the high-density
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character pattern data Eor one line read out from the
ROM 43 is developed in the RAM 17, the CPU 14 executes
the printing operation in step S37. The CPU 14 supplies
the print data including the character pattern data from
the RAM 17 to the controller 18 in the same manner as in
the dot printing operation of standard characters. The
controller 18 controls the head 11 in accordance with
the high-density character pattern from the register 23
shown in Fig. 2. Thus the head 11 prints a character
corresponding to the high-density character pa-ttern data
on the paper sheet.
The CPU 14 recognizes a memory arrrangement in the
unit 22 with respect to the ROMs 41 to 43 and the RAMs
39 and 40 in which a storage area is divided into page
areas. Thus, the CPU 14 executes printing processing,
eOg., as shown in Fig. 6 if the arrangement of the
memory group in the unit 22 is as shown in Fig. 4. If
the ROM 43 shown in Fig. 4 is no-t mounted, th~ CPU 14
interrupts readout of the character pattern data from
the ROM 43, and executes processing indicating that
printing of the character pattern data stored in the ROM
43 cannot be performed. When the RAMs 39 and 40 are not
present, the CPU 14 interrupts the read/write operation
with respect to the RAMs 39 and 40, and executes
processing indicating that printing of character pattern
data stored in the RAMs 39 and 40 cannot be performed.
According to the present invention, the CPU 14 at
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the printer side can recognize the storage area (page
area) corresponding to the predetermined character
pattern data in accordance with the arrangement of the
memories in the unit 22. For this reason, when the ROMs
41 to 43 and the RAMs 39 and 40 are present in the unit
22 and the arrangement thereof is unknown, the CPU 14 at
the printer side can recognize the storage area
corresponding to the predetermined character pattern
data. Therefore, characters other than the standard
characters can be printed simply by loading the font
cartridge unit to the printer main body.
