Note: Descriptions are shown in the official language in which they were submitted.
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BACKGROUND OF THE INVENTION
The present invention broadly relates to circuit
boards and, more specifically, pertains to a new and improved
arrangement of and method for manufacturing multisubstrate or
multilayer circuit boards.
Generally speaking, the circuit board arrangement
of the present invention comprises a multiple substrate circuit
arrangement between individual metal layers applied to mutually
insulated and mutually pressure-bonded support elements and
separable into contact surfaces, conducting traces or both.
In other words, the multilayer circuit board of the
present invention comprises a substantially planar first
support element, a substantially planar second support element
and a substantially planar insulative element for bonding the
first support element and the second support element together.
The first support element has a first side remote from the
second support element and a second side confronting the second
support element and bonded to the .insulative element. The
second support element has a first side remote from the first
support element and a second side confronting the first support
element and bonded to the insulative element. The first side
of the first support element is provided with a metal layer and
the second side of the first support element is provided with a
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metal layer. The first side of the second support element is
provided with a metal layer.
The method of the present invention relates to for
fabricating a multiple substrate circuit arrangement and
electrical intexconnections thereof.
A circuit arrangement having a plurality of
superimposed printed circuit boards as well as a process for
interconnecting the individual circuit boards of the plurality
are known from German Patent No. 2,103,767. The circuit boards
are separated from each other by an insulating layer and the
appropriate holes can go through the whole layered block or,
alternatively, only through individual layers. Solder-coated
or pre-tinned spiral springs are inserted in these holes. This
multilayered arrangement employs only such electrical
interconnection between the separate circuit boards as can be
achieved by merely heating the solder-coating or tinning on the
springs.
SUMMARY OF THE _NVENTION
Therefore, with the foregoing in mind, it is a
primary object of the present invention to provide a new and
improved arrangement of a multilayer circuit board of the
previously-mentioned type and a method for fabricating such a
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circuit board and its electrical interconnections which do not
exhibit the aforementioned drawbacks and shortcomings of the
prior art constructions.
Another and more specific object of the present
invention is to provide a multisubstrate or multilayer, i.e.
multiple-plane, circuit arrangement as well as a method of
manufacturing such a multisubstrate circuit arrangement and the
electrical connections thereof in which a reduction of the
number of substrate carrier elements and simultaneously a
smaller construction unit is realized while retaining a
relatively high connection density (packing density) in a
minimum amount of space.
Yet a further significant object of the present
invention aims at providing a new and improved construction of
a multisubstrate circuit arrangement of the character described
which is relatively simple in construction and design,
extremely economical to manufacture, highly reliable in
operation, and not readily subject to breakdown or malfunction.
Now in order to implement these and still further
objects of the invention, which will become more readily
apparent as the description proceeds, the multiple substrate
circuit arrangement of the present invention is manifested by
the features that the multiple substrate circuit arrangement is
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fabricated as a pressure-bonded, three-layer multiple
substrate. This pressure-~onded, three-layer multiple
substrate comprises a component plane, an intermediate plane
and a ~ottom or lower plane. Tn~s multiple su~strate circuit
arrangement compr~ses a douale-sidedly metallized support
element defining a f~rst support element of the mutually
insulated and mutually pressure-~onded support elements. The
multiple substrate circu~t arrangement compr~ses a single-
sidedly metallized support element defines a second support
element of the mutually ~nsulated and mutually pressure-~onded
support elements, and th.e multiple suDstrate circuit arrange-
ment st~ll further comp~ises an ~nsulat~ve element arranged
~etween the first support element and the second support
element. The component plane has an exposed metal layer
defining a ~irst ~etal l~yer of th.e individual metal layers,
while th.e ~ottom or lo~er plane has an exposed metal layer
de~ning a second met~l layer o~ the individual metal layers.
A t~rd ~etal layer o~ th.e ind~v~dual metal layers de~ines a
sandwic~.ed metal layex. T~e ~ t metal layer and the second
metal layer are electr~cally connected to th.e ~ni~d metal
laye~ ~y metallized Dl~nd holes, and the flrst metal layer
and the second metal layer are mutu~lly electrically
interconnected ~y metallized through.holes.
In ot~er wo~ds, the multilayer circuit ~oard of the
present inVenti~n ~s man~fested ~y the features that the first
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support element is provided with blind holes extending from the
first side of the first support element through the metal layer
of the second side of the first support element, the blind
holes of the first support element are metallized for
electrically interconnecting the metal layer of the first side
of the first support element with the metal layer of the second
side of the first support element, the second support element
is provided with blind holes extending from the first side of
the second support element through the insulative element and
through the metal layer of the second side of the first support
element, the blind holes of the second support element are
metallized for electrically interconnecting the metal layer of
the second side of the first support element with the metal
layer of the first side of the second support element,
predetermined ones of the blind holes of the first support
element axial:Ly coinciding with predetermined ones of the blind
holes of the .second support element such that through holes are
formed extending ~rom the first side of the first support
element to the first side of the second support element and the
through holes are metallized for electrically interconnecting
the metal layer of the first s:ide of the first support element
with the metal layer of the first side of the second support
element.
The method of the present invention is manifested
by the features that it comprises the steps of etching a metal
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layer of an intermedia~e plane to form conductor traces,
pressing together a first support element, an insulative
element and a second support element for bonding the first
support element to the second support element to form a
construction unit, subsequently boring a first plurality of
holes in accordance with a first hole schedule and extending
between a metal layer of a component plane and the conductor
traces of the intermediate plane at programmatically
predetermined locations, inverting the construction unit,
subsequently boring a second plurality of holes in accordance
with a second mirror-image hole schedule and extending between
a bottom plane and associated conductor traces of the
intermediate plane at programmatically predetermined locations,
metallizing all holes of the first plurality of holes and the
second plurality of holes for electrically interconnecting the
component plane, the intermediate plane and the bottom plane,
fabricating contact surfaces and conductor surfaces in mutual
spaced relationship in said component plane by etching and
fabricating correspondingly arranged conductor traces in the
bottom plane by etching.
In other words, the method of the present invention
is manifested by the features that it comprises the steps of
photo-etching a first metal layer provided on a second side of
a substantially planar first support element to form a desired
one of conductor traces extending substantially parallel to a
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predetermined direction, conductor traces extending
substantially perpendicular to the predetermined direction and
conductor traces extending both substantially parallel and
substantially perpendicular to the predetermined direction,
pressure-bonding the first support element to a substantially
planar second support element by the intermediary of a
substantially planar insulative bonding element to form a
multilayer circuit board blank, boring a plurality of blind
holes extending from a second metal layer provided on an
exposed first side of the second support element through the
insulative bonding element and through desired ones of the
conductor traces formed on the second side of the first support
element at desired locations, inverting the multilayer circuit
board blank, boring a plurality of holes extending from a third
metal layer provided on an exposed first side of the first
support element through desired ones of the conductor traces
formed on the second side of the first support element at
desired locations such that desired holes of the plurality of
holes axially coincide with desired holes of the plurality of
blind holes to form through holes extendi.ng from the first
metal layer to the third metal l~yer and such that remaining
holes of the plurality of holes form blind holes, metallizing
all holes of the blind holes and the through holes for
electrically interconnecting the first metal layer with desired
ones of the conductor traces formed on the second side of the
first support element for electrically interconnecting the
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third metal layer with desired ones of the conductor traces
formed on the second side of the first support element and for
electrically directly interconnecting the second metal layer
with the third metal layer independently of the conductor
traces formed on the second side of the first support element,
photo-etching the second metal layer to form a desired
configuration of contact pads and power conducting traces, and
photo-etching the third metal layer to form conductor traces
extending substantially parallel to the predetermined
direction.
BRIEF DESCRIPTION OF THE DRAWINGS
. _
The invention will be better understood and objects
other than those set forth above will become apparent when
consideration is given to the following detailed description
thereof. Such description makes reference to the annexed
drawings wherein throughout the various figures of the drawings
there have been generally used the same reference characters to
denote the same or analogous components and wherein:
Figure 1 schematically shows a multisubstrate
circuit arrangement as an embodiment of the invention in
cross-section and on an enlarged scale; and
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Figure 2 schematically shows the circuit
arrangement of Figure 1 in exploded perspective view.
DETAILE~ DESCRIPTION OF THE PREFERRED EMBODIMENTS
Describing now the drawings, it is to be understood
that to simplify the showing thereof only enough of the
structure of the multisubstrate circuit arrangement has been
illustrated therein as is needed to enable one skilled in the
art to readily understand the underlying principles and
concepts of this invention. Turning now specifically to Figure
1 of the drawings, the structure illustrated therein by way of
example and not limitation will be seen to comprise a three-
layer superimposed or laminated multisubstrate circuit
arrangement which essentially comprises a first substrate 10
serving as a first support sheet or laminate as well as a
second substrate 20 serving as a second support sheet or
laminate. A pre-impregnated insulative sheet material 30, such
as for instance the commercially available product Prepreg, is
employed as an adhesive or bonding agent and as an insulator
between the first and second substrates 10 and ~0. The first
substrate 10 is coated on first and second sides thereof with a
not particularly referenced suitable metal layer which is
etched into separate, mutually spaced, conducting tracks or
traces using a known photolithographic process of semiconductor
technology, i.e. photo-etching. The second substrate 20 is
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coated on a first side only thereof with a not particularly
referenced suita~le metal layer whic~ is also, as described
a~ove, suh-divtded tnto indiv~dual contact surfaces or pads or
into conducting tracks ~r traces ay etch~ng.
The circu~t arrangemen~ tS presented ~n exploded
perspective v~e~ in Figure 2 and ~ithout t~e sheet of
insulative material 3Q. T~e second su~strate 2Q having
mult~ple contact surfaces ox pads 22, 23, 24, 25, 26, 26' and
27 etc~ed ~rom the met~l layer as ~ell as a conduct~ng track
or trace 28 used as an electr~cal current supply track or rail
and electrically connected to the contact surface 26 ~y a path
or trace 26', can ~e recogn~zed, Furthermore, the first
su~strate 10, ~h~cH.~s provided wit~ conducting tracks ar
traces 31, 32, 33, 34, 35, 36 and 37 formed from a metal
layer on the second side o~ the ~irst su~strate lQ facing t~e
second su~strate 2Q and which ~u~th.er i`5 pxov~ded with con-
ducting trac~s or txaces 13, 14, 15, 16, 17 and 18 etc~ed
~om th.e ~etal layer on t~e ~rst s~.de c~ tn.e ~irst su~trate
lQ. ~ci~ng aw~y~rom t~e second suPstrate 2U, can ~e
~ecogn~zed. T~.e canducting t~ac~s~ ~r tr~c~s 31 to 37
P~ovided on tH.e second s~de ~ac~g t~e second subs~t~ate 2a
can ~e o~ented suhstant~lly ~n e~,ther of two mutually
orthDgonal d~rections indic~ted ~y~the dou~le-h.eaded ar~ows X
and X in Figure 2 or in ~oth.of these di~ections, wh~le the
conducting tracks or traces 13 to 18 arranged on the under or
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first side of the first substrate 10 may be oriented
substantially in only the direction indicated by the arrow Y.
The conducting tracks or traces 13 to 18 as well as
31 to 37 provided on the first substrate 10, as well as the
contact surfaces or pads 22 to 27 and the current supply track
or rail 28 provided on the second substrate 20, are etched from
the actual metal layers according to a program (CAD). The
metal layers can consist of, for example, a bonded copper foil
or of a vapor-deposited or sputtered copper layer, or the like.
The electrical contacts in the circuit arrangement
described above must not only be established between the
contact surfaces or pads 22 to 27 on a component plane
indicated by the arrow A and the conducting tracks or traces 31
to 37 in an intermediate plane indicated by the arrow B and
oriented in the X or Y direction, or both, but also, as
illustrated in Figure 1 and Figure 2, must be established
between the contact surfaces or pads 22 to 27 of the component
plane A, the conducting tracks or traces 31 to 37 of the
intermediate plane B and the conducting tracks or traces 13 to
18 of a lower or bottom plane of the first substrate 10
indicated by the arrow C and oriented in the Y direction. The
contact surfaces or pads 22 io 27, the contact tracks or traces
31 to 37 as well as the sontact tracks ox traces 13 to 18 can
hereby be displaced in the X or Y direction, or both, in
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relation to each other. Essentially, this is achieved ~y a
processing step wherein a first set of holes 1', 3", 4', 6'
and 7' is ~ored in thedirections indicated ~y the arrows 1, 3,
4, 6 and 7. The holes are bored, for instance using a first
hole schedule ~CAD-data~, at pre-programmed locations ~here an
electrical connect~on ~etween the metal layer o~ the component
plane A and the corresponding conducting tracks or traces of
the intermediate plane B are to ~e esta~lished. The holes are
bored after t~.e conducting tracks ~r traces in t~e intermediate
plane B ha~e ~een etc~ed and the separate elements 10, 20 and
3Q have ~een ~onded into a 6ingle unit.
The uni.t ~.s inyerted ~n a ~econd processing step
and positioned ~,n suc~ a manner tnat, at pre-programmed
locations ~nere an electr~c~l connect~on ~etween the metal
layer o~ the lo~er or ~ottom plane ~ and the corresponding
conducting trac~s or traces of the intermed~ate plane B are to
~e esta~lis~.ed, a second set o~ holes 2~, 3", 5~ and 6" is
~ored uslng a second ~o~ed ~Ple schedule ~CAD-datal ~n the
directions ~ndicated ~y t~e ar~ow~ 2, 3~, 5~ and 6~. T~e holes
1~, 2~, 4~, 5~ and 7 t are sh~ s~ ~lin~ noles i`n ~gure 1.
The hole$ 3" and 6'~, due to t~e do~ s~ded boring process,
~ecome th.rough holes. T~e ~oles 1~, 2~, 3~, 4~, 5l, 6" and 7'
are metallized ~,n a thi`rd process~ng step wherein electrical
interconnection o~ th.e met~ ers of the separate planes A, B
a,nd C ~s ach.~eved. The contact sur~aces or pads 22 to 27, as
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well as the current supply track or rail 28 on the component
plane A and the conducting tracks or traces 13 to 18 oriented
in the Y direction on *he lower or bottom plane C, are now
produced by etching.
