Note: Descriptions are shown in the official language in which they were submitted.
cxcc~- Ç2 '-I 1
INTEGRATED VOICE/DATA/CONT~OL SWITCHING SYSTEM
Background of the Invention
This invention relates to digital voice/data/control
switching systems and more particularly to circuitry for
communicating voice data and control information to and
from a local communication station in a serial, time
multiplexed signal stream.
As the complexity of data communications networks
increases the need for simpler and more economical
methods of interfacing the various devices on the networks
becomes critical. Simple interconnection between two
devices such as two telephones or such as a computer and a
terminal can be accomplished quite easily. For example,
communications can ye established between devices with one
wire, such as was done with an early telegraph system.
Though each device had simultaneous access to the one
wire, typically connecting a remote junction box to a
central switching location, only one device at a time
I could use the wire to send messages to other devices.
; 20 When the device relinquished the line, another device
could then use the line to send messages. Since only one
device could use the line to send at any one time, the
number ox messages which could be sent would be quite
low. Thus, the data rate of the systems was low. Some
protocol was established for determining which device had
the use of the line at any time. Considering the relative
simplicity of such a system and the low data rates, and
the fact that the system was most likely under the
jurisdiction of one entity, such as the telegraph company,
the protocol could be as simple as listening to determine
whether the line was in use. As the volume of signal
tragic on the line bacame greater and the need or
immediate availability of communication paths increased,
alternative systems came into use.
Most present day switching systems employ star
architectures or distributed star architectures. In the
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star architecture, a large central switch is employed and
all stations are wired to a central location. At the
central location, a communications line from one device
could be connected to the communications line from anot'ner
device to which communication was to be established. This
could be done manually as with an operator at switchboard,
electromechanically such as in a complex telephone
crossbar system, or under computer control as is done in
modern telephone networks.
Although the method of running communications lines
from each user to a central location has many advantages,
it has the distinct disadvantage of requiring a
communications line from each device to a central
location. Thus, although two devices might be relatively
close to each other compared to the distance to the
central location, communications between the two devices
would be routed through the central location. In a large,
widespread network this would require substantial
expenditures for the communications lines that would
remain idle much of the timeO If another device has to be
added to an existing system a new dedicated communications
line would have to be added to connect the device to the
central location. Moreover, since the entire system was
dependent upon proper operation ox a central switch, the
survivability of the system was low. It is obvious that
such a method of interconnecting communications devices
has substantial economical and practlcal drawbacks.
A distributed star still employs a large central
switch but reduces the wiring requirements to that switch
by multiplexing many conversations, or circuit paths, onto
the wiring between the central switch and peripheral
switching units. The advantages of distributed switching
include improved reliability, improved availability,
improved survivability, and reduced installation in wiring
costs. However, a fundamental obstacle has prevented the
wldespread adoption of distributed switching, that
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obstacle being connectivity or allocation of circuit paths
among the various nodes of the network. The connectivity
between peripheral switching units remains limited to the
number of circuit paths or "party lines" carried on the
multiplexed wiring between the central switch and the
peripheral switching units (PSU). The users in a given
area would have to wait until the party line to the
central switching location was not in use before
initiating a message. As was frequently the case, a large
number of users could want to send more messages than such
a system could handle in a given time frame. Connectivity
is not a problem when the switch is non-blocked, i.e.
there is a circuit path for every station in the system,
such as in the earlier star architecture. However, the
cost of a non-blocked system is excessive and some level
of blocking is introduced in order to reduce the cost per
station of the system. The challenge is therefore to
provide a communications system that employs some degree
of blocking to avoid costly redundancies, but does so in a
widely distributed manner to avoid bottlenecks in the
signal traffic.
In the distributed star, blocking may be introduced in
the PSU. Consequently, all stations on the PSU may
contend for the number of circuits that exist between the
~5 PSU and the central switch. Typically the number of calls
initiated per unit time varies from one PSU to another.
To obtain a desired grade of service, i.e. the likelihood
that a circuit path will be available for a call, it is
thus necessary to balance the load on the PSU's by
physically changing the number of telephones wired
thereto. Because of the dynamic nature of modern
businesses, the offered load to each PSU changes with time
necessitating an ongoing process of traffic analysis
followed by physically disconnecting and reconnecting
telephones from one PSU to another. That process is
costly, time consuming and introduces reliability
problems.
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When the number of circuits is small a significantly
larger ratio of circuits to telephone sets (telesets) i3
required to ensure a fixed grade of service. For example,
a 30% grade of service is insured by providing three
circuits to service ten telsets, but requires two circuits
to service four telsets. Therefore, in order to minimize
the number of dedieated circuits, a more desirable system
would allow the number of circuits per PSU to vary
dynamieally in accordance with the number of assoeiated
telesets. Ideally, the system would allow for the offered
load from a loeal station to contend for all the circuits
of the eentral switch rather than to contend for the small
and fixed number of circuits at an individual PCU.
One approach to the problem developed in the prior art
ts is the use ox time division multiplexing of digital
data. In a system which uses time division multiplexing a
communications line is not provided from each device to a
eentral loeation. Instead, each device is connected to
other devices relatively close to it. Thus, there are
eonsiderable savings in the number of communications lines
needed to intereonnect the devices in a network. All the
devices in a communications network may be connected in a
ring, chain or the like, with each device connected to two
other devices, or to one other device in the case of a
device at the end of a chain connection. Although it
might appear that such a device would then only be able to
; communicate with a device to which it has a direct
eonnection, each device ean communicate with all other
devices conneeted to the network. The network ring or
chain is eontinuous, with each device either tapping the
ring or ehain, or forming a part of the ring or ehain.
Although the devices are physieally eonneeted to the same
line at any one time9 and do not transmit data at the same
time, the devices may be time multiplexed and need not
-35 have to wait until other devices complete their messages
before sending their own messages. Communication between
devices can typically be accommodated using only a portion
of the time available in each cyclical message frame,
thereby allowing the ring to communicate numerous messages
within a p,iven period. Moreover, the message pool
includes all the resources of the network signal stream.
Thus, blocking is provided on the most distributed basis
possible.
When time division multiplexing is employed the
communications line is not assigned solely to one device
until the completion of a message. Instead, the line is
assigned to each device for a relatively short period of
time, typically referred to as a time slot. Other devices
in the comm~mications network are likewise assigned to
time slots. The time slots occur periodically on the
communications line, and are repeated at a frequency such
that the device can send or receive data continuously at
its normal data rate. A message frame is comprised of all
the time slots available for devices.
In an exemplary system utilizing time division
multiplexing, the communications devices might operate at
a data rate of 1000 bits per second (bps). A
communication line operating at 1 oo,noo bps would be able
to transfer messages to or from this device and 99 similar
devices in a message frame which has a 1000 hertz
repetition rate. The data from each device would be
assigned to each of the 100 one-bit time slots in the
message frame. Other configurations could assign the time
slots for devices in multiple-bit groups.
In either the contemporary centralized network or the
3~ contemporary ring network, however, devices can only be
added to the system if there are time slots available in a
message frame. Therefore, it would be difficult, if not
impossible, to add the 1~1st device to the exemplary
system if the available time slots are permanently
assigned to other devices. In many communications
applications the devices present in the system probably
would not all be communicating at the same time. Thus,
there could be a substantial number of the time slots idle
at any given time. However, a typical prior art
communications system would not have the flexibility to
reassign the idle time slots to-additional devices to take
greater advantage of the available time slots. Although
increasing the number of time slots would accommodate
extra devices, if possible to do so, the incremental
increase in the number of time slots might be large
compared to the number of devices to be accommodated, and
therefore could result in a large number of unused time
slots.
Another problem with the typical prior art system
utilizing time division multiplexing is that devices
operating at different data rates cannot be accommodated.
Although the time slot allocations in a message frame
might be adequate for most devices in a system, there is
often a need for other devices operating at higher or
lower data rates. For example, a system might consist
primarily of digitized telephones operating at 64,000
bps. If a typical network is configured to accommodate
the telephones ? it might not be able to accommodate the
communications to and from a terminal device operating at
other data rates, e.g. 19,200 bps. Furthermore, a device
might be such that it operates at different rates when
communicating with different devices. Thus, a time slot
assignment sufficient to accommodate a 19,200 bps data
rate would be partially unused it the device were to
operate at g600 bps or a lower data rate. Similarly, a
time slot assigned to a terminal device operating at 9600
bps would not be able to accommodate the same device
operating at 19,200 bps.
voice signal can be transferred without any
appreciable loss of quality as a stream of 64,000 data
bits per second (64,000 bps). The voice signal is sampled
at periodic intervals by the sending device; the samples
2~
are converted to a digital format; the digital data is
transferred to the receiving device as a stream of data
bits; and the digital data is converted to a voice signal
by the receiving device.
In comparison to a voice signal, the transmission of
character information between a cornputer and a high-speed
video terminal can require data transmission rates in the
range of 19,200 bps. On the other hand, a typical
teletypewriter terminal might only require data at a`rate
of 110 to 300 bps to operate at full capacity.
Typically a data communications network, therefore,
needs to be capable of handling data rates from 110 bps to
19,200 bps, and under some circumstances up to 1,000,000
bps or Gore.
As can be readily seen from the foregoing, the
implementation of time division multiplexing in the prior
art accomplished a significant savings in physical
resources in a typical communications network. However,
the prior art systems have serious li1Ditations with regard
2~ to flexibility in light ox the ever increasing demands on
data communications systems, both with regard to the
increases in the quantity of devices to be connected to a
system and with regard to widespread variations in the
communications rates used by those devices.
In practice, a user at a given location will have both
voice and data communications equipment which may be
alternately, or simultaneously used. Preferably, the
communications equipment connecting the local station to
the network should be able to accept either or both voice
and data inforrnation, format information for communication
to the network, and synchronize the data rates of that
inEormativn with the network data rate. The equipment
should also have the ability to dynamically modify the
network bit space allocation assignable to the particular
communications device in accordance with the operating
requirements oE that device. The equipment should
By
preferably be able to effect those functions without t'ne
need for extensive control equipment at the local
equipment, and without the need for connecting the local
equipment to dedicated control lines. The system should
have the ability to communicate control information to and
from the network controller using the same lines used to
communicate voice and data information, thus simplifying
the connection requirements for individual communications
devices.
In contemporary communications systems interconnection
of devices that operate with different comm~mications
formats and information rates is accomplished through the
use of interlace devices that perform a specialized
function and operate with only one or, a most, a small
number of terminal devices. Generally, such interface
devices are hardwired with regard to formats and rates, or
are manually switchable. Such devices do not lend
themselves to control by a central network controller and
do not provide the requisite flexibility in the rapidly
expanding communications field.
Summary of the Invention
In accordance with the present invention a
communication switching system is provided for
independently steerable data and controlled channels
between a station device and a circuit using a
shared time multiplexed signal path, the system com-
prising a digital communication device operative to
generate and receIve data information, device further
being operative to selectivèly request access to the
facilities of a packet channel circuit; a controller
connected to the device and operative to enable a
path to the packet channel circuit in response to the
packet channel access request; station ports connected
to the station device and to the circuit; micro-
telephone controller connected to the stationports, device and controller, the ~icrotelephone
, .-
Lg
controller being operative to communicate databetween the device and the station ports and to
communicate control i`nformation between controller
and the station ports, the controller being
further operative to formulate the control
information and the data informati`on in a time multi-
plexed signal stream; and cïrcuit adapted to
receive the time multiplexed signal stream and
to direct the control informatïon to a packet channel
l circuit and to dire-ct the data information to a data
network.
The invention therefore permits a local station
to accommodate independently steerable data communications
and control communications. The user may, for example,
access the node processor on the control communications
line to view selected information at a station display
device while, at the same time, effecting data
communications communicating data information with a
distant station. The inventïon therefore provides
the user with access to the facilities of local or distant
processors at the same time as enabling data
communications with other devices. As described below,
the data communications channel enables interconnection
with devices operating at a variety of speeds and in a
variety of modes.
The communications switching system provided enables
the communication of data (machine data, voice data,
and/or image data) and control in~orma~ion to and from a
statlon device in a combined serial signal stream.
The switching system comprising a plurality of switches
each switch having a station-to-highway section
and a highway-to-statïon section. Each section
i5 disposed in electrical communication with a
station port and with a plurality of node information
highways. Each section includes independently
and dynamically configurable information channel
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circuits adapted to communicate data information
between the station ports and a selected node
information highway. Each section further includes packet
channel circuits in electrical communication with the
station ports and with a node processor. The packet
channel circuits being operative to derive control
information from a signal stream from a station
port, and to combine control information with data
l information to form a serial signal stream for
communication to a station port.
The switching system may accommodate station devices
different information rates on the node information
highways and at the station ports.
These sections each may comprise a plurality of
channels, each of which may include an independently
configurable control register that facilitates a
communications path between the information highway
and a station port,
Each channel may include an independently configurable
control register that may contain
information representative of the information highway from
which the information is transferred, the time relative
the time relative to the beginning of a message frame at
which the information is transferred and the bandwidth of
information transferred between the information highways
and the station ports. The control
registers may be dynamically reconfigured in response to
control signals from node processors
The communication switching system may further
comprise a microtelephone controller connected to a
digital communications device and in electrical
communication with the station ports. The
microtelephone controller is adaptable to interface
digital information between the station ports
and the device. The microtelephone controller
8~
comprises a system interface onerative to
demultiplex a serial signal stream from the station port
into control and data ;nformation. The system
interface being further operative to multiplex
control and data information into a serial signal stream
for communication to the station port 286. The
microtelephone controller further ïncludes clear
channel serial rate conversion logïc for translating
the information rate of data from the system interface
into a rate compatible with the local device. The
rate conversion logic also being operative to
translating the rate of data received from local device
to a rate compatible wi`th the operation of system
interface. The microtelephone controller further
includes asynchronous, synchronous, and terminal
rate logic operative to format the data from the
local device into a message segment for transmission
to the system interface, and for deriving data from a
message segment received from the system interface.
The microtelephone controller also includes packet
channel logic for communicating control information
between the system interface and a microprocessor
interface. The packet channel logic ïs also
operatïve to generate monitoring signals responslve
to the content of the control information.
The microprocessor controller may facilitate
voice and/or data communications. When the microtelephone
controller is connected to an audio device, it is
provided with a voice interface for communicating
voice information between the audio device and the
system interface.
The system interface Jay ïnclude the system
interface multiplexer operatiYe to combine control
signals from an external proce-sor, voice signals
from an external audïo devïce and data signals from
an external data device and to transmït a combined
~''`~ .
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signal in a serial signal stream to the station port.
The system interface may further include a
decoder adapted to receive a serial signal stream
from the station port and to separate the control
signal portion from the received signal stream.
The data portion of the message segments
communicated to and from the station ports may
include a variable number of valid data bits. The
number of valid data bits may be determined in
response to the data rate ox the device.
Brief Description of the Drawings
The foregoing objects, features, and advantages as
well as others of the invention will be more fully
comprehended from the following description and
accompanying drawings in which:
Figure l(a) is an illustration of a prior art star
architecture PBX.
Figure 1(b) is an illustration of a prior art
distributed star PBX.
Figure 2(a) is a high level illustration of wide area
networking in accordance with the present invention.
Figure 2(b) is a high level illustration of a
representative PBX ring network including a baseband bus
local area network.
Figure 2(c) is a high level illustration of a
representative PBX ring network including a dual ring
transmission scheme.
Figure 3(a) is a wiring diagram of a switching node.
Figure 3(b) is an illustration of an exemplary signal
frame,
Figure 4 is a block diagram of the network interfacing
circuitry.
Figure 5 is a block diagram of the data path from a
digital telephone through a node to the network loop.
Figure 6(a) is a block diagram of the internal
configuration of a node with associated modules.
.,
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Figure 6(b) is an illustration of the switching within
a ring interface and control unit (RICU).
Figure 7 is a a block diagram of an RF modem.
Figure 8(a) is a block diagram of the data steering
module that controls switching of data between the network
loop and the node internal TDM highways;
Figure 8(b) is a flow chart of the functions of the
Network Timeslot Manager (NT~);
Figure 8(c) is a flow chart of the functions of the
Network Timeslot Servers (NTS);
Figure 9 is a block diagram of the internal
configuration of a network interface module (NIM).
Figure 10 is a block diagram of the internal
configuration of a station interface module (SIM).
Figure 11 is a wiring diagram of a quad Per Line
Switch (QPLS) element showing the external connections.
Figure 12 is a block diagram of the connections
between several of the principal portions of the QPLS.
Figure 13(a) shows data flow from the information
highways to the station port.
Figure 13(b) shows data flow from the station port to
the information highways.
Figure 13(c) shows a detailed block diagram of an
input shift register in Figure 13(a).
2~ Figure 14 is a block diagram of the control interface
logic.
Figure 15 is a block diagram showing the
interconnections between four exemplary PLS's,
Figure 16 is a block diagram of the optional
diagnostic channel.
Figure 17 is a timing diagram exemplifying the
relationship between the information highway data rates.
Figure 18 is a timing diagram exemplifying the data
transfer formats to a station device in the local mode.
Figure 19 is a timing diagram exemplifying the data
transfer formats to a station device in the remote mode.
-14-
Figure 20 is a timing diagram illustrating an
exemplary data encoding format applied to nonreturn-to-
zero (NRZ) data.
Figure 21 is a reference table for the signals on the
pins of the QPLS.
Figure 22 is a detailed logic diagram of the QPLS
Information Channel Out (ICO).
Figure 23 is a logic diagram of the QPLS Information
Channel In (ICI).
10Figure 24 is a logic diagram of the QPLS Packet
Channel Out (PCO).
Figure 25 is a logic diagram of the QPLS Packet
Channel In (PCI).
Figure 26 is a logic diagram of the QPLS CRC Circuit
(CCITT).
Figure 27 is a logic diagram of the QPLS Output Line
Control (OLC).
Figure 28 is a logic diagram of the QPLS Input Line
Control (ILC).
Figure 29 is a logic diagram of the QPLS Line Clock
Rate Registers (CRGS).
Figure 30 is a logic diagram of the QPLS Internal
Control, Timing, and Buffers.
Figure 31 is a logic diagram of the QPLS Mode
Register/Status.
Figure 32 is a logic diagram of the QPLS Biphase Mark
Encoder/ Decoder (BME/BMD).
Figure 33 is a logic diagram of the QPLS Input Message
Control (IMC3.
30Figure 34 is a logic diagram of the QPLS Input/Outpu,
Decode/ Control.
Figures 35-41 are logic diagrams of the QPLS Reference
Timing.
Figure 42 is a wiring diagram of one implementation of
the microtelephone controller (MTC) showing the external
connections.
Figure 43 is a high level block diagram showing a
typical implementation of the MTC in a digital telephone
station.
Figure 44 is a functional block diagram of the
internal configuration of the MTC.
Figure 44A is a functional block diagram of the MTC
and associated teleterminal devices.
Figure 45 is a timing diagram exemplifying the
relationship between the data format received by the MTC
and the internally generated synchronization signals.
- Figure 46 is a timing diagram exemplifying the
synchronization pattern of the data received by the MTC in
the absence of any information data.
Figure 47 is a timing diagram exemplifying the
relationship between the data from the system node to the
voice channel CODEC.
Figure 48 is a timing diagram exemplifying the
relationship between the data received by the MTC from the
system node and the internally generated PBX data formats.
20Figure 49 is a timing diagram exemplifying the
relationship between the lower rate PBX data formats and
the 64 kHz PBX data formats.
Figure 50 is a timing diagram exemplifying the
resynchronization of terminal data when a missing stop bit
or an extra stop bit is received by the MTC.
Figures 51(a), (b), (c), (d) and (e) are more detailed
block diagrams of the functional units of the MTC
generally illustrated at Figure 44.
Figure 52 is a timing diagram showing the relationship
between biphase mark encoded data and NRZ data.
Figure 53 is a logic diagram of the MTC system
interface.
Figure 54 is a logic diagram of the MTC packet channel
receive logic.
35Figure 55 is a logic diagram of the MTC CRC checking
logic.
-16-
Figure 56 is a logic diagram of the MTC CRC timing
logic.
Figure 57 is a logic diagram of the MTC CRC generating
logic.
Figure 58 is a logic diagram of the MTC decoding
loglc .
Figure 59 illustrates a portion of the MTC clear
channel rate conversion logic.
Figure 60 illustrates another portion oi the MTC clear
channel rate conversion logic.
Figure 61 illustrates another portion of the MTC clear
channel rate conversion logic.
Figure 62 illustrates another portion ox the MTC clear
channel asynchronous, synchronous and terminal rate logic.
Figure 63 is a logic diagram of the MTC decoding
circuit.
Figure 64 is a logic diagram of the MTC output clock
signals.
Figure 65 is a block diagram of a video interface
module (VIM).
Detailed Description of the Preerred Embodiment
Prior Art PBX Systems
Figure 1(a) illustrates a representative star
architecture PB~ such as one currently produced by Lexar
Corporation. In operation, communications between
individual stations t1 are effected via dedicated
communications lines interconnected on a point-to-point
basis at central switch 13. When a user at one station
desires to communicate with another, he takes the receiver
of hook and dials a number on the local station. That
action causes the signal to be sent to the central switch
13 which connects a communication path with the station
being called. The control switch 13 typically
incorporates a time multiplexed switching network that
includes time slots dedicated to the switching
requirements oi individual stations. The central switch
-17-
13 is a time slot interchange that typically provides tr,70
time slots for each station connected to the central
switch. In this manner, the system operates in a non-
blocking mode, i.e. a communications path is always
s available, providing total connectivity for all peripheral
voice and data devices 11. In some applications the non-
blocking nature of such products can be advantageous
because no traffic engineering is required to obtain an
adequate level of performance. However, such products
suffer from a significant lack of flexibility because the
total system size is limited, absolutely, to the traffic
capacity of the central switch.
Other contemporary systems, such as the Model SX-20~0
system produced by Mitel Corporation, have addressed the
expansion requirement by adding an expansion switching
module that effectively doubles the capacity of the time
slot interchange. Such systems, however, still require
dedicated communications lines between the local stations
1l and a central switch. Moreover, a number of connecting
lines between the central switch and the expansion modules
are limited. Thus, the capacity of the switch remains
limited despite the addition of expansion switching
modules.
The distributed star POX illustrated in Figure 1(b) is
representative of commercial systems currently available,
such as the~SL-l system produced by Northern Telecom,
Inc. The primary switching element is time slot
interchange (TSI) l5, which serves as the central switch
and is connected to each of the peripheral switching units
(PSU) 17 by means of communication paths 19, which
typically operate at 2.048 Mbps and carry 30 channels of
PCM voice traffic. Individual stations l1 are separately
connected to PSU's. In practice, a user at local station
l1, desiring to communicate with another station, will
take the receiver off hook and dials a number. That
action causes a signal to be sent to a PSU l7 and then to
i *Trademark
a
-18-
central switch 15 which connects the user to another
station 11 via communication some path 19 and some PSU
17.
All communications between a station connected to one
PSU and a station connected to another PSU must proceed
via the communication paths through the TSI 15 which
performs all switching functions. Moreover, in many
cases, even signals between stations connected to a common
PSU must also be corducted via the communication paths to
the TSI, where the signal is then channeled back to the
originating PS~T. Such a system is inherently inefficient
because it uses system capacity for intra-PSU traffic.
Also, data transmission in such systems typically uses a
full 64 kbps time slot even if the data speed is, for
example, only 4800 bps. Moreover, those tire slots remain
dedicated to a particular connection, whether in use or
not, and are unavailable for other connections.
In some other contemporary systems the PSU serves as
an intercom swltch to channel local traffic without the
need for communicating the local signal to the TSI.
However, such systems retain the inherent fixed level of
connectivity associated with the branch connecting to the
control switch and also remain statistically inefficient
due to the poorer utilization of the total pool of time
slots.
Overview of Dynamic Network Switching
As detailed below the system provided in the present
invention allows dynamic allocation of the network signal
stream, thereby providing dynamic connectivity as well as
variable bandwidth circuits.
Figure 2(a) is an illustration of wide area networking
in accordance with the present invention. This igure is
intended to illustrate potential application of the
present invention for interconnecting various traffic
subsystems called pools, located substantial distances
apart. Network connections between pools may be
- l 9 -
accomplished by means of dedicated or switched land line
connections 34, by light or microwave links 36, by
satellite links 38, or by other such connections. Large
ring based systems can be constructed using two or more
5 levels of pools as illustrated in the Figure and described
below.
The general topology of the presently preferred
embodiment of the invention is a hierarchy of broadband
rings. It should however, be understood that in its
broader aspects the present invention may function in
conjunction with network signal streams that are not
communicated via a ring configuration. The lowest level
of the hierarchy (Level O) consists of a single switching
node N1, connected to ring 18, and to its local station
devices 11, which may be terminals, teleterminals, file
sub-systems, etc. A switching node is a fundamental
portion of the present invention which permits
communication between the network signal stream and one or
more lacal devices. As described in more detail below,
2U the node selectively extracts information from and inserts
information to the network signal stream for communication
to devices connected to other nodes. The node is
dynamically configurable in order to make use of available
bandwidth in the network signal stream. Network control
information to effect the dynamic bandwidth allocation may
be transmitted along with the network signal stream or
independently communicated between the nodes.
Independent of whether the nodes receive network
control in~orma~ion with the network packet switched data
or on a separate line, they are constructed to integrate
control information (packet data) with the voice and clear
channel data (circuit switched data) for communications
with the local devices. Thus, the need for elaborate
control interfaces between the local devices and the node
are eliminated. Moreover, a plurality of data
communications equipment, integrated at the local station,
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; may collectively communicate the node via the same simple
wiring arrangement. As also described below, multiple
local devices may be connected to a single node.
The next level of the hierarchy above the switching
s node (Level 1), e.g. ring l consists of a broadband ring
connecting two or more level 0 rings, e.g. N1, N2 and
associated devices 11, in a circular arrangement termed an
"orbit". Level 2 of the hierarchy consists of another
broadband ring, e.g. ring 14 or 16, connecting two or more
orbits in a circular arrangement termed a "system". The
method of connecting orbits is by means of special nodes,
; e.g. 42,44,~6 which interface to both the orbit ring and
the system ring and provide cross-over switching between
the two. These special nodes are called "Bridge Nodes"
and are constructed from the same basic modules as the
switching nodes. Level 3 of the hierarchy is a ring
connecting two or more systems, e.g. via the illustrated
satellite, termed a "galaxy". Because a system is capable
of serving in excess of 30-60,000 installed devices,
discussion of the properties of Level 3 and 4 ("cosmos",
not shown) networks will be limited to the obvious
generalizations of the lower order formations.
Each level of the hierarchy is capable of functioning
as an autonomous, stand-alone switching system because
management of resources for a given level is always
handled within that level. Thus, for example, should ring
14 become inoperativej ring 18 may continue to operate for
communications between any of the nodes on that ring.
This property contributes significantly to the
survivability aspects of the invention especially with
respect to multiple failure modes. Furthermore, this
model for the management strategy is repeated at each
level of the hierarchy in a symmetric fashion, which
contributes to the ease of modeling and ultimately of
- 35 implementation. Connectivity between the rings is
established by assemblies called highway-to-highway
interface nodules (HIM' 5), described below.
-21-
Figure I shows an exemplary level 1 rlng system of
switching nodes 21 employing the services of a baseband
bus Local Area Network (LAN) for the purpose of network
control and internodal communications. Interface between
the nodes 21 and the circuit switched ring path 25 is
effected by Ring Interface and Control Units (RICU) 27.
The embodiment illustrated incorporates an ethernet LAN
23. The use of a Lo to establish a communication path
between nodes employs protocol that permits both
-transmitting and receiving nodes to coordinate access to
the network signal stream. Though the control functions,
e.g. channel allocation, performed by the ethernet are in
some ways peculiar to the particular ring construction
employed, there are basic similarities to the channel
allocation functions performed in contemporary control
devices such as the~D-3 Channel Bank, produced by American
Telephone and Telegraph. However, the present invention
expands upon existing capacity for time multiplexing
mutual access to the network signal stream by permitting
dynamic allocation of the size and location of the access
channels.
Because the software is typically layered, e.g. to
allow the nodes to autonomously perform certain intranode
and internode functions without involving the network
controller, the physical and link level protocols
effecting lower level functions can be changed without
afecting higher level software or system functioning.
Therefore, the means of effecting high level management
and supervision of the control unctions delegated to the
node may be modified without substantially altering the
nodes' autonomous functions. In such a manner the Lo 23,
which communicates control signals between nodes, may be
readily replaced by a token ring configuration. In the
token ring configuration control information may be
integrated into the Detwork signal stream and decoded at
the individual node. The token ring cofiguration may
*Trademark
-22-
employ a standard protocal such as the proposed IEEE 802
standard to facilitate communication of control signals
between the nodes. The management of the network control
functions in the presently preferred embodiment is
described in more detail below.
Figure 2(c) illustrates another level ring system
using a dual ring transmission scheme. Two identical ring
paths 25(a) and 25(b) are illustrated which may each carry
both a token ring component that conveys control
13 information (i.e. packet data), and a time division
multiplexed (TDM) ring that conveys the network circuit
switched signal stream (i.e. voice and data signals).
Alternatively, one ring may be dedicated to control
information and the other to circuit switched data. In
one embodiment one ring (called the forward ring) may
carry circuit switched data traffic in the TDM ring
portion, and network management and other control signals
in the token ring portion. The other ring (called the
backward ring) may carry digitized video channels in the
TDM ring portion and control information in the token ring
portion.
Consistent with Figure 2(b), the token ring component
of Figure 2(c) may be replaced with an ethernet controller
including Ethernet transceiver 31 connecting the Lo bus
23 to the node (shown in the dashed lines).
Typically, redundant dual-ring systems will include at
; least two nodes equipped with disc memory subsystems 29,
as indicated in the figure. The disc memories typically
serve to store the programing information transferred to
the various processor modules within the node upon
start-up. Disc systems may be used for storage of textual
data for electronic messaging applications as well as to
provide two identical redundant copies of the system data
base and operational software. A small computer standard
interface (SCSI) bus 58 provides an interface to a disc
storage and tape storage module such as disc 29
-~3-
illustrated in Figure 2(c). While the presently
preferred embodiment of the invention employs
conventional cable TV coaxial cable for the network loop
paths, other point-to-point transmission media of
S sufficient capacity could equally well be used, e.g. iber
optics or a parallel buys.
igure 3(a) illustrates a high level external wiring
diagram of a switching node illustrating the communication
of various signals to node 21 for switching in proper
sequence. Figure 3(a) shows in isolation the node 21
illustrated as part of a larger system in Figures 2(b) and
2(c). As also shown in Figure 2(c), inputs to the
switching node may typically include trunk lines 54 from
the public telephone company for service to network analog
teleset lines, and peripheral highways 56 to digital
telephone stations. The node serves to interface such
traffic and the network ring 25 via the RICU 27.
An ethernet transceiver 31, if utilized, communicates
signals between the node and the LAN 23 as shown in
Figure 2(c). As is more fully described below, in a
multinode system the LAN is used to carry messages between
nodes for the purpose of establishing time slot
assignments for communicating between particular nodes and
for maintaining overall network control and status. In
practice, the eithernet transceiver 31 or the RICU 27 may
be located on the node for ease of manufacture.
Overview of Network Timing
To operate as a PBX or voice switching system the data
is transmitted around the network ring at some
predetermined rate, e.g. once every 125 microseconds.
That transit rate is preferably set by the master timing
node for the entire ring. The need for a master timing
node arises from the fact that data is typically
transmitted around the network ring 25 in such less than
125 microseconds. Assuming the ring is a few thousand
meters in circumference, it takes only a few microseconds
-2~-
for data to completely transit the ring and arrive back at
the master node. Thus, unless one node is able to buffer
the incoming signal stream and transmit at the
predetermined rate, the nodes will receive the data at
sore uncertain rate, which would be a function of the
length of the combined network frame. All nodes may have
the circuitry needed to function as a loop master, but
only one node assumes that role during normal operation.
When the system is initialized one of the nodes will
provide frame synchronization for the network ring. Ring
mastership may be determined using any of a number of well
known techniques. The priority for each node may be based
upon factors such as the number of interconnected local
stations, the characteristics of those stations, or the
address of each node. A score indicative of those
priorities may be determined by each node and transmitted
in response to a broadcast signal generated at start-up.
upon failure of a loop master another node may assume that
role.
As is more clearly illustrated at Figure 4, which
shows the network interfacing circuitry, if the node is
the master node that clocks the signal around the network
ring, a switch 39 in the receive circuit is in the open
position enabling the received sig-nal to be stored in a
buffer 35 until the next master frame sync signal is
received.
In order to adjust the transit time to a full frame
(125 microseconds), buffer 35 acts as an elastic store.
Data is loaded into buffer 35, accumulated for a period of
time (i.e., 125 microseconds minus the ring delay for the
received data), and then unloaded from the buffer when the
next frame synchronization signal is generated. The
transit time of data to the slaved -nodes around the ring
is thereby adjusted to be one complete frame. The token
ring of the network signal stream is separated by
demultiplexer 53 and communicated to token ring receive
-25-
logic 37~ Accordingly, on the the TDM field need be
communicated to the buffer 35,
The relationship between the information rate on the
ring and the data rate on the internal highways t which
communicate the demultiplexed network signal stream, is a
function of the number and speed of the TDM highways (i.e.
node transmit and node receive highways) 66,68 within the
node and the speed of the token ring 25 (equivalent to an
integer multlple of TDM highways). where the
representative node contains 8 TDM highways and a token
ring equivalent to 4 TDM highways, the ring data rate is
12 X the data rate of the TDM highways. The data rate for
; the presently preferred embodiment of the ring 25 is
49.152 Mbps for 4.096 MHz operation on the internal
highways 66,68. If the internal highways operate at 8.192
MHz, the data rate on the ring 25 is doubled. However, it
is understood that the broader aspects of the present
invention are independent of the particular transmission
rate. Operation of the node highways 66,68 at different
data rates is described in more detail below in connection
with Figure 17.
One frame time o-f a 4.096 MHz TDM highway, i.e. 125
microseconds, can be divided into 64 8-bit bytes, or 512
bit time slots, as shown at Figure 3(b). In order to
increase the traffic capacity of the nodes and of the
network, 8 TDM highways are provided in the presently
preferred embodiment of the node, thus producing 512 8-bit
time slots per frame, or 4,096 bit level time slots per
frame.
Figure 3(b) illustrates a high level view of a typical
network ring frame format in a token ring
impLementation. In each 125 microsecond frame, 512 bytes
; of information are transmitted. As described in more
detail, below, each byte is typically 12 bits and
comprised of two fields, one of 8 bits, and one of 4
bits. The 8-bit field carries TDM data for the circuit
-26~
switched paths. The 4-bit field is communicated to the
token ring LAN. Bytes 0 and 1 in the TDM field may be
used for the frame synchronization pattern. A
conventional correlation type circuit is used to determine
frame synchronization from the bit pattern carried in
these two bytes, e.g. indicating the frame number. Such
conventional synchronization procedures are well known in
the art and are described in numerous publications such as
J. Bellamy, Digital Telephony, (J. Wiley and Sons, U.S.A.
1982). It is understood that various types of frame
synchronization techniques may be implemented within the
teachings of the present invention.
Once frame synchronization is established the token
field is effectively an unframed continuous bit stream
whose protocol typically follows standards adopted or
proposed by the United States IEEE 802 Committee. Other
token ring protocols may be used equally well.
As the case with ring timing, one node is typically
designated master node for ring management or control
functions. That node is typically called the network
manager and, for practical purposes, may be the same node
that serves as the master timing node. As is also the
case with frame timing, each node typically has the
resources to serve as ring master, and mastership may be
2~ determined in accordance with the same priorities for
determining timing mastership.
In the presently preferred embodiment, messages to the
ring master, i.e. the network manager, may be transmitted
as "generic" messages, which are neither messages directed
to a particular address nor broadcasts processed by each
node. Only the node performing the network message
function operates to respond to the message by, for
example, allocating ring bandwidth to the requesting
device to facilitate communication between nodes. Those
network control functions are described in more detail
below.
8~9
-27-
Overview of Local Timing
Virtually all PBX telephone equipment operates at some
multiple of 8,000 samples per second which rate can be
represented by one cycle, or frame, occurs every 125
microseconds. Accordingly, for telephone applications the
node TDM highways should operate at integer multiples of
8,000 samples per second to accommodate conventional
digital PBX's. The majority of data communication
equipment operates at speeds which are multiples of 600
bps. Because the present invention is intended to support
both voice and data communications, it is necessary to
find a local clocking scheme which supports both multiples
of 8000 Hz and multiples of 600 Hz. Simultaneous voice
and data communications may be supported by choosing a
clock rate, for transmission between the node and
interconnected telephone equipment, that is a common
multiplier of both 600 and 8,000, such as 192 kbps. It is
therefore possible to simultaneously provide sampling
clocks for the majority of local communications
requirements by providing a signal frame including two
independent channels of 8-bit voice or data communications
for communication to the local station (i.e. voice, data,
and local control information), and 8 blts of control
information. Each 8-bit data channels provide an
aggregate throughput of 64 kbps per channel. As shown in
the inset at Figure 5 the 192 kbps rate utilized in the
presently preferred embodiment is apportioned into several
sections; a 64 kbps data section, a 64 kbps voice or data
section, a 32 kbps overhead section, and a 32 KB signaling
section. Because individual devices operate at different
data rates, the number of valid data bits that may be
communicated during the 64 kbps section will vary. The
system node will therefore communicate a variable number
of valid data bits and fill bits during the 64 kbps
section. The particular number of fill bits and data bits
will depend upon the characteristic operation of the
particular device.
~z~
-28-
Overview of Data Flow Through The Node
Figure 4 illustrates on a broad level t'ne flow of
network ring signal traffic through the node. Details of
the internal configuration of the module.s used to direct
the flow of traffic through the node are set forth later
in the specifications following the operational
description. In Figure 4 the serial bit stream from the
network ring enters a receiver and demultiplexer 53, whlch
forms a portion ox the RF modem described below at
Figure 7. In demultiplexer 531 the bit stream is
demultiplexed from frames of 512, 12-bit bytes into byte
portions onto an 8-bit bus and a 4-bit bus. The 4-bit bus
is processed by a token logic 37. Each bit of the 8-bit
TDM portion of the receive signal is communicated to a
dedlcated network receive highway 62 to a dedicated data
steering logic element 41. Similarly, each node transmit
highway 64 is dedicated to one of eight bits of the TDM
data stream. Each data steering logic element 41 is
connected to each of the eight node receive highways 66
and each of the eight node transmit highways 68. The data
steering logic 41 can selectively communicate one or more
bits from a network receive highway 62 to a node receîve
highway 66. Similarly each data steering logic 41 can
selectively communicate one or more bits from a node
transmit highway 68 to a network transmit highway 64.
Each data steering logic 41 can steer data bits
independent of the other elements of data steering
logic 41. In the presently preferred embodiment groups of
bits sequentially received on the same network receive
highway (i.e. occupying the same position in a plurality
of successive or periodic bytes received at the node) may
be transferred by the data steering logic 41 onto a node
receive highway 66 for communication to an individual
station device 45 via a per line switch 43, which is
typically connected to each of the node highways and to
one local device. The mapping of communication paths for
8~
-29-
each bit is described in more detail below. If the
network signal portion is not intended for a device
connected to the particular node, the data steering logic
will simply pass the portion onto transmit and multiplexer
33 where the network serial bit stream is recomposed.
Alternatively, the data steering logic may both
communicate the portion to a local device and to the
transmit and multiplexer 33.
The data steering module 50 also illustrated at Figure
8(a), generally includes a FIFO buffer 35, a switch 39 and
data steering logic 41. As previously mentioned, in a
multinode network only one node need act as a master for
TDM timing purposes. The master node employs the FIF0
buffer 35 to adjust the transit time of TDM data around
the ring to exactly one frame time. Slave nodes, on the
other hand, bypass the FIF0 buffer by closing the switch
39. Whether the node is a master or a slave, the received
data is passed into the data steering logic 41. The data
steering logic 41 also includes a bit map, see Figure
8(a), which depicts and controls the flow of data, bit by
bit, highway by highway, from the network receive highways
62 to the node receive highways 66, and from the node
transmit highways 68 to the network transmit highways
64. The contents of the bit map are established by a CPU
59 (see Figure 5) as implemented under the control of
messages from the token ring. Further description of the
data steering logic and control mechanisms are set forth
below.
Data from the local station 45, to be communicated to
3~ a distant station, is transmitted onto the peripheral loop
60, and through the per line switch 43 onto a selected
node transmit highway 68. The node transmit highways
communicate data back to the data steering logic 41. From
data steering logic, data is communicated to the network
transmit highways 64 and onto the network loop via the
transmitter and multiplexer 33.
-30-
As shown in more detail in connection with Figure 12,
each PLS 43 is connected to each of the 8 node transmit
highways and 8 node receive highways. The PLS, however,
is connected to only one local station, though the station
may include a plurality of data communication devices.
Thus, intranode communications between local stations may
be effected by communicating a signal to the associated
PLS which transmits that signal onto a selected node
transmit highway The data steering logic 41 may then
direct that signal from the node transmit highway back to
the node receive highway from which it may be communicated
to another PLS, connected to the receive station. More
details of the operation of the PLS and intranode
communications are set forth below.
It should be noted that when the data steering module
70 connects the TDM highways to the network ring traffic,
the TDM hiohways conceptually form a portion of the ring
network. When the signal into the data steering module is
not intended to be directed to a local station the TDM
ring is bypassed and the signal is transmitted back onto
the network ring via transmit and -multiplexer circuit
33. Unless in use for network traffic the TDM highways
are available for internal calls within the local ring.
Overview of Packet Data Flow Throu~ The Node
Another view of data flow in the system is seen in
Figure 5. That figure illustrates the differentiation
- between the flow of packet switched data and the flow of
TDM circuit switched dataO The token ring data is there
referred to as packet data and the TDM data is referred to
as voice and clear channel data. Packet data and voice
and clear channel data enter the node via modem 55 where
they are demultiplexed into separate packet channels and
TDM channels. The TDM channel is communicated via the
network interface module (NIM) 51 to the station interface
module (SIM) 57, which contains PLS 43 (illustrated at
Figure 4). Details of the construction and operation of
the NIM 5l and SIM 57 are set forth below in detail.
Packet data is also communicated to NIM 5l whereupon it
may be communicated to on-board processors in the NIM 5l
and SIM 57, directly, or communicated to the primary node
processing network 59, which may include a plurality of
individual central processing units (CPU). As previously
noted, the signal communicated between SIM 57 and voice
data digital telephone station 45 preferably includes four
bits of packet switched data carried in the 32 kbps
signaling channel as illustrated in the inset. Four
additional bits from each frame are used for overhead.
One of those four bits encodes framin8 information.
Another bit defines active signaling, i.e. that bit
indicates that the four signaling bits contain valid
signaling data. A third bit encodes an underrun
condition, wherein valid signaling is present but the data
bits in the signaling field are fill characters that
should be ignored by circuitry in the telephone 45,
instead of signaling data. The last of the overhead bits
is unused in the presently preferred embodiment. The
remaining portion of the packet includes eight bits of
data and eight bits of voice or data. Additional
description of the packet channel is set forth below.
A number of applications of the packet switched data
are contemplated. One application for this data is to
facilitate the initialization of calls. Messages
indicating telephone handset off hook, dialed digits and
other button depressions are encoded and carried in the
packet switched signaling channel. These signaling
messages may be passed to one of the 6~000-type CPU
modules 59 that execute the call processing software. In
the case of a voice connection, the dialed digits may be
processed by the call processing software and checked
against a directory of telephone numbers active on the
node. If the called number resides on this node a control
message is transmitted from the 68000-type CPU to the SI~1
~2~ 9
-32-
on which the telephone resides for the purpose of
establishing a clear channel connection to allow
conversation to take place. If the called number resides
on another node a control message is transmitted from the
68000-type CPU to the SIM on which the telephone resides
via the LEN to establish a clear channel connection to
allow a conversation to take place over the TDM highways.
Internal Configuration Of The Node
Figure 6(a) is a block diagram showing the internal
configuration of a switching node. A switching node is
composed of three basic classes of components: buses,
plugable modules, and a power subsystem. The buses are
preferably carried on the backplane of the cabinet for the
system and consist of transmit highways 72, receive
highways 74, global bus 76, segmented general purpose bus
78 and serial bus 80. In the presently preferred
embodiment there are eight receive highways and eight
transmit highways, although it is contemplated that other
numbers oE highways could be employed.
The global bus 76 is a high speed computer bus with
parallel address, data and control lines. The general
purpose bus serves several different functions depending
on the application. In the presently preferred
embodiment, the general purpose bus 78 is partitioned into
four independent segments along the length of the
backplane. One portion of the general purpose bus
comprises a second computer bus which facilitates
communication between a 68000 CPU 75 and a local memory
card 89 such that program access does not cause contention
on the global bus. The global bus may be implemented
mostly as a VME bus (IEEE proposed standard 896), with the
primary exception that Euro Card physical card connectors
are not used. Another application of the general purpose
bus 78 is as an alternate set of transmit and receive
highways. In systems that employ fully redundant dual
rings, two NIM's 51 are utilized. One NIM 51 communicates
to the primary transmit and receive highways, and a second
NIM 51 communicates with the alternate transmit and
receive highways on the general purpose bus.
Other plugable assemblies that are also served by the
general purpose bus 78 include the highway-to-highway
interface module (HIM) 61 which facilitates the switching
of time slots from one set of highways to the other. Each
HIM is a plugable assembly that provides a number of
; variable bandwidth channels from the first level ring to
the second level ring. A bridge node can be populated
with a number of HIM's sufficient to provide capacity for
the maximum level of connectivity required. Those
variable bandwidth channels, or "tie-line channels", in
; the HIM's are dynamically allocated and, when not in use,
do not consume bandwidth from either level ring. The HIM
may also operate as a variable bandwidth time slot
interchange (TSI) which makes it possible for any station
on a first level ring to access any other station on
another first level ring via the resources of the second
level ring. The rings so tied can operate at any
bandwidth, erg. from 8,000 bps to 512 kbps. Thus, both
the bandwidth and the connectivity for inter-ring
communications are dynamically allocatable.
Video interface module (VIM) 63 typically interfaces
192 kbps or 448 kbps channels from the general purpose bus
and mixes a 64 kbps voice channel from the transmit and
receive highways 72 and 74 to service a composite high-
speed voice and data peripheral loop from SIM 57. The
switching functions performed by the HIM 61 and the VIM 63
; 30 are effected by the Quad Per Line Switch (QPLS) which
provide the ability to switch time slots as described
below.
Another application of the general purpose bus 78 is
to transmit data along a number of bidirectional analog
highways for communication between the analog interface
module (AIM) 65 and the modem pool and trunk test module
67. Analog signals can be routed from the analog module
65 directly to an optional trunk test module (not shown)
where diagnostic operations can be performed to determine
the viability of the trunk circuit.
The serial bus 80 provides an economical, low speed
serial communication path between various modules of tne
system. The serial bus carries traffic logically
equivalent to the traffic that is often carried on the
global bus 76, i.e. command and control messages frost the
~0 CPU controller to the various peripheral cards. The
serial bus 80 is dedicated to command and control
information of lower priority and lower traffic volume.
That traffic could equally well be carried on the global
bus 76. The choice is a matter of economics. Modules
along the serial bus, e.g. AIM 65, may be interconnected
to the global bus via the tone generator and module 71,
also referred to as the Tone Interface Module (TIM).
AIM 65 provides interconnection to the telephone
company trunks and to analog telesets, the modem pool and
trunk test module 67 which provides low speed dial-up
modems for diagnostic and test purposes as well as analog
trunk test circuitry, and a Conference Bridge and Voice
Prompting module 69 which performs the algebraic summation
of three, four or eight voice combinations in order that
voice conference calls may be established. Conference
bridge ntodule 69 may also incorporate a voice synthesis
capability to provide prerecorded messages and voice
prompts.
The tone generator and receiver module 71 includes a
number of read only memories to store the tone patterns
required for normal operation of a PBX such as dial tone,
ring back tone, error tone, and the DT~F tones associated
with dialing.
SIM 57 may typically provide an interface to sixteen
voice/data digital telephones on the peripheral
highways. The SIM includes a micro compiler (see module
-35-
139 at Figure 10) that can execute programs which
implement a portion of the X.3 Packet Assembly and
Disassembly (PAD) junction as well as control operations
for establishing circuit connections.
The T-1 carrier module 73 provides an interface for
North American standard 24 channel T-1 carrier service
that permits synchronization with the entire Bell System
communications network. Both common channel signaling,
i.e., utilizing the services of a LAN for control signals,
and in-band signaling, i.e., wherein control signals are
contained in the data stream, may be supported via the T-1
standard clock.
CPU module 75 employs a microprocessor CPU with memory
protection circuitry and direct memory access. The memory
cards typically accommodate 1,000,000 bytes of error
correcting memory and can be configured as either local
memories, e.g. 1MB ECC local memory 89, or as global
memories, e.g. lMB ECC global memory 91. As a local
memory the card attaches to the general purpose bus in a
segment of the backplane dedicated to processor
functioning. The memory uses conventional Hamming code
error correction for 2-bit error detection and 1-bit error
correction. The memory card can also function as a global
memory in which case it operates on the global bus 76 and
functions as a shared memory between two or more 68000
CPU's such as CPU 77 within the node. CPU 77 corresponds
to processor 59 in Figure 5 and functions as the main
processor which implements the principle operating
programs ox the node and communicates instructions and
receives data prom on board processors within modules such
as the NIM 51 and SIM 57 (see Figures 9, 10). Each CPU
module includes a small computer standard interface bus
I/O port which supports multiple master CPU's and allows
up to four CPU's to share a single disc system, e.g. a 10~1
byte winchester desk, or multiple tape and disc systems
79.
-36-
NIM 51 provides control logic and steering logic for
both the LAN controller 81 and the circuit switched TDM
pathways. As is more fully described below, the network
ring signal stream is communicated to NIM 51 via RICU 27
and OF modem 55. The NIM 51 provides connectivity from
the network loop to the internal highways and may be
connected to either the normal transmit and receive
highways 72 and 74 or to the auxiliary transmit and
receive highways that are part of the general purpose bus
78.
Bus interface and control unit (BICU) 83 provides
access to a read only memory contained in Node ID logic
87. In addition, BICU 83 provides access to the
intelligent power supplies 85 which are capable, under
microprocessor control, of monitoring their own
voltages.
Data communications processor 161 is a packet
switching server which can be configured as an X.25 server
or as a local area network bridge, depending upon the
devices to be attached. Processor 161 thus provides a
means of connecting the node to external packet data
networks.
Ring Interface Control
Figure 6(b) illustrates an embodiment of the RICU 27
that serves to bypass failed nodes or to heal the ring if
cable faults occur. The system operates with an active
ring. In the presently preferred embodiment each ring
supports a 16 Mbps token ring and a 32 Mbps synchronous
TDM ring. The token rings in both active and standby
rings may be used to carry data and control traffic. The
active ring may be used to carry circuit switch data and
voice, and the standby ring may carry digital video in the
32 Mbps TDM bandwidth. In event of a failure which
necessitates switching from the active ring to the standby
ring, video transmission may be sacrificed. Similarly, if
broken cables occur and the ring must be healed, video may
also be sacrificed. The RICU 27 may include switching
devices that can bypass a failed node or connect the two
rings together on either side of a node in the event of
node failure or failure in the ring path, respectively.
Typically, such bypass may occur on power failure of the
node, failure of either the receiver or transmitter logic,
or failure of critical components within the node that
render it inoperative. Monitoring of the status of the
node and control of the operation of the RICU 27 is
accomplished by the modem control and status logic 103 in
conl1ection with programming information residing in the
on-board processor 110 in the NIM, described in more
detail in connection with Figures 7 and 9.
In the case oE broken cables, the RICU 27 directs
traffic on the ring to the network interface modules
(NIM's) associated with each node. See Figure 6(a) RICU
27 has switches 57(a-d), controlled by relay control logic
59, which make it possible to connect both rings so as to
heal the defective ring. The resulting structure is
topologically still a ring. However, the traffic on one
of the rings is sacrificed in the healing process.
In the present embodiment, one ring, denominated the
forward ring, has priority over the second ring,
denominated the backward ring. If carried on the backward
ring, video transmission is lost in the event of a
failure. Clearly, other priorities could be applied to
the healing process. If two or more breaks occur in the
ring, the resulting structure may autonomously operate
distributed switches. This capability affords high
survivability to the switching system.
Internal Configuration of RF Modem
Figure 7 is a block diagram of the RF modem 55
employed in the presently preferred embodiment of the
invention. In this embodiment the transmitter 101 and
~5 receiver 93 employ skewed quadriphase shift keyed (SQPS~)
modulation to encode and decode a bit stream of 49.152
~2 ~2
-3~-
Mbps. The information received is framed as s'nown in
Figures 3(b). The output of the receiver 93 is a
continuous bit stream which is processed by the
demultiplexer clock and frame synchronization logic 95.
Logic 95 includes correlation circuitry and a state
! machine which detects a 16-bit frame synchronization
pattern in the bit stream and allows for two consecutive
erroneous frame synchronization patterns before losing
frame synchronization lock. The third and fourth bytes in
the TDM field contain the 16-bit code which is the frame
number within a 65,536 frame multiframe. This time code
allows for process synchronization among the nodes. Both
a total loss of frame synchronization and a transient
frame synchronization error that does not cause a loss of
frame synchronization are detected and indicated. In the
present embodiment the frame synchronization logic
monitors two consecutive frames for bit errors before
causing a loss of frame synchronization and a search for
new framlng.
The TDM receive data output from the demultiplexer 9S
is directed onto an 8-bit parallel bus thaw forms the TDM
highways 82 and the token ring data is directed onto a
4-bit bus that forms token highways 84. The master timing
logic 97 contains an oscillator which is used by a master
node to provide clock and timing for the entire network.
In slave nodes, the master timing logic block, the
transmit logic, and the entire node are driven from the
frame sync clock and multiframe sync derived from the
incoming bit stream in demultiplexer 95. In master nodes
the master timing logic 97 must provide both highway
timing within the node and transmit timing to the network
loop. In an independent FIF0 control timing scheme, the
FIF0 input timing may be derived from the incoming network
ring bit stream 90, though the FIF0 output timing 92, node
timing 94, and transmit timing 9~ are generated by the
master oscillator itself.
2B~
-39-
On the transmit side, multiplexer clock and sync logic
99 receives eight TDM transmit highways 86 and four token
ring highways 88 as a 12-bit parallel bus. Multiplexer 99
combines the data with transmit timing information, passes
the data to the transmitter module 101 where the network
ring bit stream 90 is discharged. The modem control and
status logic monitor 103 monitors the status of the
receiver input power via receiver 93, and monitors bit
synchronization, and frame synchronization via
demultiplexer 95. Modem control and status logic 103 also
monitors the transmitter output power via transmitter 101.
An optional programmable loopback path between
transmitter 101 and receiver 93 is provided for diagnostic
purposes. This allows the output of the transmitter to be
switched to the input of the receiver. This loopback
diagnostic capability typically disconnects the path with
the network loop, and therefore is used only when a node
is taken off line.
The modem control and status logic 103 also processes
and passes control signals to RICU 27 for the purpose of
bypassing a node or healing a broken ring as described
above at Figure 2~d).
Internal Configuration of Data Steering Logic
Figure 8(a) is a diagram of the data steering module
of the NIM 51 which controls the switching of data between
the network loop and the node TDM highways. In Figure 4
above the output of the demultiplexer 53 or FIFO buffer 35
was shown to enter the data steering logic 41 where the
data could be directed to the network transmit highways or
node receive highways. Figure 8 shows how the steering
logic operates to enable the appropriate path in the
presently preferred embodiment. A data steering logic
element 105 exists for each of the eight highways. The
steering ma? 107, which ls shown as external to the data
steering logic 41, is typically a 1K by 16 random access
memory which uses two control bits for each highway.
-40-
These control bits are labelled Bo and l in the control
logic truth table on the righthand side of the Figure.
The output of the control logic 105 comprises four signals
which control the switches labelled (A), (B), (C), and
(D). These switches operate as open collector logic or as
tri-state logic. The truth table indicates which switches
are on or off for the various modes of operation of the
logic.
The steering map control logic 109 contains a 1~-bit
counter which is reset by the frame sync signal and
incremented once for each clock pulse. The control of the
steering map is effected by the steering map control logic
41. The output of the counter is used as the address in
the steering map 107. Once each clock time, the 16-bit
output of the random access memory within steering map 107
is made available to the eight data steering logic
elements 105. There are two pages of memory within
steering map 107: an active page and a background page.
The background page is part of the memory space of the CPU
~0 47 that controls the functions of the NIM 51 (see
Figure 4). The steering map RAM may be organized as a
column of 2 bits by 1K for each of eight highways. Each
bit pair controls a single bit on the network loop. Thus,
to steer an 8-bit byte of data from the network loop into
the node and from the node back onto the network loop
requires writing a desired bit pattern, e.g. 00, into
- eight consecutive positions in memory corresponding to the
time slot being addressedO Bits which are passed from the
network receive highways to the network transmit highways
are not made available to the internal highways o the
node For each of those bit positions, the node transmit
highways are connected to the node receive highways. The
data steering logic l forms a TDM bus for the duration of
such bit intervals. When a bit is to be steered into the
node, switches B and D are opened and switches A and C are
closed, enabling a bit to travel from the TDM receive
highways to the node receive highways and from the node
transmit highways to the TDM transmit highways. Thus, in
a dynamic fashion the internal highways of the node change
from a bus structure for internal calls to a ring
structure for external calls.
Two other modes of operation exist. One mode provides
the multi-drop capability for data communications. In
this mode it is possible to allow multiple listeners for a
single transmission or for multiple terminals to transmit
to a host or terminal controller using a shared circuit.
When a multi-drop is established at each node, all
participants in the network are enabled. One embodiment
of the multi-drop capability is shown in the control logic
truth table wherein switches A, B, and C are on and switch
D is off. This would support either half or full duplex
multi-drop communication such that with switch A on, a
poll message could be received by all terminals and at the
same time the poll message could be propagated to the next
node when the B switch is also on.
All elements of the system are typically designed such
that an idling or unaddressed terminal causes the transmit
highways to be in a high state. Thus, the output of
switch C is typically in a high state for any inactive
terminal in a multi-drop mode. In a normally operating
multi-drop network only one terminal transmits at a
time. Because the terminal controller is in an idle state
the TDM receive highway, i.e. the output of the switch B,
is high. This allows the addressed terminal to pull the
junction at the output of the switch C low as required for
the transmission of its messages.
The background page of the steering map memory can be
read or written by the CPU on the NIM under autonomous
local control or in response to control signals from the
token ring or the ethernet. Once the background steering
map is properly loaded to contain the most recent status
of all calls a bank swap command may be generated by CPU
~Z ~2
-42-
which causes the active and background maps to switch
roles at frame sync timeO Thus, the map that was formerly
in background becomes active and the formerly active map
becomes the background. Additional call setups and/or
knockdowns can be made in the background map after the
bank switch operation has been performed.
Network Timeslot Management
Formation of the data steering map is controlled by
the node designated as the resource manager for each level
ring in the network. The remaining nodes in the ring
(resource servers) may be delegated some autonomous power
to communicate intranode, or internode using preassigned
time slots on the signal streamO The designated resource
manager, however, monitors that delegation and allocates
additional timeslots as necessary.
The administration of the network control functions
for the present invention may be accomplished via a
hierarchy of independent resource managers and resource
servers. Each resource server preferably administers one
or more delegated pools of resources (e.g, timeslots) and
services requests for allocations and deallocations from
its pools in an autonomous fashion. If a pool should
become diminished, it may request an additional allocation
of resource for that pool from its resource manager. If a
pool has an excess of available resource manager for
redistribution. The resource manager oversees the
distribution and utilization of resource and provides for
administration of "fairness" and "priority" rules for its
correspondent servers, All communications from resource
servers to the resource manager may be via generic
addressed messages. These generic messages are
communicated via the token ring or the ethernet and are
processed at the node that is currently hosting the
resource manager for that ring. Though all nodes may
receive the generic message only the resource manager node
will respond to the message by modifying the allocation to
-43-
the requesting network server node, as required. Thus, it
is not necessary for each server in the ring to knor,7 the
exact logical node address for current resource manager,
which greatly simplifies the task of re-esta~lishing
S control in case of a failed resource manager, since the
messages will automatically be delivered wherever the
resource manager is installed.
In the presently prefered embodiment, there is full
redundancy of the manager function for each ring of the
hierarchy, thus, any node is capable of performing
resource server functions can also be a resource
manager. The designation of which node will perform the
resource manager function is made trivial by the fact that
one node of each ring must already be deisgnated as source
of synchronization for the ring, as previously
described. Thus, the designation of ring synchronization
master can be made to also imply the designation of
timeslot resource manager for that ring. All recovery
strategies developed for line of succession of ring
synchronization mastership will work equally well for
recovery of the timeslot manager function. If during
recovery procedures the newly inaugurated timeslot manager
is for any reason unable to access the current copy of the
ring allocation data, it may issue a broadcast message
requesting the ring servers to report themselves and their
current allocations. The responses to this broadcast may
then be checked for consistency and used to rebuild the
timeslot allocation data base. A flow chart of a program
to implement the functions of the network timeslot manager
and the network timeslot server is set forth at Figure
8(b) and 8(c), described below.
During initial start-up the designated timeslot
manager for each ring will begin with a pool that
represents all of the available timeslots on that ring.
It will either have available from data-base or will build
a map of the nodes (i.e. timeslot servers) on that ring
and decide on initial allocations for each server either
based on historical data from data-base or via pre-defined
defaults.
For a Level 1 Ring (i.e. Orbit) the initial
allocations to each node may include a pool of slots
reserved from general distribution to create a "free-pool"
for support of conflict-free intra-node calling for all
the server nodes. Another pool may be reserved for
distribution of tone sources to all nodes from a
designated source node. Each server node in the Orbit is
then initialized with the following information: the
location and extent of the "free-pool" (intra-node), the
"tone pool", and its primary allocation for a network
timeslot pool. Once a server node has been initialized in
this manner, it is then ready to begin establishing
circuit switched connections both internal and network
using timeslots from its known pools without need for
further interaction with the ring timeslot manager until
one or more oE its pools are exhausted. Use of those
allocations will depend upon the bandwidth requirements of
the interconnected devices. Thus, each network server
node need use no more of its timeslot allocation than is
necessary.
When an Orbit server attempts to establish an
intra-nod connection it looks for available slots in
its"free-pool" and may use any that it finds of the
correct dimensionality. In the case where no slots are
available, it may borrow one or more slots from its
network pool as available. When attempting to establish a
connection from the network pool (inter- or intra-node)
the server will first examine its primary allocation and
choose from these slots if any are available. If the
primary allocation is depleted, the server will next check
secondary, then tertiary, etc. allocations until either it
winds the required slot(s) or there are no more to
check. In the latter case the server may request an
-~5-
additio-nal allocation fro-n the ring manager and if granted
will add it as the last choice of all o~,~ned allocations.
Whenever a server node finds a secondary or higher ordered
allocation unused and has a predefined additional amount
of unused resource (for hysteresis), it will voluntarily
return the unused allocation to the ring manager for
redistribution.
The ring timeslot manager can keep track in its data
base of the pattern of additional allocation requests by
various nodes to build a fairly accurate time averaged
model of the "normal traffic load" for each server in its
ring. This can then be fed back into the configuration
data base so that each server's primary allocation will be
for the most part sufficient to carry its normal
traffic. The goal in this is that secondary and tertiary
allocations be devices to help deal with the occasional
peaks and shifts in traffic distribution, not the
sustained average load. Furthermore, the dimensionality
of the free-pool can also be fine-tuned empirically by
examining a server parameter which reports the peak
percentage utilization of the "free-pool" with the
objective being to choose the value which keeps the worst
case server(s) as close to 100% as possible. Finally, the
ring timeslot manager can provide an ongoing measure of
ring traffic loading. When its pool of available slots is
nearing exhaustion it can broadcast an instruction to the
server nodes to return any unused units immediately, and
if this does not yield sufficient relief, it can further
instruct the servers to enter a predefined load-shedding
mode which will defer allocations to lower priority
functions until the overload condition has subsided.
The Timeslot tanager for an Orbit Ring with 8 highways
at 4 Mhz will have
~2 9
-46-
(8 x 512) - (F x 8) - (T x 8) = 4096 - [(F = T) x 8] bitslots
where for example F (Free Pool)=40, T (Tone Pool) =32,
= 3520 bitslots
available after subtracting the allocations for
"Free-pool" and "Tone-pool" bytes. The free-pool
allocation can overlay the slots required for frame
synchronization flags so that no additional bandwidth is
consumed for them.
For the Level 2 Ring (i.e. System) the allocation is
similar to Level l, but even simpler since there is no
requirement for a free-pool or a tone pool. This is
because typically the only nodes on the Level 2 Ring are
Bridge Nodes which have no voice or data ports and hence
no need to support intra-node communications. Moreover,
each Orbit will contain one or more tone sources (for
redundancy) so there is no need to transport tones across
the System Ring. Thus the Timeslot Manager for a System
Ring with 8 highways @ 4 Mhz will have
(8 x 512) - (4 x 4) = 4080 bitslots
available (after subtracting frame synch requirements) for
distribution to the Timeslot Servers in the Bridge
~5 Nodes. Furthermore, since it is anticipated that a System
Ring will be available with highways at 8 Mhz, it could
have as many as
(8 x 1024) - (4 x 4) = 8176 bitslots
available to carry inter-Orbit traffic for large
systems. The system timeslot manager would be resident in
the Bridge Node which provided System ring synchronization
and would make allocations to the system servers in the
Bridge Nodes based on their static (primary) and dynamic
(secondary, etc.) demands.
With the above scheme establishment of a du?lex
network circuit for a voice or data connection becomes
straightforward. The node originating the connection
needs only to consult with its resident server to obtain
an Orbit timeslot. If necessary, the resident server may
request an additional allocation from the Orbit timeslot
manager to satisfy this request. Once the timeslot is
obtained the originating node sends a message to the
terminating node, via the token ring or the ethernet, to
establish the connection with that timeslot. If the
desired connection is an intra-Orbi~ circuit, the
terminating node receives that message, programs its data
sterring module and PLS accordingly, and returns a
connection established message. If the requested
connection involves an inter-Orbit circuit, the message
will be received by the network circuit manager (NCM) in
the Bridge Node of the originator's Orbit. The NCM will
request a System ring timeslot from its System timeslot
orbit timeslot to the System timeslot and vice versa. It
then forwards a connect request message for the System
timeslot that was allocated to the NCM at the Bridge Node
of the terminator's Orbit. The NCM at the Bridge of the
ter~inator's Orbit receives this message, requests a
timeslot from the pool of its Orbit timeslot server, and
programs an available highway-highway link from the System
timeslot to the Orbit timeslot and vice versa. It then
forwards a connect request message for the Orbit timeslot
to the terminating node, which programs its data steering
module and PLS accordingly and returns a connection
established message to the originating task.
If either the System timeslot server or the Orbit
timeslot server were unable to satisfy the request for a
timeslot, it would consult its respective timeslot manager
for an additional allocation, and the timeslot manager
would in turn broadcast a request for immediate release of
unused timeslots to all the servers in its ring if it were
~2~
-48-
unable to satisfy the request directly. Thus only in the
case where all t'ne servers of a ring had no available
; timeslots would the request for connection establis'nment
fail.
~aGY_~,3~l95~nger (RTM) Functions:
RTM functions can be understood in connection with the
flow chart provided at Figure 8(b), which can be
summarized as follows:
1. On ring initial start-up, establisn tone zone and
intra-node zone, if required, and issue primary allocation
to each RTS based on prior history if available, else use
default values.
2. Maintain tables of all current allocations and
administer a MAX function to prevent excessive allocations
to any RTS. Alert ring master diagnostic manager if any
apparent cases of non-normal usage by an RTS are detected.
3. Service requests for additional allocations based
on priority of requests Dynamic computation of
allocation unit size will select units of 8, 4, 2, or 1
byte depending on size of remaining pool, the current ring
status level, and the number of RTS's being managed.
4. Collect periodic RTS statistics and log to data
base. Also perform a periodic audit check that each RTS's
allocation map is in agreement with the data in the master
tables. Resolve any conflicts so detected.
5. Issue broadcasts or requesting early release of
unused allocation units upon reaching ring status decrease
thresholds to prevent unnecessary boundary crossings.
6. Issue broadcasts for change of ring status.
7. Return freed allocation units to available pool
with recombination of continuous pieces whenever possible.
8. On recovery start-up, broadcast request to RTS's
for report of current allocations, rebuild the data base,
and check data obtained for consistency. Resolve any
conflicts which may be found.
-49-
9. During system "least busy" periods, revier,
current primary and intra-node allocations versus
accumulated actual usage data and make strategic
adjustments as required.
10. Maintain historical data base of allocations,
usage, and other traffic related statistics.
Ring Timeslot Server (RTS) Functions:
The functions of te RTS can be understood in
connection with the flow chart provided at Figure 8(c),
which can be summarized as follows:
l. On start-up or restart, announce presence to Ring
Timeslot Manager (RTM) via generic addressed message, and
request primary allocation.
2. Service local requests for intra-node allocations
as follows:
a. if (Ring Status < Request Priority) then
fail request, else
b. check intra-node pool as first choice,
c. if b) fails, then attempt to borrow from
inter-node pool (see 3 below for inter-node
allocation schema),
d. if c) fails, then request additional
allocation from RTM at intra-node priority,
if request fails then return failed,
2~ e. if request granted add new allocation to end
of list and service the request.
3. Service local requests for inter-node allocations
as follows:
f. if (Ring Status < Request Priority) then
fail request, else
g. check primary allocation as first choice,
h. if b) fails, then check secondary, tertiary,
. . ., etc. allocations in order until
success or list exhausted,
i. if c) fails, then request additional
allocation from RTM at specified priority,
if request fails then return failed,
-50-
j. if request granted add new allocation to end
of list and service the request.
4. Respond to RTM Status Poll messages.
5. Maintain local statistics for following: (in
bit-slots)
k. current total of all inter-node owned
l. current amount of inter-node in use at each
priority level
m. average amount of inter-node used since last
poll
n. peak amount of inter-node used since last
poll
o. current amount of intra-node in use at eac'n
priority level
p. average amount of intra-node used since last
poll
q. peak amount of intra-node used since last
pol 1
6. Maintain value for Current Ring Status
Internal Confi uration of NIM
Figure 9 is a block diagram of a NIM 51 illustrating
the relationship between the data steering module, the
local area network (LAN) controller and the on board
processor. The details of data steering module control
have previously been described. Control messages to the
data steering nodule are provided by the CPU portion of
the on board processor 110. It should be noted that on
board processor 110 is repeated in, e.g. SIM 57, HIM 61,
SIM 63 and AIM 65. With the exception of some functions
peculiar to those modules, the processor is programmed to
perform the same function in each module. One
commercially available processor that is suitable to
perform the required functions is the model 8088 processor
produced by Intel as Corporation, in cooperation with a 68
K Byte 2-port RAM. The on board CPU 115 obtains messages
from the 68 K CPU 77 (Figure 6(a)), and the circular
~%~ 9
-51-
buffers in the 64 K bytes 2-port RAM 121 of Figure 9. As
described earlier the data steering module 123
incorporates part of the memory space of the CPU 115.
As noted above the steering map of the data steering
module block 107 of Figure 8 can be conceived as having
one word for each time slot on the node highways and t~1o
bit locations within each word corresponding to each of
the eight highways within the node. Therefore, in order
to set up a connection on the network, the CPU block 115,
Figure 9, writes into the background page of the steering
map. The words correspond to the time slots to be
allocated, and the bit positions correspond to the highway
to be allocated. The bit values are selected from the
control logic truth table on Figure I. The CPU 115
causes such connections to be made Gn demand of the 68 K
CPU 77, Figure 6. CPU 77 writes control messages into
circular buffers contained in the 64 K Bytes 2-port RAM
121, Figure 9. The on board CPU 115 controls the
operation of the entire NIM. When the NIM is powered on
Eor the first time an initialization program is executed
from read only memory (ROM) 111. At that time complete
diagnostics are also executed, and if the board is
functional a code so indicating is written into the Board
Control and ID Register 119. At that time, CPU 115 goes
into a state awaiting acknowledgment from the CPU 77,
shown at Figure 6~a). CPU 77 writes a code into the board
control and ID register 119 via on board bus 102, which
enables CPU 115 to read and write the transmit and receive
TDM buses 22 and 74, enables the interrupt logic, and
3~ enables the 64 K Bytes 2-port R~ onto the global bus
76. The operational code modules for CPU 115 are loaded
into the 64 K Bytes 2-port RAM 121 by the CPU 77. CPU 115
then executes its code from 2-port RUM 121. The 2-port
RAM 121 also contains a number of circular buffers for
communication between CPU 115 and CPU 77.
-52-
The NIM is event driven, wherein events are signals
initiated by devices attached to the peripheral highways
via the SIM 57, the AIM 65, the VIM 63, or the T-1 carrier
module 73, shown at Figure 6(a). The 2-port RAM 121 can
5 be viewed as part of the memory space of CPU 77 and is
accessed via the global bus 78.
Internodal control message traffic, requesting
establishment of a circuit, is handled with the Lair
controller 125, which communicates timeslot management
10 control information in accordance with the previous
description. LAN controller 121 may, in practice, be
mounted on the NIM and therefore may be viewed as part of
the NIM. However, it is understood that such a
construction is not necessary to the invention.
If a node has a control message for another node, that
message is typically generated and formatted by the CPU 77
and written into a circular buffer in 2-port RAM 121 of
the NIM. CPU 115 then processes the message, adding the
necessary protocol information and passes the message to
20 the LAN controller 125 for transmission to the distant
node. Similarly, a control message coming from a distant
node via the LAN will be arriving at the LAN controller
125 and will be processed by the CPU 115, and passes the
message to the CPU 77 via a circular buffer and 2-port RAM
121.
Thus, if the message traffic from a distant node were
a request to establish a circuit, that message would
arrive in the LAN controller 125 and protocol handling
would be accomplished by CPU 115, which removes the
30 necessary protocol information. The message would then be
written into circular buffer and 2-port RAM 121. The
circuit request would be processed in the CPU 77, and the
final request for circuit establishment would be generated
by CPU 77 via a message written into a circular buffer in
35 2-port RAM 121. That message would then be processed by
CPU 115. In a manner earlier described, the CPU 115 would
load the data steering module 123 to set up calls.
~z~
-53-
When messages are written into the 2-port JAM 121 by
either CPU 115 or CPU 77, the interrupt control logic 117
is employed. Messages emanating from the NIM cause
interrupts to be generated for the CPU 77. Messages from
the CPU 77 to the NIM cause interrupts of the processor
115 via the interrupt control logic 117.
Except for dynamically enabling the connection of node
transmit highways to node receive highways, the NIM
assembly is not involved in calls within a node, but it is
o involved in all calls between nodes. The RF modem control
logic 127 is used to communicate with the RF modem for
diagnostic and control purposes and for control of the
RICU 27, which is a peripheral of the RF modem. The two-
to-one multiplexers 129 are used to select between the
normal transmit and receive highways and an alternate set
of transmit and receive highways which may Eorm a part of
the general purpose bus. In redundant systems, which use
two NIM's, one NIM is set up to communicate with the
normal transmit and receive highways and the second NIM is
set up to communicate with the alternate set of transmit
and receive highways. Messages for directing such setups
to occur are passed to the NIM via circular buffers and
the 2-port R~ 121.
Timers 1l3 include a watchdog timer that is reset by
the CPU 115 periodically in order to indicate proper
functioning of the CPU and its associated programs. If a
failure occurs which results in the inability of the CPU
115 to reset the watchdog timer portion of timer 113, that
portion will activate the reset line to the CPU which will
tenDinate its operation and cause the board control and ID
register 119 to indicate that the board is inoperative.
Other timers included in 113 provide timing for measuring
intervals between various events of significance involved
in the handling of communications protocols between nodes.
-54-
Internal Configuration of SIM
Figure 10 is a block diagram of the station interace
module (SIM). The processor portion of the SIM is similar
to the NIM and all messaging and control between the SI~I
and CPU 77 follows the same procedures described in the
NIX. The entire system described in this invention is
event driven where events occur asynchronously (e.g.,
initiated by the various assemblies that interface to
human users or to intelligent peripherals such as
computers) or synchronously (e.g., initiated by various
process controls). The SIM serves as an interface to the
digital station equipment attached to the peripheral or
local highways 104. A user of a digital teleset connected
to a peripheral highway can initiate events by pressing
buttons on the telephone, by lifting the handset, or by
toggling the various modem control lines on the data
interface portion of the station. Such an event causes a
signal to be transmitted from the telephone to the SIM via
the wires of the peripheral highway. Two pairs of wires
typically carry DC power for a digital telephone. One
pair is used to transmit to the telephone while the other
pair is used to receive messages from the -telephone. Quad
line interfaces 133 interface the peripheral highways to
the I/O ports of the quad per line switch (QPLS) 131.
2~ It is common practice to equip a node with more
peripheral highways than are actually in use. The teleset
power corltrol register (TPCR) 147 is used to selectively
control the power transmission to the telephones (e.g., 16
stations) supported by the SIM. That is, any telephone
can be turned on or off by setting the appropriate bit in
the power control register 147. PCR 147 thus permits
powering down selective peripheral highways as Jay be
desired for various reasons, e.g. to prevent their
unauthorized use, or to reduce power consumption in order
to accommodate battery operation of the node in the event
of a power failure.
Messages generated by stations on the peripheral
highways are received by the QPLS 131, which passes the
messages to the CPU 139 in on board processor 259. r~hen a
valid signaling message is received the CPU either takes
immediate action or passes the message or interpretation
of the message to the 68 K CPU 77 (Figure 6(a)) via a
circular buffer in 2-port RAM 145. Messages from stations
requiring immediate feedback include tone feedbac1~ to
indicate valid depression of buttons and other character
echoing functions for data applications. After a
telephone number is dialed, the message indicating that a
connection is to be established is generated by the CPU 77
and sent to the on board CPU 139 via a circular buffer of
the 2-port RAM 145. The CPU 139 then processes the
message and causes one per line switch (PLS) of the four
within QPLS 131 to be programmed for use of the particular
time slot or time slots as detailed below in connection
with Figures 12 and 13. Intra-node connections typically
require independent receive and transmit time slots,
though network connections may require only a single time
slot.
Brief Description of the Quad Per Line Switch (QPLS)
In the preferred present embodiment, the QPLS consists
of four essentially identical Per Line Switches (PLS).
Each PLS operates independently and each can switch
variable bandwidth information channels of data from
independent node information highway input, carrying
internode or intranode signal traffic, to an external
station device on a peripheral highway, or to another node
inforrnation highway. The data from the external station
device can therefore be switched via the variable
bandwidth channels onto any selected node information
highway outputs. The channel and bandwidth selections in
each PLS are all completely independent of each other. In
the present embodiment, sixteen independent node
information highways (eight transmit and eight receive)
-56-
are available for use by all PLS's. In the preferred
embodiment, each PLS contains a packet channel for
transferring control and general purpose data and circuit
switched channels for communicating voice to and from a
station device. Both the packet channel and the circuit
switched channels are interlaced into a single serial
signal stream communicated to and from the station
device. Packet data in both directions may be monitored
for errors utilizing cyclic redundancy generating and
checking circuits.
The QPLS can be configured under program control such
that the PLS's operate in pairs to tranQmit data to and
receive data from two station devices at twice the normal
data rate. As described below, the PLS's can also be
configured to operate as a single switching unit to
transfer data between the information highways and a
single station device at four times the normal data
rate.
When operating with local station devices, that is
devices connected on the same circuit board as the QPLS,
the PLS's can transfer data to and from the station
devices in synchronization with the information
highways. When operating with remote station devices,
that is devices connected to the QPLS circuit board by
transmission lines, the PLS's can operate synchronously
with the devices, transmit to them in synchronization with
the information highways, and receive from the devices by
self-synchronization with each device. In the presently
preferred embodiment the QPLS can also switch nine
3~ channels of data between information highway inputs and
outputs without transferring data to or from a station
device. when the QPLS is operating in this manner,
information highway data may be time compressed or
decompressed by setting the data rate on the information
35 highway outputs to be a multiple or submultiple of the
data rate on the information highway inputs.
2~%15~9
-57-
Detailed Descrip tion of the Quad Per Line S~Jitch
Figure 11 shows a wiring diagram of the Quad Per Line
Switch (QPLS) 221 in its presently preferred embodiment.
The QPLS may be advantageously manufactured as a 4~-p in
5 large scale integrated circuit having the inputs and
outputs shown.
The operation of the QPLS can be more easily
envisioned by an understanding that the QPLS selectively
routes data between one or more of the information
highways (272 and 274) within the node and the station
devices 290. As was described in the background and
summary of the invention, the QPLS routes the data on the
basis of time division multiplexing. The particular
selection and timing of data transfers between the
information highways and the station devices is controlled
by an external control means such as microprocessor 223
shown in Figure 11.
Because the QPLS is used to transfer data to and frorn
information highways, a brief description of the
information highways will be presented before proceeding
with the detailed description of the invention. In the
present embodiment, the eight information highways are
identical and are used to transfer time-division
multiplexed data to and from the QPLS. The eight
information highway inputs (HYWI7-0) 274 are distinct from
the eight information highway outputs ~HYW07-0) 272.
However, in alternative implementations, the information
highway inputs 274 and information highway outputs 272 can
be tied together to form a bidirectional data path to and
from the QPLS.
Description of the Data Transfer F_rmats
and QPLS Configurations
The forrnat of the time-division multiplexed data on
the information highways is shown in Figures 17(a), 17(b),
and 17(c). The serial data to and from the QPLS is
transmitted in synchronization with clock signals. The
~x~ g
-58-
information highway inputs 274 are synchronized with the
highway input clock (HIC) 278, and the information highway
outputs 272 are synchronized with the highway output (HOC)
clock 282. Typically, the highway input clock 278 and the
highway output clock 282 will be supplied from the same
source and will be the same signal. In Figure 17, the
highway input clock 278 and the highway output clock 274
are shown as one signal. Alternatively, the information
highway inputs 27~ and the information highway outputs 272
can operate at different data rates to allow the data on
the information highway inputs to be compressed or
decompressed. For instance, if the highway output clock
(HOC) 282 operates at twice the rate of the highway input
clock (HIC) 278, the data from two information highway
inputs 274 could be compressed by the QPLS and transmitted
out on one information highway output 272 at twice the
data rate. Decompression of data could be accomplished by
operating the highway input clock 278 at a multiple of the
highway output clock 282.
Data is continuously transferred to and from the QPLS
on the information input highways 274 and information
output highways 272. Because the information is time-
division multiplexed, further synchronization of data is
required. The fr~ne sync input (FSI) 276 occurs
periodically to mark the beginning of a new frame of
information on the information highway inputs 274. In the
present embodiment, the frame sync input 276 occurs every
125 microseconds, and thus has a repetition rate of 8000
hertz. Similarly, the frame sync output (FSO) 280 occurs
;30 every 125 microseconds, and marks the beginning of a new
frame of information on the information highway outputs
272. Typically, the frame sync input 276 and the frame
;sync output 280 are the same signal In the presently
preferred embodiment, the highway input clock 278 and the
highway output clock 282 will operate at 2048 kHz, or 256
times the repetition rate of the frame sync input 276 and
-59-
frame sync output 280 (i.e., 8000 X 256). Thus, because
the information on the highways is synchronized with the
clock, there will be 256 pieces of information within each
frame. Each of the pieces of information occupies a time
slot in a message frame as shown in Figure 17(a).
Similarly, if the highway input clock 278 and highway
output clock 282 operate at 4096 kHz or 8192 kHz, the
number of information bits derived by the QPLS per frame
will be 512 or 1024, as shown in Figures 17(b) and 17(c)
respectively.
As previously described, the QPLS transfers data
between the high-speed information highways 272, 274 and
the station devices 290, which operate at a slower data
rate Typically, a station device can receive data at a
rate of 128 kbps. This is illus-trated in Figure 18(a)
which illustrates the 16 time slots within the 8000 Hz
frame, resulting in a 128 kbps data rate. Because a
single information highway input typically transfers data
at a rate 16 times higher than the station device (i.e.,
2,048,000 bps, or 128,000 frames per second, each frame
including 256 information bits), only selected portions of
an information highway frame can be transferred to the
station device. The difference in data rates can be seen
by comparing the information highway data rates
illustrated at Figure 17 with the station data rates
illustrated at Figure 18.
Returning to Figure 17(a), each of the 256 pieces of
information in a frame on the information highways is
called a data bit, or channel The QPLS transfers
selected portions of the data on the information highways
from the information highways to station devices, and
transfers data from the station devices to selected time
slots in the message frames of t'ne information highways.
In the preferred embodiment, up to 64 bits of information
can be transferred from the information highways to
station devices and from the station devices to the
-60-
information highways during each 125-microsecond frame.
That transfer rate occurs when each of the four PLS's in
the QPLS transfers 16 bits of information during a single
frame.
As described below, valid data is transferred in
groups comprising one to eight bits of data in each
direction. The number of valid bits of data in a group is
the bandwidth of the group. The location of the bit, with
reference to the beginning bit of the information frame,
is designated as the channel of the information. The
ability of the QPLS to dynamically select the channels and
the bandwidths of the data to be transferred, as will be
described more fully below, is one of the advantages of
the QPLS over the prior art which permits more efficient
use of the network signal stream.
As will be described more fully below, the QPLS has
the ability to dynamically increase the rate at which data
can be transferred between the information highways and a
station device. In the normal data rate configuration,
the QPLS can transfer up to 128,000 bits per second (i.e.
16 bits/frame) to each of four station devices. In the
medium data rate configuration, the QPLS can transfer up
to 256,000 bits per second (i.e. 32 bits/frame) to two
devices. In the high data rate configuration, the
2~ can transfer up to 512,000 bits per second (i.e. 64
bits/frame) to a single station device. The formats of
the data transferred in the medium data rate configuration
and the high data rate configuration are illustrated in
Figures 18(b) and 18(c).
In the normal, medium and high data rate
configurations the data transfers may occur synchronously
or asynchronously with the data on the information
highways. In the "local" mode, data transferred to and
from the station devices connected to the QPLS is
synchronized with the information highway clocks 278, 282
and the frame syncs 276, 280, by direct connection to
-61-
those signals. The station devices can also be controlled
by the same means as the QPLS. However, if the stations
devices are not on the same circuit board as the QPLS, it
is not always practical to have the station devices
controlled by the same clocks and synchronization signals
(i.e., be in the local mode). The QPLS can also be
configured in the "remote" mode to synchronously transfer
data to and from such remotely connected devices without
sending the highway clocks and synchronization signals to
the devices. In the remote mode the transmission of data
to and from remote devices by the QPLS is accomplished by
synchronizing data transfers with the information highway
timing. The data from the remote devices to the QPLS is
self-synchronized within the QPLS by transmitting the data
from the device as biphase mark encoded data in a format
shown in Figure 20. As compared with nonreturn-to-zero
(NRZ) data, the biphase mark encoded data has at least one
transition between the high and low state for each data
bit. decoding circuit in the node can derive a clock
and a data signal from the encoded signal. Of course,
other well known self-synchronizing data formats can be
used.
Furthermore, because the external means which control
the QPLS is not on the same circuit board as the station
devices, the QPLS must provide means of transferring
synchronization information as well as control and status
information between the external control means and the
station devices. In the presently preferred embodiment
those needs are accommodated by transferring
synchronization information and control and status
information within the signals transferred between the
device and the QPLS. The synchronization signals and the
control and status signals comprise the first eight bits
of data preceding the sixteen bits of information data
transferred between the QPLS and the station devices.
This is illustrated in Figure 19(a). As can be seen by
8~L~
-62-
comparing Figures 18 and 19, the 125 microsecond message
comprises 24 data bits in the remote mode as as compared
to 16 data bits in the local mode. In order to
accommodate the additional eight bits of data, in the low
data rate configuration, the data is transferred between
the QPLS and the station device at 192 kHz, in contrast to
the 128 kHz data rate in the local mode. Similarly, as
shown in Figures l9(b) and 19(c) for the medium and high
data rate configurations, in the remote mode the data is
transferred between the QPLS and the station devices at
; 1.5 times the corresponding data rates in the local mode.
The QPLS can also be reconfigured to selectively
bypass any of the station devices. In this "loopback"
mode, the information from the QPLS which would normally
be transferred to a station device is instead transferred
from selected information highway inputs 274 to selected
information highway outputs 272, That configuration can
be advantageously used for diagnostic purposes or for
switching between information highways.
More detailed descriptions of the local/remote mode,
the low data rate/medium data rate/high data rate mode,
and the normal/loopback mode will be disclosed below in
connection with the detailed drawings.
Again referencing Figure 11, the QPLS 221 transmits
data to the four station devices 290 on the line outputs
(LO3-LO0) 284 and receives data from the four station
devices 290 on the line inputs (LI3-LI0) 286. In the
local mode, the data on the line outputs and line inputs
is synchronized with the data on the information highway
inputs (HYWI7-0) 274, and with the information highway
outputs (HYWO7-0) 272 by the line clock (LC) 288. The
line clock (LC) 288 operates at the data rate of the
information highways (2,048; 4,096; or 8,192 Kbps). In
the remote mode the line clock operates at higher rates,
e.g., 12,288 Kbps, and facilitates encoding and decoding
of data communicated between the station devices and the
-63-
information highways over transmission lines. Upon
receipt of data from the information highways in the
remote mode, the line clock is used to generate biphase
mark encoded data transmitted to the station devices on
the line outputs. Upon receipt of data from a station
device in the remote mode, the line clock is used to
decode the biphase mark encoded data received from the
station devices on the line inputs by sampling the input
signal at sixteen times the maximum input data rate. The
biphase mark encoded data is sometimes referred to as
biphase Manchester encoded data.
QPLS Control Lines
The QPLS 221 is controlled by a microprocessor 223
which represents the SIM on-board processor 259 (Figure
10) as updated by the 68 K CPU 77 (Figure 6(a)).
Principal control signals are communicated to the QPLS via
the address lines (~D4-AD0) 402, the data lines
(DAT7-DAT0) 404, the read/write control line (R/W) 406,
and the strobe (STB) 408. The QPLS signals the
microprocessor upon the occurrence of internal events by
activating the interrupt line (INT) 410. The QPLS is
initialized by the microprocessor or by external power-on
reset logic by activation of the chip initialize line (CI)
412. The five address lines (A~4-AD0) 402 are
controllable by the microprocessor and determine the
interface operation to be performed. The read/write
control line (R/W) 406 determines whether data or control
information is transmitted from the microprocessor to the
; QPLS in the write mode, or whether data or status
information is transmitted to the microprocessor from the
QPLS in the read mode. Such data, control or status
inEormation is transmitted over the eight bidirectional
data lines (DAT7-DA~0) 404. The strobe (STB) 40~ clocks
data into the QPLS in the write mode and indicates
completion of the data transfer in the read mode. The
chip initialize line (CI) 412 functions to cause the QPLS
-64-
to be initialized to certain known conditions when it is
activated by the microprocessor or power on reset logic.
In particular, the QPLS is disabled from communicating
with the information highways or the station devices until
specifically activated by the microprocessor.
General Description of Data Flow
From Highways to Station Devices
As shown in Figure 12, the QPLS 221 is composed of
four essentially identical per line switches (PLS's) 243
a, b, c and d. Functionally, each PLS 243 consists of a
station-to-highway circuit 244 and a highway-to-station
circuit 246 which operate independently or in conjunction
with the corresponding circuits in the other PLS's. The
highway-to-station circuit 246 (forming the right hand
portion of Figure 12) receives serial information data
from the information highway inputs 274 and transfers the
data in the selected format to the station device
290(a-d), (see Figure 21) connected to the respective
PLS. The highway-to-station circuit 246 includes
information channel output circuits (ICO1 386 and ICO0
388), the packet channel output circuit (PCO 390), the
biphase mark encoder circuit (BME 393), and the output
logic control circuit (OLC 389). As shown in more detail
in Figure 13(a), each information channel output circuit
ICO1 386 and ICO0 388, selects an information highway
input 274, a starting bit for a channel on the highway and
a channel bandwidth independently of the other. In the
preferred embodiment, both ICO1 386 and ICO0 388 each
receive up to eight bits of data from the information
highway inputs 274 in one 125-microsecond frame. The data
is transmitted to the station device 290 during the
following 125-microsecond frame in one of the formats
shown in Figures 18 or 19. In the local mode, in the
preferred embodiment, the PCO 390 and BME 393 are bypassed
by line 614, thus eliminating the packet channel portion
of the signal. In the remote mode, in the preferred
~24
-65-
embodiment, the PCO 390 appends eight bits of pac'~et data,
consisting ox synchronization bits and control
information, to the data signal, from the information
channel output circuits The total 24 bits of serial
5 information transformed to biphase mark encoded data by
BME 393 and are transmitted at 1.5 times the local data
rate in the 125-microsecond frame in the format described
in more detail in connection with Figure 19(a).
General Description of Data Flow From
Station Devices to Highways
The station-to-highway circuit, e.g. 244d in PLS 243d
(the left hand side of Figure 12), consists of the input
logic control (ILC 387), the biphase mark decoder (BMD
461) the information channel input circuits (ICI1 582 and
ICI0 584), the packet channel input logic circuit (PCI
385) and the input message control logic circuit (IMC
381). The station-to-highway circuit 244 in PLS 243d
receives serial data on LI3 286d from the device 290d
connected to the station port and transfers that data to
selected channels on selected information highway outputs
272. Each of the inEormation channel input circuits, ICI1
382 and ICI0 384, independently selects an information
highway output 272, a starting bit for a channel on the
highway and a channel bandwidth. In the local mode, only
16 bits of data are input to the PLS 243d and the packet
channel input logic circuit 385 in the station-to-highway
circuit 244d is not used. The data from the station
device 290d is typically in nonreturn-to-zero (NRZ) data
format, and the biphase mark decoder logic 461 is not
used. This is accomplished under the control of ILC 387
which channels data directly to ICI1 382 rather than to
BMD 561. The IMC 381 allows the data to be clocked in
synchronization with the information highway outputs
274. In the remote mode, the biphase mark decoder (BMD)
261 in the station-to-highway circuit 244d receives
encoded data from ILC 387 and derives NRZ data and a clocl;
8~9
from the encoded data. The first eight bits ox the 224
bits of data are used by the packet channel input circuit
(PCI) 385 to derive data and status information from the
station device for transmission to the microprocessor.
The derived NRZ data is then communicated via OLC 387, to
the highway outputs in ICI1 and ICI0,, and to the PCI
385. Data from PCI 385 is accessed by the microprocessor
223 via data lines (DBA7-0) shown on Figure 25. The PCI
385 and IMC 381 function to verify that the received data
is synchronized.
Interconnection of the PLS's or Higher Data Rates
As shown in Figure 12, the PLS's are interconnected to
allow data transfers to occur at higher data rates. In
the low data rate configuration, each PLS 243 operates
independently and transmits up to 16 bits of data to and
receives up to 16 bits of data from its corresponding
station device 290 in the local mode, or 24 bits in each
direction in the remote mode. As described below, the
PLS's may function in pairs, or four at a time to
accommodate higher data rates.
Higher Speed Data Rate Configurations
(a) Highway-to-Station Interconnections
In the medium data rate configuration, the
interconnections of the highway-to-station circuits 246 of
two PLS's, such as PLS0 and PLS1, allow the two PLS's to
operate as a single unit. The output of ICO0 388 or PCO
390 of PLS1 is input to ICO1 386 of PLS0 via OLC 389.
Thus, in the local mode, the output of PLS0 to the station
device is 16 bits of data from PLS0 followed by 16 bits of
data from PLS1, and will be transmitted on line LO0 284a
to the station device Z90a connected to OLC 389 of PLS0.
The resulting 32-bit data signal is transmitted to the
station device 290a in 125 microseconds at twice the low
data rate in the format shown in Figure 18(b). In the
remote mode, the data signals from the highways and the
accompanying control and signaling information to the
-67-
station device, e.g. 48 bits of signal total, are
transmitted to the station device 290a in one frame, e.g.
125 microseconds. No data is transmitted to an external
device on PLS1, and BME 393 of PLS1 is bypassed via line
616, because the data will be encoded by BME 393 in
PLS0. The operation of PLS2 and PLS3 in the medium data
rate configuration is substantially identical to t'nat set
forth in connection with PLS0 and PLS1. The data received
from the information highway inputs 474 selected by ICO1
386 and ICO0 388 in PLS2 and PLS3 is transmitted to the
station device 290c connected to OLC 389 of PLS2.
In the high data rate configuration, the
highway-to-station circuits 246 in the four PLS's are
interconnected so as to cooperatively transmit data to the
station device 290a connected to PLS0. All four PLS's are
interconnected in a fashion similar to the PLS
interconnections in the medium data rate configuration,
with the data output of PLS2 (ICO0 388 or PCO 390)
transferred to ICO1 386 of PLS1. In the local mode, data
signals from the highways connected to ICO0 and ICO1 of
each PLS, e.g. up to 64 bits, are transmitted to the
station device connected to PLS0 during each
125-microsecond frame at four~times the normal data rate,
in the format shown in Figure 18(c). In the remote mode,
data and control signals from ICO0 388, ICO1 386, and PCO
390 of each PLS, e.g. 96 bits are transmitted to the
device in the format shown in Figure 19(c).
(b) Station-to-Highway Interconnections
The station-to-highway circuits 244 in each PLS 243
may be similarly interconnected to operate at different
data rates. In the medium data rate configuration of the
station-to-highway circuits 244, data is received from the
station devices 290a, 290c connected to PLS0 and PLS2.
The data from the station device 290a connected to PLS0 is
input through ILC 387 of PLS0. In the remote mode, the
data signals and the accompanying control and signaling
-68-
information, e.g. 48 bits, from the station device 290a
are clocked through ILC 387 of PLS0, and N~Z data and
clock are derived from the encoded signal by BMD 461 of
PLS0. The data is then clocked through ILC 387, ICI1 382,
ICI0 384, and PCI 385 of PLS1, then back through ILC 387,
ICI1 382, ICI0 384, and PCI 385 of PLS0. In the remote
mode, clocking and synchronization of the data is
controlled by IMC 381 of PLS0. BMD 461 of PLS1 is not
used in this configuration since the clock and data have
been derived by BMD 461 of PLS0. In the local mode, the
data signals, e.g. 32 bits, from the station device, are
;input through ILC 387 of PLS0, then through ILC 387, ICI1
382, and ICI0 384 of PLS1, then back through ILC 387, ICI1
382 and ICI0 384 of PLS0. The interconnections between
PLS2 and PLS3 are similar to the interconnections of PLS0
and PLS1 in the medium data rate configuration, and the
data is input from the station device 290c connected to
ILC 387 of PLS2.
In the high data rate configuration of the
2~ station-to-highway circuits 244 data is received from the
station device 290a connected to ILC 387 of PLS0. In the
remote mode, the signal data and control and signaling
information, e.g. 96 bits, from the station device 290a is
clocked through ILC 387 of PLS0 where NRZ data and clock
~2~ are derived by BMD 461 of PLS0. The data is then clocked
;through ILC 387, ICI1 382, ICI0 384, and PCI 385 of PLS3,
PLS2, PLS1 and PLS0, in that order. Synchronization and
clocking are controlled by IMC 381 of PLS0. In the local
mode, the signal data, e.g. 64 bits, from the station
device 290a connected to ILC 387 of PLS0, is clocked
through ILC 387 of PLS0, then through ILC 387, ICI1 382,
and ICI0 384 of PLS3, PLS2, PLS1 and PLS0, in that order.
General Description of the Loopback Mode
Another feature of the QPLS is the ability to
3~ configure the PLS's in the loopback mode. In the loopback
mode, each PLS can independently select the output of OLC
-69-
389 as the input to ILC 387. Thus, data on the input of
the highway to station circuit is transferred to the
output of the station to highway circuit without any
communication to the station device. The effect is to
permit information transfer between highways via the
QPLS. Referencing Figure 12, the loopback mode has the
effect of routing data from t'ne information highway inputs
274 selected by the information channel output circuits
(IC01 386 and ICOO 388) of the PLS to the information
highway outputs 272 selected by the information c'nannel
input circuits (ICI1 382 and ICIO 384) of the same PLS.
Thus, a PLS in the loopback mode can switch data between
selected information highway inputs 274 and selected
information highway outputs 272 without involving a
station device. This ability can be implemented at the
various QPLS data rates. For example, in the medium data
rate configuration, the input of ILC 387 of PLSO selects
the output of OLC 389 of PISO. This has the effect of
routing the data from the information highway inputs 274
selected by IC01 386 and ICOO 388 of PLSO to the
information highway outputs 272 selected by ICI1 382 and
ICIO 384 of PLSO, respectively, and routing the data from
the information highway inputs 274 selected by IC01 386
and ICOO 388 of PLS1 to the information highway outputs
272 selected by ICI1 382 and ICIO 384 of PLS1,
respectfully. Additionally, in the remote mode, a PLS in
the loopback mode routes the packet data from the
microprocessor through PCO 390 and back through PCI 385
where it can be accessed by the microprocessor. Thus, the
operation of the packet channel logic can be tested prior
to routing any data to a station device connected to that
PLS. T'ne operation of PLS2 in the loopback mode in the
medium data rate configuration has similar effects on PLS2
and PLS3. In the high data rate configuration, ILC 387 of
PLSO selects the output of OLC 389 of PLSO. The data from
the information highway inputs 274 selected by the
-70-
information channel output circuits (ICO1 38~ and ICO()
388) of each PLS is routed to the inforrnation highway
outputs 272 selected by the corresponding information
channel input circuits (ICI1 382 and ICI0 384) of each
5 PLS.
General Description of the Diagnostic Channel
Figure 16 is a block diagram of the optional
diagnostic channel of the QPLS. As shown in Figure 16,
the diagnostic information highway read channel (ICOD) 503
receives serial information of a selected bandwidth from a
selected channel of a selected information highway input
274. The serial information received is stored as eight
bits of parallel data in holding register 593, and can be
read by the microprocessor. The diagnostic channel can
operate in either the loopback mode or in the
microprocessor controlled mode. In the diagnostic channel
loopback mode, the stored data in register 593 is
available to the diagnostic information highway write
channel (ICID) 501, which can then transfer the data to a
selected channel of a selected information highway output
272 at a selected bandwidth. Alternatively, in the normal
mode, the microprocessor can communicate eight bits of
data to a holding register 596 in ICID 501 via the control
interface logic 591, shown in Figure 14. In this mode,
the data from the microprocessor can be transmitted to the
selectPd information highway until changed or disabled.
The diagnostic channel may be used to test the information
highways by providing a means of switching data between
information highway inputs 274 and information highway
outputs 272, or between information highway inputs 274 and
outputs 272 and the microprocessor 223 without using the
PLS's or a station device.
DETAILED DESCRIPTION OF THE ~PLS
A more detailed description of the operation of the
various parts of each PLS follows and is referenced to the
detailed block diagrams of Figures 13, 15 and 16, and the
QPLS I/O Address Assignment Table.
~2~
Description of the Information Channel Output Circuits
As shown in Figure 13(a), information channel output
circuit 1 (ICO1 386) and information channel output
circuit 0 (ICO0 388) are substantially identical and t'ne
following description of the operation of ICO1 is
applicable to ICO0. In the preferred embodiment,
information channel register 411 is a 16-bit register
which receives the control information for ICO1 386. The
control information in register 411 is loaded from the SIM
on-board microprocessor 223 via control interface logic
591 (shown in Figure 14) which represents a portion of the
SIM on-board processor 259 shown at Figure 10. Selection
of the particular bandwidth and highway is accomplished by
operation of the network management program, previously
described. Information regarding the operating
characteristics of the transmitting or receiving station
is maintained in the 68 K CPU 77 of the respective server
nodes, which implement the network server programs.
The signal from microprocessor 223 to register 411
sets register 411 to enable an input from an information
highway at a particular time, and for a particular
bandwidth. Since the microprocessor transfers data in
bytes of eight bits, the data required for register 411 is
transferred in two eight-bit bytes. The first eight-bit
byte of data is stored in a temporary register (not
shown), and both bytes are transferred to register 411
when the second byte is transferred from the
microprocessor. In the preferred embodiment, the format
of the data in the information channel registers 411 and
409 is as follows:
Information Channel Register Format
H2 H1 H0 B1 B0 E C9 O C7 C6 C5 C4 C3 C2 C1 C0
; 35 The 3 most significant bits of the register 411, H2,
H1 and H0, control the multiplexer 419 w'nich gates one of
8~
-72-
the eight information highway inputs (HYWI7-HYWI0) to the
shift register 415O The highway selection is typically
encoded as follows:
H2 Hl H0 Highway
0 0 0 HYWI0
O 0 1 HYWI1
0 1 0 HYWI2
0 1 1 HYWI3
1 0 0 H~I4
1 0 1 HYWI5
1 1 0 H~II6
1 1 1 HYWL7
The least significant ten bits in register 411, C9-C0,
define the starting location of a message time slot in
the information frame. ReEerring to Figure 17, the data
on the information highway inputs during each cycle of the
highway input clock occupies a time slot in the
information frame. Each time slot has a duration of
20appro~imately 490 nano9econds at 1,024 kilobits per
second, 245 nanoseconds at 2,048 kilobits per second, and
122 nanoseconds at 8,1g2 kilobits per second. in the
preferred embodiment, the information frame has a duration
of 125 microseconds, and the time slots are thus repeated
2S8,000 times per second. The ten bits, C9-C0, can provide
the binary representation of each of the 1,024 time slots
in the message frame operating at 8,192 kilobits per
second. Only nine bits, C8-C0, are required to represent
each of the 512 time slots at 4,096 kilobits per second,
and only eight bits, C7-C0, are required to represent the
256 time slots at 2,048 kilobits per second.
Bits C9-C0 prom register 411 are compared in
comparator 413 with the output of counter HIRC 423.
Counter HIRC 423 is a ten-bit binary counter which is
reset to zero (0000000000) with each occurrence of an
active signal on the information highway frame sync input
-73-
FSI 278. Each of the clock signals on the highway input
clock HIC 276 will cause HIRC 423 to increment by one
count. Thus, the ten outputs of HIRC 423 will provide the
binary representation of the current time slot location
within an information frame. If the information rate on
the input highways is 8,192 kilobits per second, HIRC 423
will count from zero (0000000000) to 1,023 (1111111111)
before being reset by FSI 278. Similarly, at 4,096
kilobits per second, HIRC 423 will count from zero to 511,
l and at 2,048 kilobits per second, HIRC 423 will count from
zero to 255.
If the ten binary outputs of HIRC 423 match bits C9-C0
from register 411, the output of comparator 413 will be
active to enable shift register 415 and shift the data
from the selected information highway from multiplexer 419
into shift register 415. The number of bits of data
shifted into shift register 415 will depend upon the
bandwidth selected by bits B1 and B0 of register 411. The
bandwidth selection is typically encoded as follows:
B1 B0Bandwidth
0 0 1 bit
0 1 2 bits
1 0 4 bits
1 1 8 bits
The bandwidth bits, B1 and B0, are also inputs to
comparator 413 and selectively disable the three least
significant bits of the comparator. If the selected
bandwidth is one bit, all ten bits of HIRC 423 must be the
same as C9-C0 of register 411 before the output of the
comparator will be active to enable shift register 415.
Thus, there will only be one successful comparison in each
information frame, and, as explained in more detaiL in
connection with Figure 13(c), shift register 415 will only
shift in one bit from multiplexer 419. If the selected
bandwidth is two bits, the least signiicant bit of the
comparator is disabled. Thus, there will be t~,70
successful compares per information frame since the
comparator cannot distinguis'n between two counts differing
only by the least significant bit. For example, count 19
(00010011) will compare the same as count 18 (00010010).
The output of comparator 413 will therefore enable the
shift register 415 to shift in two bits from multiplexer
419. In like manner, comparator 413 will not check the
least significant two bits of HIRC 423 to allow register
415 to shift in four bits, and will not check the least
significant three bits to allow register 415 to shift in
eight bits. In an alternative embodiment (not shown), the
bandwidth can be selected as 3, 5, 6, or 7 bits.
Control register 411 also has a bit designated as E.
this bit when set enables the output of the comparator
413. If it is not set, the output of comparator 413 is
disabled and shift register 415 will not be enabled at any
time during the information frame. Thus, a bandwidth of
zero can be selected.
At the end of the information highway frame, the data
in shift register 415 is parallel loaded into shift
register 417. As previously described, the transfer to
shift register 417 is controlled by the status of B1 and
B0. Although illustrated as a single shift register in
Figure 13(a), shift register 415 is, in the preferred
embodiment, comprised of multiple stages as illustrated in
Figure 13(c). Decoder 415(a) generates one of four output
signals, sel8/, sel4j, sel2/ or sel1/ depending upon the
bandwidth selection by bits B1 and B0 described above. B1
and B0 activate sel8/ when an eight bit bandwidth is
desired. When sel8/ is activated, OR-gate 415(b) will
enable the serial data from the information highway input
multiplexer 419, described above. Eight HIC clock edges
enabled by comparator 413 through AND-gate 415(j) will
cause the data from OR-gate 415(b) to be shifted through
the four-bit shift register stage 415(c), multiplexer
-75-
415(d), two-bit shift register 415(e), multiplexer 415(f),
flip-flop 415(g), multiplexer 415(h) and into flip-flop
415(i)- The Q-outputs of 415(c), 415(e), ~15(g), and
415(i) will be transferred to shift register 417.
Multiplexers 415(d), 415(f) and 415(h) are adapted to
select their B inputs because their select lines are
inactive in the eight-bit bandwidth configuration.
If a bandwidth of four bits is selected, decoder
415(a) will activate the sel4/ line. 0~-gate 415(b) will
not be enabled by sel8/ and, therefore, will force all
"ones" into shift register 415(c). In response to sel4/,
multiplexer 415(d) will select the direct serial data from
multiplexer 419. Four HIC clock edges enabled by
comparator 413 through AND-gate 415(j) will shift the data
through shift register 415(e), multiplexer 415(f),
flip-flop 415(g), multiplexer 415(h) and into flip-flop
415(i). Shift register 415(b) will have four "ones" on
its outputs.
The operation o the circuits for bandwidths of two
and one are similar, with the first data bit in the input
stream from multiplexer 419 shifted into flip-flop 415(i)
and the remaining data bits or fill data of all ones
shifted into the other shift registers us a result of
the selective shifting of data through the stages of
register 415, the most significant bit of data from the
information highway input will be in the most significant
bit position of register 415 at the end of the frame for
any selected bandwidth. Thus, the data will be
transferred to shift register 417 with the most
significant bit of data from the inEormation highway input
in the most significant bit portion of shift register 417.
The operation of inEormation channel output 0 (IC00
388) is independent of but identical to information
channel output 1 (IC01 386). It can select an information
highway and a time slot on the highway totally independent
of the selection of IC01. As described previously, the
8~
information channels do operate together to shift the
information data from shift registers 417 and 403 to the
station device. In order to accomplish this, the serial
output of shift register 417 of ICO1 386 is the serial
input to shift register 403 of ICO0 388 as shown in Figure
13(a).
In order to provide the interconnections to configure
the highway-to-station circuits of the PLS's in the medium
and high data rate configurations, the input to shift
register 417 of ICO1 386 will be the output of the output
line control logic of the next higher numbered PLS. For
example, the input to shift register 417 for PLS0 will be
the output of the output line control logic (OLC 389) of
PLS1. The connections to implement the higher speeds of
operation are effected by enabling interconnection of the
PLS's under program control implemented by the SIM
on-board processor in response to directions from the ~8 X
CPU 77 (Figure 6(a)), In the local mode of the higher
speed configuration, multiplexer 391 in the output line
control logic (OLC 389) of the next higher PLS is
similarly controlled such that the input to shift register
417 of a PLS will be the output of shift register 403 of
the next higher numbered PLS. In the remote- mode,
multiplexer 391 of the lower numbered PLS selects the
unencoded output of shift register 401 through multiplexer
395 in the packet channel logic (PCO 390). Figure 15
shows the interconnections between the PLS's which provide
for the transfer of serial information between the PLS's
in the medium and high data rate configurations.
Des lption of the Packet Channel Output Logic Circuit
As previously described, the packet channel output
(PCO 390), Figure 13(a), is bypassed in the local mode,
and the output of shift register 403 is communicated
directly to multiplexer 391 in the output line control
logic OLC 389. The output of OLC 389 is in turn
communicated to the station port, via buffer 589, or in
the higher data rate configurations, to ICO1 386 of the
next PLS, as shoT~n in Figures 12 and 13(a).
In the remote mode, the packet out control logic 421
receives timing signals derived from the highway input
clock (HIC) 278, the highway frame sync input (FSI) 276,
and the line clock (LC) 288, and receives control signals
from the microprocessor 223 via the control interface
logic 591 (shown in Figure 14). In response to the
control and timing signals, the packet out control logic
4~1 controls the contents of the first eight bits of data
in each frame sent to the device 290 connected to the
station port. The format of the first eight bits of data
sent to the station port through output line control (OLC)
389 is shown in Figure 19 and implemented as illustrated
in connection with Figures 13(a) and 24. During those
periods in which no packet data is being transmitted to
the station device by the external control 1neans, the
eight bits will contain the following idle states. The
first bit to be transmitted is the sync bit, S, which
alternates states once each frame. The second bit to be
transmitted is the packet flag bit which will be in the
reset state (1). The third through sixth bits to be
transmitted comprise the four packet data bits which,
during idle periods, contain all ones. The seventh bit to
be transmitted is the K flag which, during idle periods,
is in the reset state (1). The eighth bit to be
transmitted is always in the zero state.
When the packet data register 399 is loaded, a packet
flag within the packet out channel control logic 421 is
set This action causes PCO 390 to exit the idle state
and enter a busy state, and an indication of this status
(busy) is made available to the external control means.
At the beginning of the frame hollowing the frame in which
the packet data was loaded, the shift register 401 will be
loaded with the following states. The first bit will be
loaded with the current state of S, the second bit will be
-78-
loaded with the set state (0) of the packet flag PF, the
third through sixth bits will be loaded with the four
least significant bits of the loaded packet data from
register 399, the seventh bit is loaded with the reset
state (1) of the K flag, and the eighth bit is loaded with
a zero. The next consecutive frame will contain the same
status with the updated state of S and the four most
significant bits of packet data from register 399.
If the microprocessor does not cause the packet
register 399 to be reloaded with data within 250
microseconds (two frames), following the last load, the K
flag is set (0) to indicate that the data in the next
frame is fill data, of all 1's within an active packet
message, which should be ignored by the device connected
to the station port. The packet out control logic 421
will continue to send packet data as received or send fill
data until the microprocessor causes the packet flag (PF)
to be reset by executing a write command to the
appropriate address of the control interface logic 591
(shown in Figure 14). When that occurs, the internal
packet flag is reset. The PLS will typically send four
additional frames of packet data, which will consist of
the sixteen bits of cyclic redundancy checking (CRC) data,
before resetting the packet flag in the data sent to the
station device. After outputting the CRC data, the packet
out control 13gic 421 will re-enter the idle state with
operation as previously described.
A typical format for the control and signaling
information generated by the packet channel output logic
PC0 390 at different data rates is shown in detail in
Figures 19(a), 19(b) and 19(c). The four bits labelled
l'PD" are the bits from the microprocessor; "K" is the K
flag; "PF" is the packet flag to the station device; and
l'S" is a synchronization bit which alternates between its
set and reset states in successive frames.
-79-
The data from shift register 401 is communicated to
the cyclic redundancy generation circuit (C~C 397). Only
the four bits of recognizable packet data from each frame
are shifted through the CRC 397O Furthermore, only that
packet data with the packet flag (PF) set (0) and the K
flag reset (1) is shifted through. When the packet flag
(PF) is reset (1), the packet out control logic 421 causes
the sixteen bits of data accumulated by the CRC 397 to be
communicated to the multiplexer 395 and to be subsequently
output to the station device as the last four frames of
packet data. Wren a typical station device receives the
reset packet flag, it can perform a cyclic redundancy
check on the accumulated data to determine whether there
were any errors in the received data. Cyclic redundancy
generation and checking circuitry is well known to the
art. For example, a description of a typical cyclic
redundancy generating and checking circuit can be found in
Encyclopedia of Computer Science and Engineering, 2nd Ed.,
Van Nostrand Reinhold Co., Inc., 1983, at pp. 434-437.
Description of the Biphase Mark Encoder Circuit
The output of multiplexer 395 is input to the biphase
mark encoder (BME 393) which converts the nonreturn to
zero (NRZ) output of multiplexer 395 to biphase mark
encoded data. In general, the biphase mark encoder
assures that each bit time of the output data will include
at least one transition from the high to low logic state,
or vice versa, and an exemplary format is shown in Figure
20. Each "1" in the data stream is represented by two
transitions in the bit time and each "0" by only one
transition per bit time. A circuit in the receiving
device can derive data and clock from the encoded signal.
The output of the biphase mark encoder 393 is
transferred to multiplexer 391 which is part of the output
logic circuitry 389. The other input to multiplexer 391
is the output of shift register 403 which bypasses the
packet channel output logic (PCO 390) in the local mode as
-80-
described above. The output of the multiplexer 391 is
buffered through buffer 589 and then transmitted to an
external pin to which the station port device 290 is
connected. The output of the multiplexer 391 is also
available in -the loopback mode as an input to the input
logic circuitry of the same PLS, and is available as the
input to the next lower numbered PLS, as shown in Figures
12, 13 and 15, for configtlring the PLS's as units of two
or four devices for medium data rate and high data rate
operation.
The synchronization bits generated by each PLS are all
active when the PLS's are configured in the low data rate
mode. In the medium data rate mode, only PLS0 and PLS2
have active synchronization bits, and PLS1 and PLS3 force
their sy-nchronization bits to an inactive (1) state. In
the high data rate mode, only PLS0 has its synchronization
bit active and PLS1, PLS2 and PLS3 all force their
synchronization bits to an inactive (1) state.
Description of the Information Channel Input Circuits
As illustrated in Figure 12, and as shown in more
detail in Figure 13(b) and in Figure 15, the data from the
station devices 290 is input to each PLS through the input
logic circuitry ILC 387. Also, in response to the
configuration commands, each ILC 387 provides the means of
configuring a plurality of the PLS's to operate in
conjunction in the medium and high data rate
configurations. Exemplary means of interconnecting the
PLS highway input circuit in the different modes and
configurations are described below.
Local Mode
As shown in Figure 13(b), multiplexer 587 of each PLS
selects either the data from the station port in the
normal mode or the data from the output of the
corresponding highway-to-station circuitry in that PLS in
the loopback mode. us described above with regard to the
data flow from the information highways to the station
-81-
ports, the output of the PLS in the loopback mode can be
N~Z data or encoded data, depending upon whether the QPLS
is in the local or remote modeO
In the local mode, multiplexer 383 of each PLS selects
the output of multiplexer 587 of that PLS. In the remote
mode, multiplexer 383 selects the output of the biphase
mark decoder (BMD) 461 of that PLS. Similarly,
multiplexer 585 selects either the output of shift
register 357 of ICI0 384 in the local mode or the output
of shift register 341 of PCI 385 in the remote mode. In
the medium and high data rate configurations, the output
of multiplexer 585 is an input to the next lower numbered
PLS to provide a means of interconnecting the
station-to-highway circuitry of the PLS's.
Multiplexer 583 in each PLS selects the input to ICI1
382 of that PLS, depending upon whether the QPLS is in the
low, medium or high data rate configuration. In the low
data rate configuration, multiplexer 583 selects the
output of multiplexer 383 of the same PLS. As shown more
clearly in Figure 15, in the medium data rate
configuration, multiplexer 583 of PLS3 selects the output
of multiplexer 383 of PLS2; multiplexer 583 of PLS1
selects the output of multiplexer 383 of PLS0; multiplexer
583 of PLS2 selects the output of multiplexer 585 of PLS3;
and rnultiplexer 583 of PLS0 selects the output of
multiplexer 585 of PLS1. As also shown in Figure 15, in
the hi8h data rate configuration, multiplexer 583 of PLS3
selects the output of multiplexer 383 of PLS0; multiplexer
583 of PLS2 selects the output of multiplexer 585 of PLS3;
multiplexer 583 of PLS1 selects the output of multiplexer
585 of PLS2; and multiplexer 583 ox PLS0 selects the
output of multiplexer 585 of PLS1.
In the local mode, in the low data rate configuration,
the data in each PLS is transferred from the output of
multiplexer 587, through multiplexer 383, and through
multiplexer 583 to the serial input to shift register 369
~2~
-82-
of ICI1 as shown in Figure 13(b). Typlcally, sixteen
clock edges per frame generated by control interface logic
591 (shown in Figure 14), using timing signals derived
from the highway input clock (HIC) 278 and frame sync
input ~FSI) 276 as a reference, will cause the data to be
shifted through shift register 369 of ICI1 and shift
register 357 of ICI0 until the first bit of information
data is in the most significant bit position of shift
register 357. In the medium data rate configuration in
the local mode, typically 32 clock edges will cause the
information data entering through multiplexer 587 of PLS2
in one frame to be shifted through shift registers 369 and
357 oE PLS3 and then through shift registers 369 and 357
of PLS2 via multiplexer 585 of PLS3 and multiplexer 583 of
PLS2. Similarly, information data entering through
multiplexer 587 of PLS0 will be shifted through shift
registers 369 and 357 of PLS1 and then through shift
registers 369 and 357 of PLS0 via multiplexer 585 of PLS1
and multiplexer 583 of PL,S0. In the high data rate
configuration, the information data will enter through
multiplexer 587 of PLS0, and, typically after 64 clock
edges, the data will be shifted through registers 369 and
357 of PLS1, and registers 369 and 357 of PLS0, in that
order, via the multiplexer selections described above.
Remote Mode
~Ln the remote mode, the shifting of the input data is
similar except, as previously described, the data from the
station devices comprises control and signaling
information as well as the information data. In the low
data rate configuration, the data from each station device
is input through multiplexer 587 of each PLS and then
through the biphase mark decoder (BMD) 461 which generates
a synchronous clock and NRZ data from the encoded
signal. The control and signaling information is encoded
into the data from the station device by a unit such as a
microtelephone controller (MTC), at the local station.
~2~
-83-
Details of the structure and function of an exemplary MTC
are set forth below.
The NRZ output of BMD 461 is transferred through
multiplexer 383 and multiplexer 583 to s'nift register 3~9
of ICI1. After 24 clock edges, the data will be shifted
through shift register 369 of ICI1 and s'nift register 357
of ICI0 and then through shift register 355 of PCI 385.
The control and signaling information in each frame will
be in shift register 355 after the shifting is complete.
In the medium data rate configuration in the remote mode,
48 clock edges derived by BUD 461 of PLS2 will shift the
data from BMD 461 of PLS2 through shift registers 369, 357
and 355 of PLS3 and then through shift registers 369, 357
and 355 of PLS2 via the previously described
connections. Similarly, the data from BMD 461 of PLS0
will be shifted through the corresponding registers of
PLS1 and PLS0 by 48 clock edges from BMD 461 of PLS0. In
the high data rate configuration in the remote mode, after
96 clock edges derived by BMD 461 of PLS0, the data from
BMD 461 o PLS0 is shifted through shift registers 369,
357 and 355 of PLS3, PLS2, PLS1 and PLS0 in that order via
the previously described connections. In each of the data
rate configurations J the input message control (IMC) 381
of each PLS will monitor the packet flag and fill flag in
2S the control and signaling data shifted through shift
register 355 of PC0 385 of the PLS and will verify that
the message is in synchronization by checking the
alternating state of the sync bit S. If the packet flag
is set and the fill flag is not set, the four bits of
packet data in each frame will be shifted from shift
register 355 into shift register 351 and into cyclic
redundancy checker (CRC) 353 of PCI 385. The further
operation of PGI 385 will be described in more detail
below.
8 9
-84-
Transfer of Data Within Information Channel Input Circuits
The operation of the station-to-highway circuitry in
ICI1 and ICI0 of each PLS is substantially the same
whether the QPLS is configured in the low, medium or high
data rate configurations or whether the QPLS is in the
local or remote mode. In either the local or the remote
mode, the parallel output of shift register 369 of ICI1
may be transferred to buffer 371 upon receipt of the next
frame sync output signal on FSO 280. The data in buffer
371 from the previous frame may be simultaneously
transferred to shift register 373 on the same signal on
FSO 280. Thus, the data in shift resister 369 is delayed
by one full frame (125 microseconds) before being
transferred to shift register 373. This allows the
synchronization of data from an asynchronous station port
to the frame timing of the information highway outputs
272. In like manner, the parallel output of shift
register 357 is transferred to buffer 359 and then to
shift register 361 in ICI0. In the local mode, buffers
371 and 359 can be bypassed if the line buffer bypass bit
(B) is set in the control interface logic 591 (shown in
Figure 14). Typically, this will be done if the highway
input clock (HIC) 278 and highway output clock (HOC) 282
are tied together, and the frame sync input (FSI) 276 and
the frame sync output (FSO) 280 are tied together. This
would cause the information highway inputs 274 and
information highway outputs 272 to be synchronized.
In the preferred embodiment, register 377 in the
information channel input logic (ICI1 382) shown in Figure
14 has the same format as register 409 and register 411 in
the information channel output logic (ICOO and ICO1).
Those formats are set by SIM on-board processor 259
(Figure 10) in response to information received from the
68 K CPU 77 (Figure 6(a)). The information in the 68 K
CPU is derived from the LAN network which processes
information representative of the bandwidth requirements
of the transmitting and receiving stations.
~2
~85-
The ten-bit counter (HORC 425) is reset with signal
on frame sync output (FSO) 280 and is clocked by the
highway output clock (HOC) 282. The ten bits from the
counter (HORC 425) are input to comparator 375 and are
compared with the channel selection information in the ten
least significant bits of register 377. Bits B1 and BO of
register 377 control the compare logic 375 in the same
manner as the compare logic 407 and 413 in the information
channel output logic When the output of HORC 425 is
identical to the channel selection bits (C9-CO) in
register 377, the compare logic will generate 1, 2, 4, or
8 clock edges, depending upon the bandwidth selected by
bits B1 and BO, and will shift data out of shift register
373 into the demultiplexer 379. Thus, C9-CO and B1-BO
define a time slot on a highway. The demultiplexer 379 is
controlled by bits H2, H1, and HO of register 377 and
selects one of the eight information highway outputs. If
bit E of Legister 377 is set, the data from shift register
373 will be inserted on the selected information highway
output (HYW07-HYWOO) 272 after being synchronized with HOC
282 in register 597. Otherwise, the selected information
highway output 272 will not be afected.
The control register 365, compare logic 363, and
demultiplexer 367 in information channel input O (ICIO
384) operate in the same manner as in information channel
1 (ICI1 382). The operation of information channel input
O (ICIO 384) and information channel input 1 (ICI1 382) in
each PLS is controlled independently.
It should be noted that although the allocation of
highways and timeslots for communications between local
devices connected to a common node need no require
network bandwidth, such allocations must be consistent
with network allocations. As previously noted, the 68 K
CPU 77 (Figure 6(a)) in conjunction with the SIM on-board
processor, functions to allocate timeslots from the node
-- free pool (if available) and assign particular highways
-86-
for a communication path. Intranode traffic can be
channeled in a manner that takes into account the
timeslots and highways assigned to internode traffic, and
avoids conflicting assignments.
Alternative Embodiment
In an alternative embodiment, the amount of circuitry
required for implementation of the device can be reduced
by providing only one channel register for each of the two
channels in each PLS. Thus, rather than considering the
station-to-highway and highway-to-station sections of each
channel separately as has been done heretofore (iOe., ICOl
and ICIl), each channel of each PLS can be considered as a
unit. One register can then be used to select the time
slot during which the channel is active and to select the
direction of data flow on the selected information
highways. separate bit in the register selects the
direction of data flow. Each channel operates on two
information highways which are selected by the register.
Each channel will receive data from one information
highway and translDit data on another information
highway, If the status of the direction bit is changed,
the use of the two information highways is reversed. In
this alternative embodiment, the information highway
inputs 274 and the information highway OlltpUtS 272 are the
same physical units, and data can be sent in either
direction on the highways under control of the direction
status bit in each PLS. The use of this alternative
embodiment can enhance the utilization of the available
time slots in a given information frame since two PLS's
3~ can accomplish complete bidirectional (i.e., full duplex)
communication in only one time slot. One PLS will
transmit on one highway during the time slot while
receiving on another highway The PLS with which it is
communicating will transmit on the highway on which the
first PLS is receiving and will receive on the highway on
which the first PLS is transmitting. Changing the status
-87-
of the direction bit in each of the two PLS's will re~Jerse
the direction of data flow on the two information
highways. This has been found to be particularly
advantageous at a system level wherein the allocation of
time slots for communications between two PLS's at a local
level must be compatible with the system allocation.
Thus, since full duplex communications between two PLS's
can be accomplished with only one time slot, this
alternative implementation can effect a savings in system
resources as well as a savings in device complexity. In
this alternative embodiment, the highway input clock (HIC)
278 must be the same as the highway output clock (HOC) 282
and the frame sync input (FSI) 276 must be the same as the
frame sync output (FSO) 280.
description of the Packet Channel Input Logic
Reverencing Figure 13(b), the packet in control input
logic 592 oE each PLS will keep track of the control data
input to the PLS in the remote mode. When eight bits of
packet data have been shifted into shift register 351, the
packet in control logic 592 will, providing that the
end-of-message (E) status is not set and providing that
six bytes of packet data are not already stored in the
FIFO 349, parallel load the packet data into the six-byte
first-in/first-out resister, FIFO 349. The data available
status bit (D) is set for that PLS. The status bits (D0
for PLS0, D1 for PLS1, etc.) are available as inputs to
the SIM on-board microprocessor to indicate which FIFO's
349 have active packet data. The first byte of data in
the FIFO 349 is available on the output of the FIFO 349 to
be read by the SIM on-board microprocessor. The FIFO 349
has an internal FIFO counter which is incremented for each
byte of packet data received from the device connected to
the station port, and is decremented for each byte of
packet data which is read by the microprocessor. The FIFO
counter is not affected by fill data. When the fifth byte
of data is loaded into the FIFO the FIFO full (FF) flag is
8~3
set (1) which causes the status interrupt flag (IO for
PLS0, I1 for PLS1, etc.) to be set (1) and causes an
interrupt to be transmitted to the microprocessor. The
microprocessor can read the QPLS interrupt status (Address
08) to determine the source of the interrupt via interupt
control logic 141 (Figure 10). Although it is recognized
that various signal formats may be implemented without
departing from the scope of the invention, the format of
the interrupt status in the presently preferred embodiment
can be as follows:
I3 I2 I1 I0 D3 D2 D1 D0
The FIFO 349 will hold one additional byte after the FIFO
full (FF) flag is set. If a seventh byte of packet data
is attempted to be loaded into the FIFO 349, the FIFO
overrun (OR) flag is set (1). Only the first six bytes of
data in the FIFO are retained.
The packet data received by the QPLS with the packet
flag (PF) set (0) and the fill flag (K) reset (1) is also
transferred in the cyclic xedundancy checker CRC 353.
When the packet flag (PF) is reset (1) in the input data
stream, the outputs of the CRC 353 are checked to
determine whether an error has been detected. If an error
is detected, the CRC status bit (C) will be set l and
will be available to the microprocessor when the PLS
packet status is read. The resetting of the packet flag
(PF) also sets (1) the end of message status bit (E),
which causes the interrupt flag (I0 for PLS0, I1 for PLS1,
etc.) to be set (1), and causes an interrupt to be
transmitted to the microprocessor on the interrupt line
(INT) 610. When the end of message status bit (E) is set,
the last two bytes of data in the FIFO 349 typically
should be ignored since they contain data which was
generated by the CRC generator in the station device and
do not contain packet message data; however, some
diagnostic tests may utilize this CRC data.
~2~
~9
If the overrun status bit (OR) becomes set aster the
end of message status bit (E) is set, there has been an
overrun of packet messages such that the station device
began sending a second message while the FIFO has data
from the first message.
Description of Input Message Controller
Each remote station device will input station messages
in a synchronized manner to maintain an in-frame sync
state. This is monitored in the input message controller
IMC 381 of each PLS which hunts for the alternating
polarity of the message sync (S) blt (first bit of a
station message) in the station input. When sync is
located, the station message bit counter count is adjusted
to coincide with it. Whenever the in-frame sync state is
lost, the IMC 381 will set a frame error flag (FE) (which
rnust be reset by the microprocessor) and automatically
enters a hunt-frame sync state until the in-frame sync
state is re-established. While hunting, the status bit
hunt (H) will be active and data transfers from the
associated station device are inhibited until the next
full frame after sync is re-established.
Desert ion of Additional Features_of QPLS
The QPLS also has the optional capability (not shown)
of making the current data outputs of the CRC checker
available as inputs to the microprocessor or other
external control means. If the received CRC read enable
bit (CR) is set, all PLS's in the QPLS operate in this
mode. The QPLS also has the capability of setting the
transmitter CRC read enable bit (CS) whlch will transmit
the CRC data to the station device as the four-bit packet
information in each frame rather than the actual packet
data. These two modes are principally used for chip
testing and are not necessary for normal operation.
Loopback Mode and The Diagnostic Channels
The QPLS also has two independent diagnostic channels;
one, ICOD 503, for reading from information highway inputs
-so-
274, and the other, ICID 501, for writing to the
information highway outputs 272. The diagnostic channels
are shown in Figures 12 and 16 and have been briefly
described above. The operation mode of the diagnostic
channels is controlled by status bit, L4, which selects
either t'ne normal (L4 reset (0)) or the loopbac'~ (L4 set
(1)) mode. In both modes, the diagnostic output channel
(ICOD 503) ,reads data from the selected channel of a
selected information highway input 274 into an eight-bit
s'nift register 519 (Figure 16) in the manner previously
described for ICO1 3~6, utilizing the same timing. The
information highway input 274 is selected by multiplexer
517 under control of register 513 and comparator 515. The
data is loaded from the information highway shift register
519 into register 593 on the occurrence of the frame sync
signal on FSI 276. The data stored in register 593 may be
read by the microprocessor via the QPLS parallel port.
The diagnostic input channel (ICID 501) writes data to
the selected channel of the selected information highway
output 272 in the manner as described for ICI1 382,
utilizing the same timing. The source of the data to be
written to the highway is controlled by the selected
mode. In the normal mode, data stored in register 596 by
the microprocessor through the control interface logic 591
(shown in Figure 14) is transferred through multiplexer
595 to shift register 509 at the occurrence of an active
signal on FSO 280 in each frame. The data in shift
register 509 is shifted through demultiplexer 511 to the
information highway outputs 272 under control of register
50S and comparator 507.
In the loopback mode, the data stored in register 593
is transferred through multiplexer 595 to shift register
509 at the occuxrence of the signal on FSO 280 in each
frame. The data in shift register 509 is shifted through
demultiplexer 511 to the information highway outputs 272
under control of register 505 and comparator 507.
9~
Interlace Logic and Address Assignments
The QPLS also contains random interface Logic, shorm
on the block diagram in Figure 14 as control interface
logic 591, which receives address, data, read/write
control and a strobe from the microprocessor, and
generates the internal control signals which cause the
microprocessor data to be routed to the various internal
registers. This is accomplished by activating select
signals to the multiplexers shown in the block diagrams.
The QPLS I/0 address assignments are shown in the QPLS I/0
Address Assignment Table. As will be a?parent to those
skilled in the art, various address assignments may be
used without departing from the scope of the invention.
; The address assignments set forth below and in the QPLS
I/0 Address Assignment Table in hexadecimal format are
thus only exemplary ox the preferred embodiment of the
inventionO The control interface logic 591 also contains
frequency conversion logic for developing the clocking
required by the shift registers and other logic by
deriving clocks at various rates from the line clock input
on LC 288 and from the outputs of the biphase mark
decoders 461.
.
QPLS I/0 ADDRESS ASSIGNMENT TABLE
Address (HEX) READ WRITE
00 Packet data in 0 Packet data out 0 *3
01 Packet status 0 *1 Reset PF0
02 Packet data in 1 Packet data out 1 *3
30 03 Packet status 1 Reset PF1
04 Packet data in 2 Packet data out 2 *3
; 05 Packet status 2 *1 Reset PF2
06 Packet data in 3 Packet data out 3 *3
07 Packet status 3 l Reset PF3
08 Interrupt Status (I3-I0, D3-D0) Packet status Reset *4
09 QPLS Status (V5-0, EF, SA)- -
-92-
OA Mode-L (O,O,N,L4-0) Mode-L Same as READ
OB Mode-H *2 Mode-H Same as READ
OC HDW REG SAME AS READ
OD HDR REG - -
5 OE DIAG CHAN REG OUT SAME AS READ
OF DIAG CHAN REG IN SAME AS READ
10 PLSO CHAN REG O out Same as READ
11 PLSO CHAN REG O in Same as READ
12 PLSO CHAN REG 1 out Same as READ
10 13 PLSO CHAN REG 1 in Same as READ
14 PLS1 CHAN REG O out Same as READ
15 PLS1 CHAN REG O in Same as READ
16 PLS1 CHAN REG 1 out Same as READ
17 PLS1 CHAN REG 1 in Same as READ
18 PLS2 CHAN REG O out Same as READ
19 PLS2 CHAN REG O in Same as READ
1A PLS2 CHAN REG 1 out Same as READ
1B PLS2 CHAN REG 1 in Same as READ
1C PLS3 CHAN REG O out Same as READ
20 1D PLS3 CHAN REG O in Same as READ
1E PLS3 CHAN REG 1 out Same as READ
1F PLS3 CHAN REG 1 in Same as READ
*1 (FE,H,OR,C,OE,PB,FF,E)
*2 {S1,SO,CI,B,CS,CR,R1,RO)
*3 sets associated PF flag
*4 (3-0) resets FE, OR, C, E in the selected PLS's
:
-93-
FE= Frame Error I=Interrupt
H= Hunting D- Data available
OR=Overrun V= Version number
C= C2C error EF= Even frame
5 OE= Output empty SA= Second address
PB= Packet busy N= Local mode
FF= FIFO Full L= Loopback
E= End of message S= Highway data rate
CI= Chip initialize B= Line buffer bypass
l CS= CRC send data CR= CRC receive
R= Rate select HDW= Highway Data Write
HDR= Highway Data Read
out= data transferred from QPLS to external device/PCB
logic
in= data transferred from external device/PCB logic to
QPLS
Addresses 00 through 07 are used to access the packet
channel logic. For example, Packet Data In 0 which is
read from the QPLS when the microprocessor imposes address
00 in the address lines, is the data on the output of the
six-byte FIFO 349 in PLS0. Similarly, Packet Data Out 0
is that data which may be written into the packet channel
output register to be sent to the device connected to the
station port for PLS0. When the microprocessor writes to
address 00, it also sets the packet flag (PF) for PLS0.
The packet flag is reset by executing a write to the
address 01.
If the microprocessor reads from address 01, it
receives the packet channel status for PLS0. The format
of the packet channel status received may be as follows:
FE H OR C OE PB FF E
-94-
FE status bit is used to indicate that the packet channel
input logic has previously received a frame error on t'ne
data input. The H status bit is used to indicate that the
packet channel input logic is in the hunt-frame sync
state. The OR status bit is the FIFO overrun indicator.
The C status bit is the CRC error indicator OE is the
output empty status bit which indicates to the
microprocessor that the next byte of packet data can be
loaded. PB is the packet channel busy status bit which
indicates that packet data message has been initiated by
the microprocessor. It remains set until after the packet
flag is reset by the microprocessor and all CRC data has
been transmitted. FF is the FIFO full status bit. E is
the end of message status bit which indicates that the
packet in control logic 392 has detected the end of the
message from the device connected to the station port. H,
OE, and PB are self-clearing when the associated condition
has been cleared. H will reset (0) when the in-frame sync
state is true. OE will reset (0) when a byte of data is
loaded into PCO 390 by the microprocessor, and will set
(1) after the loaded packet data has been transmitted to
the device connected to the station port. PB will reset
after the CRC data of the current message has been sent to
the station port. FF is reset (0) by performing a read
from its associated FIFO addressO E, OR and C are reset
(0) by writing to the packet status reset address. FE
requires a write to the packet status reset address after
H has been reset and the PLS is in in-frame sync. The
packet status reset address uses only the lower four bits
of the data to that address. Data bit 0 resets the status
of PLS0, data bit 1 resets the status in PLSl, data bit 2
resets the status of PLS2 and data bit 3 resets the status
in PLS3~
If the microprocessor reads from address 09, the QPLS
- 35 transmits status to the microprocessor. T'ne six most
significant bits of the data transmitted will contain the
-95-
version number of the QPLS. This version number i3 a
six-bit binary number which can be part of the mask which
creates the integrated circuit. Typically, it will be
used to comrnunicate the particular revision number of the
unit to the microprocessor 23 and can be used by the
microprocessor to select the appropriate software to be
used to control each version of the QPLS.
The least significant bit of the QPLS status is the
status of the second address (SA) which may be used to
determine which byte (upper byte or lower byte) is being
addressed when accessing addresses OE through 1F, the
eighteen 16-bit channel registers. SA is reset (O) by
activating the chip initialize input (CI) 412. Since the
channel registers contain sixteen bits of information, and
since the microprocessor data is typically transferred in
groups of eight bits, two accesses to a register are
typically required to transfer data between the channel
registers and the microprocessor.
The next least significant bit, EF, is the even frame
status bit. This bit is forced to the even frame state
when the QPLS initialize mode bit is set, and will toggle
upon receipt of each signal on the information highway
frame sync output (FSI) 276 after the initialize mode bit
is reset. This will enable multiple QPLS En bits to be
set to the same state.
A write to address OA sets the bits in mode-L
register, which is random logic contained within the
control interface logic 591 (shown in Figure 14). The
mode bits, which control functions within the QPLS, are as
follows:
O O N L4 L3 L2 L1 LO
The two most significant bits of the mode register
controlled by this address are not used. Bit 5, N, is the
local/remote mode selectO When set the QPLS is typically
-96-
in the local mode. When reset, the QPLS is typically in
the remote mode Bit 4, L4, controls the diagnostic
channel. When set, the diagnostic channel is in the
loopback operation which has been described above. The
four least significant bits L3, L2, L1, LO control the
normal and loopback operation for each of t'ne
corresponding PLS's. When the corresponding bit is set,
the PLS associated with that bit will be in the loopback
mode as described above. When the bit is not set, the
corresponding PLS wily be in the normal mode. The current
contents of this mode register can be determined by
reading from the same address. In the present embodiment,
a signal on chip initialize sets each of the loopback
; bits, L4, L3, L2, L1, LO, to their active states, and bit
N to the remote state.
A write command to address OB sets certain status bits
in the mode-H register. The format for the data bits in
this register is as follows:
S1 SO CI B CS CR R1 RO
The most significant two bits, S1 and SO, are the
highway data rate selection bits. Station port clock
synchronization for proper transfer of data between
station port shift registers and information channel shift
registers typically requires the setting of the S1 and SO
bits to match the highway data rate reference clock (HIC)
278. Typical settings are as follows:
3~ Sl SO Highway Data Rate
O 0 2048 kbps (256 bits per frame)
0 1 4096 kbps (512 bits per frame)
1 1 8192 kbps (1024 bits per frame)
The third most significant bit, CI, is the chip
initialize/normal bit. When this bit is active, highway
-97-
output drivers are inhibited. The highway input station
port input shift registers are therefore forced to load
fill bits and the station port output lines are clamped to
a constan-t "1" state. The chip initialize i5 active
following power on conditions and whenever changes are
performed in data rate configuration selection. In the
later case, the chip initialize will prevent data from
being transmitted to remote station devices or to the
highways until the reconfiguration is completed.
Initialize mode also resets the QPLS interrupt to prevent
further interrupts from occurring and forces the EF status
bit to the e-ven frame state. When chip initialize is
placed back in the normal state, all information channels
will typically continue to be disabled until the
occurrence of the next frame sync signal. The status bits
in mode-L register and mode-H register are initialized to
known states by the chip initialize signal.
The chip initialize/normal mode bit operates similarly
to the QPLS input pin (CI) which is activated at power-on
time or when specifically set by the external circuitry.
The QPLS chip initialize input pin also forces certain
mode selections which assist in QPLS testing as follows:
the four station ports are placed in the loopback mode and
in the high data rate (i.e., the four PLS's are
interconnected); the receive CRC read and the transmit C2C
read are disabled; the line buffer bypass is placed in the
normal mode; the QPLS chip initialize/normal status bit is
placed in the initialize mode, which will operate as
described above; the remote/local mode select is placed in
the remote mode; and the highway data rate selection is in
the low speed mode, i.e., 2048 kbps (256 bits per
frame). The chip initialize state will remain set until
specifically reset by resetting the CI bit in the mode H
register via the parallel port.
The fourth most significant bit in the mode-H register
is the line buffer bypass bit, B, which typically causes
buffers 371 and 359 to be bypassed in the local mode.
:
-98-
The fifth most significant bit, CS, is the transmit
CRC enable bit. When set, the transmit CRC shift register
data is typically sent as packet data to the station
port.
The sixth most significant bit, CR, is the receive CRC
read enable bit which typically is set to allow the
microprocessor to read the current output of the packet
channel input CRC circuitry rather than the packet data.
The least significant two bits, R1 and R0 are the
station port data rate selection bits. When R1 and RG are
both reset, the normal data rate is typically selected and
,~ the four station ports are configured as four independent
units. When R1 is not set and R0 is set, the station
ports Jay be configured as two units with PLS3 connected
to PLS2 and PLS1 connected to PLS0 and the PLS's operate
at the medium data rate. When R1 and R0 are both set, the
four PLS's may be connected as one unit with PLS3
connected to PLS2, with PLS2 connected tG PLS1, and PLS1
connected to PLS0, and the PLS's thus operating at the
high data rate. The fourth state, R1 set and R0 reset,
may be used to support other implementations as the
particular application requires. The data rate selection
is summarized as follows:
R1 R0 Station Port Data Rate
_
~5 0 0 Normal
0 1 Medium
1 1 High
Address OC is the highway data write register in the
diagnostic channel input (ICID 501) which is used by the
microprocessor to write data to the selected information
highway input 274 when the diagnostic channel is
enabled. This register can be read by the microprocessor
by using the same address.
If the microprocessor executes a read command on
address OD it receives the information in the hignway data
g
_99_
read register 519 in the diagnostic channel output (ICOD
503). The information will be in-formation selected by the
diagnostic channel from an information highway input 274.
Addresses OE and OF access the diagnostic channel
control registers ICOD and ICID and addresses 10 through
1F access the PLS channel registers as shown on the QPLS
I/O Assignment Table. Addresses OE-OF and 10-1F can be
written to by the microprocessor, and can be read by the
mlcroprocessor to verify their current contents.
Of npLs Operation
. _
As one of ordinary skill in the art will readily
recognize, the structure and functions of the QPLS,
described in connection with the previous drawings, may be
implemented by various alternative arrangements of the
logic elements. Although such equivalent detailed
implementations may be used, as a matter of design choice,
the particular arrangement of elements implemented in the
presently preferrer embodiment is set forth in Figures 21
through 41 in the interest of total disclosure of the
present inventionO
Figure 21 is a reference table for the pin numbers and
pads on the QPLS. Figure 22 includes the logic diagram
for the information channel out (386~388), (from station
port), illustrated more generally at Figure 13(a). The
circled numbers appearing in Figures 22-34 and 54-64 are
references to Figure numbers where the input or output
signals adjacent to the circled numbers find further
description. The HIRC 0-9 signals entering the vertical
array of OR gates to the right of the 16-bit register are
from the highway in reference counter 223 illustrated at
Figure 13(a). When the data stored in the 16-bit register
is equal to the ~IRC 0-9 information, the compare line
(CMPR) is enabled which disables the write inhibit
flip-flop (WRINH F/F) and enables the HIC clock to clock
in information to the highway in shift register network
-l oo-
comprising the serial shift registers at the lower portion
of the page. Information to the highway in shift register
network is provided on 2HYWI7-0 at the lower left corner
of the figure, are the highway select multiplexer which is
set for the appropriate highway by the 16-bit input shift
register. Information from the highway in shift register
is communicated to the 8-bit line out shift register,
shown directly above the highway in shift register, where
it is communicated to the packet channel output, as shown
a Figure 13A. Eight of the channels of the PLS will
include the line out shift register as shown in the lower
dashed box. By contrast, the diagnostic channel will
replace the line out shift register with the storage
register shown in the upper dashed box. The data
communicated to the storage register of the diagnostic
channel output 503 is clocked into the storage register by
the FSI signal and is output back onto the highways via
the D~D7-0 line. The diagnostic channel storage register
may be accessed by the microprocessor network via a
tri-state driver, shown above the storage register.
The output of the line out shif-t register may be
communicated to the packet channel channel out,
information channel output 0, or the output logic
control. As can be seen by comparison to Figure 12, the
output selection depends upon whether the QPLS stays in
the local or remote mode. Moreover, depending upon the
configuration of the QPLS, i.e. low speed, medium speed or
high speed, the output logic control may either output to
the local station or be looped back to the input of the
next PLS. In the higher speed mode, the input to the line
out shiEt register will come from the OLC, as shown on the
left ox the line out shift register.
Figure 23 illustrates the logic for the information
channel in (382,3~4) (from station port), shown in Figures
12 and 13(b). The 16-bit shift register and comparator
network, set by HORC 0-9, functions similarly to the input
-1 01 -
circuit previously described in connection wit'n tne
information channel out circuit. The output from the
highway output reference counter (HORC) sets the
comparator network to enable a compare t'ne compare line
when the input signal corresponds to that setting. The
write inhibit flip-flop (WRINX F/F) also functions
similarly to the write inhibit flip-flop in the
information channel out circuit.
Data from the station device enters the circuit from
the ILC 387 through the 8-bit line input shift register
shown in the upper central portion of Figure 23. The data
from the ILC 387, or from the ICI 1 272 of the previous
per line switch, if in a higher speed configuration, is
clocked into the 8~bit shift regis-ter by the signal 3SCRI,
where it remains until the end of the frame. At the end
of the frame, the SO signal goes low to provide a load
signal. The information from the ILC 387, or ICI 1, 272,
is shifted through a line input buffer into an 8-bit D
shift register, located in the central portion of the
igure. When the comparator signal is true, the
information in the lower 8-bit shift register will pass
through a demultiplexer, at the lower right hand portion
of the figure, for output to the information highways. As
long as the compare signal remains true, the clock signal
HOC can drive the input signal through the lower 8-bit
shift register and out to the highways through the
demultiplexer.
The dashed enclosure to the right of the figure
represents diagnostic input circuitry 501 that may be used
to replace the line input shift register and line input
buffer shift register shown in the dashed box to tne
left. The alternative circuit provides the ability to
receive external data from the DBA 7-0 connection and
store that data in the highway data write shift
register Upon receiving a compare signal, the
information in the highway data write shift register can
L9
-102-
be communicated to the highways via the multiplexer, shot"n
directly belowO The DRD 7-0 input to the multiplexer
comes from the diagnostic channel and provides the ability
to put diagnostic data onto the highway or to take data
from one highway and transfer it to another highway.
The output of the write inhibit flip-flop is also
communicated to a NOR gate which also receives an HPS
signal. The output ox the NOR gate serves to force the
8-bit shift buffer to transfer all ones through the system
until a compare signal is enabled. This prevents t'ne
passage of spurious data through the system when a compare
signal is not present.
Figure 24 illustrates the logic of the packet channel
out (PCO) circuit 390. This circuit permits the passage
of data and control information to the station port. Data
enters the packet channel out circuit 390 via the ICO/O
line, shown in the bottom right hand portion of the
figure, and is transmitted through two 4-bit line shift
registers and the 2-bit multiplexer network for
communication to the biphase mark encoder circuit (BME)
393. depending upon which PLS channel is being
considered, the dashed box marked PLS O is replaced by the
alternative dashed boxes, marked PLS 3,1 and PLS 2, to the
right of the figure. In different data speed
configurations, a plurality of PLS channels may be
interconnected as previously described. In the higher
speed configurations, only one PLS of the serial group
need serve as master for purposes of biphase mark
encoding. The illustrated larger circuitry permits bypass
of the biphase mark encoding and output logic control in
the server PLS's, when configured for higher data rates.
When a message is written into the packet out channel,
the SR latch, on the upper left portion of the figure, the
S-1 and S-2 flip-flops in the upper left portion of the
figure, and the output (OE) flip-~lop are enabled. Data
is loaded into the input 8-bit shift register, shown in
Jo
-103-
the lower leEt portion of the figure. The input signal
stored in the 8-bit input register is passed through an
adjacent idle multiplexer to a 10-bit latch. A 4-bit
multiplexer to the right of the 10-bit latch will
sequentially select two nibbles for communication to the G
shift line register to the right.
As information is stored in the 10-bit latch, the PFX
flag is forced low, indicating to the shift register in
the output circuit that valid packet data is being
communicated from the 4-bit multiplexer connected to the
10-bit latch. The CRC generator 337, shown in more detail
at Figure 26, receives input from the line shift register
when output empty (Ox) enables the CRC shift in register
(CRC SI). The CRC generator 397 shifts information out
when the SR latch is disahled by one of the write/read
lines, thus forcing the output empty (OE) signal high and
enabling the CRC output flip-flop. The CP~C output
flip-flop enables the multiplexer below the CRC generator
to select the FCO signal to clock information into the CRC
generator. CRC information is interjected into the output
stream so as to form a 4-bit window that does not
interfere with the ICO 1 and ICO 2 signal clocked to the
output.
The K-bit oE the 10-bit latch is a fill bit which
forces all ones through the system, to prevent spurious
signals when data is not loaded into the input shift
register. The pacl~et busy (PB) flag, shown at the upper
central portion of the figure, provides an indication to
the outside world that the packet channel message is
started.
Figure 25 illustrates the packet channel in (PCI)
logic 385, shown more generally at Figure 13(b). This
circuit enables communication control messages from the
station device to the node processors. The 8-bit input
shift register at the upper left hand portion of the
figure receives in-formation from ICI0 and communicates
-104-
that information to the input message control 381, or the
input logic control 387 when the PLS is in a higher speed
configuration. The information in the input shift
register is tapped at bits Q2 and Q7 which correspond to
the packet flag bit and K-bit respectively. When the
packet flag bit is low, the packet flag (PF) flip-flop, in
the lower left portion of figure, will be turned on. The
four following bits of data will then be shifted otlt of
the input shift register at the Q2 port, and input into
the two-bit multiplexer, clocked by the OCRI~ signal.
Information is then transferred to an 8-bit byte
assembling shift register, which is clocked by the PDC
signal. Subsequent input from the Q2 port is communicated
to the byte flip-flop, in the lower portion of the
figure. The output from the byte flip-flop is
communicated to a packet status OR gate which enables the
; overrun flip-flop and FIFO flip-flop to output information
regarding the status of the packet channel. The output of
the byte flip-flop also enables the data storage OR gate
to clock information from the byte assembling shift
register into the D storage flip-flop, number 6. Once
information is stored in the D storage flip-flop, the
signal is communicated to the JK flip-flop network which
ripples the signal to the right where it ultimately sets
the D flag to indicate that packet information is stored
in the flip-flop. Each successive byte of information
moves along the D storage flip-flop to the Dl flip-flop to
the right, from which it may be accessed by the node
processors 77, 25 via the state driver. The rightmost JK
flip-flop maintains the D flag on until a read is
performed on RD00,02,04,06, connected to the tri state
driver, which also turns off the rightmost JK flip-flop.
The output from the Dl flip-flop is communicated to a
tri-state driver, which drives the internal data bus so
that the external world can read the data. If 4 bytes are
stored in the D storage units, the signal on the Q port on
-105-
the JK flip-flop number 4 will communicate a signal to the
FIFO full flip-flop, shown in the upper rig'nt portion of
the figure. The FIFO full flip-flop will generate a FIFO
full flag, which in turn will generate an interrupt
indicating that the storage unit is full. Actually, only
five storage units are full at that time, however, the
flag allows sufficient response time for the
microprocessor before an overrun condition occurs, as
indicated by the overrun flip-flop, located in the upper
central portion of the figure. The overrun flag may also
be set by the output of the E flip-flop, in the center of
the figure, indicating the end of message. The end of
message flag indicates that packet flag has become
inactive and the message is completed. The E flip-flop
generates an interrupt signal via the interrupt OR gate
connected also to the FIFO full flip-flop.
The CRC status register, shown in more detail at
Figure 26, is enabled by the same signal that enables the
end of message register. At the end of -the message, the
output from the E pin of the CRC generator 353, on the
upper left portion of the figure, is communicated to the
CRC status register. If the (E) output is not a zero, the
CRC status register will indicate that something is wrong
with the data that has been communicated.
The K-bit is sampled from the Q7 port of the input
shift register. The K-bit is communicated to the K
flip-flop, in the lower left hand portion of the Eigure.
When the K-bit goes to a zero, it will inhibit the clock
passing through the packet status comparator and the data
storage comparator. The K-bit may also inhibit the packet
data clock (PDC) from clocking the CRC generator or the
byte assembling shift register. The CRM input signal is
communicated to the two-bit multiplexer and will shiEt
that multiplexer from passing data from the input s'nift
register to passing data that is in the C~C generator
353. This permits monitoring the activity in the CRC
generator for diagnostic purposes.
-106-
Figure 26 illustrates the CRC circuit, 353, referenced
earlier in Figures 24 and 25. In the presently preferred
embodiment, each PLS includes eight CRC circuits on the
QPLS chip. The preset version ox the CRC circuit uses the
standard CCITT polynomial, X16 + X12 + X5 + 1. MSI chips
that perform the same polynomial are commercially
available from a variety of sources. The "A" portion of
the CRC circuit, above the dashed line, is used in the
packet channel out circuit, which does not need the
checking circuitry, "B", located below the line. The PCI
circuits all incorporates both A and B portions. To enter
data into the D input, the G input must be high. That
will allow data to pass through the exclusive OR circuits
and be shifted in the three 16-bit shift registers. Data
is output from the CRC circuit at Q. For CRC checking,
the signal on the P input sets all of the Q flags at 1 to
cause the E circuit to go low if the circuits are
operating properly.
Figure 27 illustrates the logic of the output line
control (OLC). The output line control circuit for each
PLS is shown in the figure. Each circuit includes a
multiplexer which selects an appropriate input depending
upon the mode of operation, i.e. local or remote, and the
data speed configuration, as previously described in
connection with Figure 12. Inhibit signals are
communicated to OR gates and may prevent transmission of a
line out signal during chip initialize time, ar.d during
other diagnostic functions where it is desirable that the
external device does not receive the test data stream.
The output may also be inhibited during high data rate
modes during whichoutput may be input to the next lower
PLS. As previously noted, signal may also inhibit the
output of all PLS's except PLS0 will output a signal in
any data rate configuration. The N`l~ signal to the
multiplexers bipasses the biphase mark encoding logic to
permit output of NR~ data instead of biphase mark encoded
data to the station device in the local mode.
-107-
Figure 28 includes the logic for the line in control
circuit. The purpose ox the line in control logic i5
similar to that of the line out control logic. The line
in logic decides what data to send to the QPLS. In low
speed mode (not loopback) the line in data will go to the
particular PLS line in registers. In a remote mode, the
input will go to the biphase mark decoder prior to going
to the line in shift registers, where it can be decoded
back into NRZ data and extracted clock. The rate mode
signal similarly configures the PLS connections in one,
two, or four serial circuits as previously described in
connection with Figure 12. In the high speed mode, data
on the line input, LI O of PLS 0, comes into the upper
left multiplexer from which it is communicated to biphase
mark decoder O (BHDO), as can be seen in connection with
Figure 12. The data from the biphase mark decoder is then
returned to the PLS O channel through the multiplexer
immediately below. In a high speed mode, the output from
the BMD O multiplexer is communicated to the PLS 3 channel
~0 (lower right), where it is transferred to the PLS 3 ICI
1. The data then shifts through PLS 3, to the PLS 2 input
(from PLS 3, ICI 0), where it is input into a multiplexer
network and is communicated to PLS 27 ICI 1. The signal
i5 then communicated to PLS 2 (upper right) where it is
again transmitted through two multiplexers to be
communicated to PLS 1, ICI 1. The resulting signal is
then communicated back to PLS O (upper left) from PLS 1,
ICI 0, where it is communicated through two multiplexers
and then goes through PLS 0, ICI 1. In the local mode,
the data will be similarly communicated except that the
biphase mark decoder circuit 461 will be bipassed by the
signal NM applied to the biphase mark decoder multiplexer.
Figure 29 illustrates the logic diagrams for the
station line clock rate generation and selection circuit
in the control Interface Logic 595, shown generally at
Figure 14. In the lower left hand portion of the Figure
~L2~1
- 1 08 -
is the multiplexer network that selects the source for the
; line buffer transfer clock signals (LBXC) for each PLS~
The upper left hand circuit is the multiplexer circuit
that selects the decoded shift register clock in for eac'n
PLSo The upper center of the Figure is the multiplexer
circuit that selects the packet data clock (PDC) froM
whatever PLS is supplying that signal. The remaining
portion of the Figure is the line rate clock generator and
selection circuit for the signals SCRO, LIC and CLK3
10The shift register clock output (SRCO) is derived at
the output of the Y multiplexer at the right hand side of
the Figure. The double shift register clock out (DSRCO)
and the line in clock (LIC) are derived from t'ne same
logic. The SRCO signal provides the basic rate of the
; 15output line and would, in the remote mode! run at 192, 384
or 76~ kHz, depending upon the data rate configuration.
In the local mode the SRC clock would run at 128, 256 or
512 kHz. The double shift register clock out runs at
twice the frequency of the SRCO clock in the remote and is
~0 used to decode the ~RZ data to develop the biphase encoded
data to be sent out to the station device. The line input
clock runs at eight times the SRCO rate and is used to
decode the biphase mark encoded data being received from
the station device. The clock 3 signal (CLK 3) runs at a
2~ constant 3 megahertz in the remote mode and is used to
drive the packet channel in FIFO.
The 6-bit counter is synchronized with the frames and
provides outputs for a full frame sync pulse at 4
megahertz and 8 megahertz, and for a half frame sync pulse
operation on the highways. The counter is reset at the
trailing edge of the FSID signal, regardless of the
particular data rate.
The LC clock clocks the D flip-flop, to the left oE
the 6-bit synchronous counter, such that its Q output
passes through the multiplexer to clear the 6-bit
counter. In the remote mode frame sync is occurring at
~3 2~f2
-1 09-
either 2, 4, or 8 megahertz and the frame sync must occur
at a different time. The tables on the lower portion of
the Figure illustrate the signals on the inputs to the
respective multiplexers and indicate what inputs are
selected in each mode In the remote mode, at megahertz
operation, the Y multiplexers in the lower portion of the
Figure will have a 1 on the SM0 and SMl pins. The input
to the multiplexers is from the 1 pin, which is from the
FSIL signal in the first multiplexer and is the output
from the 2 input D multiplexer, in the second
multiplexer. The right portion of the table indicates the
state of the NM pin on the multiplexer adjacent the 6-bit
synchronous counter. As can be seen from the table, when
NM is 1 the system is operating in the local mode and
therefore it doesn't matter what the previous multiplexers
are set to because their rates do not affect the highway
rate which is being applied to the counter via the frame
sync in delayed signal (FSID). The next table to the
right indicates the RM 1 and RM 0 values in the various
data rate configurations. The rightmost table indicates
the SMl, NM and S~0 values, and the inputs selected for
the remote and various local modes.
Figure 30 illustrates the various timing logic
required by the QPLS circuitry to generate various timing
signals. The highway in reverence counter (HIRC) is
clocked by the HIC clock and is cleared by the frame sync
in delayed signal (FSID). The highway output reference
clock (HORC) is clocked by the highway output clock (HOC)
after being cleared by the signal frame sync out early
(FSOE) signal. Those signals are provided externally from
the QPLS chip and allow the reference counters to keep in
step with frame timing.
The counter that develops the FSOE signal is shown in
the upper left portion of the Figure. The FSOE signal i3
derived from the externally supplied signals frame sync
out (FSO) and highway out clock (HOC). us FS0 goes high
- 1 1 o -
the output of the multiplexer will go high. A half a bit
later, the signal HOC will clock the D flip-flop to go 10~J
and terminate the frame sync out early pulse.
The interrupt control logic produces an interrupt
whenever inhibited by the chip initialize signal or the NM
local bit. Additionally, an interrupt may come from the
packet channel input of each of the PLS's. The interrupt
signal is communicated from the chip via an open collector
driver.
The highway in timing circuitry generates timing
signals that facilitate operation of the packet channel
output and packet channel input. The FSI input signal is
provided from the external world and clocks the upper
flip-flop as long as the chip initialize signal (CI) is
not present. The upper flip-flop will output an even
frame signal (EF) that is used to generate the frame
holding register clock (FRHC). Every other FSI pulse
passes through the flip-flop and generate EF signal. FHRC
is generated when EF is low and is used to load the data
in the PCI output register into the holding register and
also sample the data status flip-flops.
Frame sync in delayed (FSID) and frame sync in late
(FSIL) is generated by the lower flip-flop. HIC clocks
the FSI signal through the lower flip-flop to produce an
2S output that is the same width as FSI, but delayed one-half
a bit. That signal is labelled FSID. FSID is produced
when the FSI signal and the Q output from the flip-flop
are both positive. The PCO, CRC clock generator circuit
clocks FSID and SCRO signals. A 3-bit counter is provided
that clocks in accordance with SCRO and produces an output
signal which is -then inverted, labelled FCW. That signal
is fed back to the input of the OR gate which stabilizes
the 3-'oit counter. Once every frame a FSID pulse reset
the counter. The FSID pulse maintains the counter on as
it forces the FCI signal to remain high. FSID also forces
the Q output of the D flip-flop to remain high. Upon the
.
~2~
end of the FSID pulse the flip-flop will be driven by the
clock to produce 4 FCI clocks and 4 FCO clocks.
The highway resync register is illustrated in the
center of the Flgure. Each output from the 8-bit shift
register is connected to an open collector driver that
drives the outputs to the chip. The 8 highways, H~7 0-7
on the left side of the chip are the 8 output hig'nways
that are internal to the QPLS. Those highways are driven
by the ICI demultiplexers, as shown in Figures 22 and
lo 23(b). The 8-bit register is clocked by the highway
output clock (HOC), In the chip initialize mode the
register is preset to prevent output of transient signals.
The right side of the Figure illustrates the signal
inputs FSI, TIC, FSO, and HOC which are highway timing
signals. The Figure illustrates the input pads, buffers
and inverters for each of those signals. The lower
portion of the buffer section illustrates the highway
inputs KIWI 0-7 and their respective pads and buffers. The
output signals are directed to the multiplexers
illustrated in the lower left hand portion of Figure 22.
Figure 31 illustrates the mode and status logic in the
QPLS. The node registers and QPLS status register form a
portion of the control Interface Logic 595. The packet
status and interrupt status registers are a portion of t'ne
packet channel input 385. The register on the upper left
side of the Figure produces the local mode bit, NM. The
next lower register indicates the loopback mode (Lo). The
loopback mode register LM produces a loopback mode control
signal for each of the PLS's and for the diagnostic
circuitry (LM4). The next lower regis-ter 9RM is used to
indicate the remote mode for channel 0 and channel 1, and
the chip initialize mode. The lowest left side regis-ter C
is used to indicate the CRC read mode, the CRC send mode,
buffer mode, and the two highway selector modes, SM 0 and
SM 1.
-112-
In the lower center of the figure is circuitry
illustrating the input and output pads for OSRTP, ISRTP,
HIRC and HORC. The STRP signals allow testing of the
shift register in the line circuitry of all chips.
In the upper middle of the figure is the QPLS status
latch. The latch allows access to the status bit second
address (SA) and to even frame (EF), which is the state OL
the even frame flip-flop. The latch also allows access to
the difEerent portions of the QPLS to allow the software
to operate on that portion in a manner that it requires.
In the upper right side of the figure is the packet
status latch that allows access to the status bits
provided from the packet channel out (PCO) and the packet
channel in (PCI). The input message bits include output
empty (OE), FIFO full, packet busy (PB), output empty
(OE), CRC error (C), overrun error (OR), hunting (H), and
frame error (FE).
On the bottom of the page is the interrupt status
latch that allows access to the state of the D-flag and I
flag from the packet channel in circuit illustrated at
Figure 25. One bit is provided for each PLS. The I-bit
is active whenever the message flag is on or the FIFO full
flag is on. When the I-flag is on, the external device
will read the interrupt status latch to determine what PLS
generated the interrupt. The ex-ternal device may
determine that more than one interrupt flag is interrupted
and can read the appropriate FIFO until the D-flag becomes
inactive. At that point, the FIFO is empty and the
external device can proceed to the next interrupt to
3~ repeat the process.
Figure 32 illustrates the bi-phase mark decoder 461
and bi-phase mark encoder logic 393. In the bi-phase mark
encoder logic the JK flip-flop is initialized by the
signal 3CI, which is useful in testing the chip. The
state of the JK flip-flop is not used to determine the
particular state of the input. The relevance of the JK
-ll3-
flip-flop is to note the point at which the input changes
state. The input to the JK flip-flop is received from the
OR-gate which is input by the packet channel out (PCO) and
the shift register clock out (SRCO)o That data is then
clocked by the double shift register clock out signal
(DSRCO). The JK flip-flop will change state at least once
per shift register clock out. The data out will appear to
the output line control as the shift register clock out
delayed by a quarter bit.
In the bi-phase mark decoder circuit 46l, on the left
side of the figure, data from the input logic control is
applied to the first of two D flip-flops. The D
flip-flops are clocked by the line in-clock (LIC) which is
running at eight times the data ratè appearing at the
ILC. The exclusive OR circuit connected to the flip-flop
outputs provides an edge detector signal (EC) that
identifies state changes at the ILC. Every time a clock
edge is detected, the first flip flop will change state.
The exclusive OR will also change state producing an edge
clock so that it goes low whenever the two flip-flops do
not contain the same data. On the next clock, the second
1ip-flop will follow, or copy the first flip-flop state,
which will remove the clock. Thus, the output from the
exclusive OR is referred to as the edge clock (EC). When
the edge clock goes low it resets the 3-bit ripple
counter. The edge clock will also reset the bi-phase mark
mising detector flip-flop in the upper portion of the
figure and will go low on the input of the SCRI flip-flop7
which produces the extracted clock signal shift register
clock it (SC~I). One LIC clock pulse later, the EC pulse
will go inactive. That action will cause the SCRI
flip-flop to change states producing a clock edge. Also,
the 3-'oit counter can begin counting. A subsequent ILC
pulse resets the 3-bit ripple count before it normally
completes counting, thus preventing the 3 input NADD-gate
from passing a reset signal (MAX clock) to the SRCI
8 9
-114-
flip-flop. If there is no ILC signal transition before
the 3-bit ripple counter completes counting, a MAX clock
signal will be generated from the 3-input NAND-gate which
will force the SCRI signal high.
extracted data from the ILC 387 is output as NRZ data
from the NR~ flip-flop and communicated to the IMC end
ILC. The NRZ flip-flop is clocked by at 3 SRCI, which is
a delayed SRCI signal. One feature of the decoder design
is that it automatically corrects for possible phase
errors in the extracted data. If the bi-phase data is out
of phase with the clocking signal a circuit will
automatically correct it.
The bi-phase mark missing detector circuit notifies
the external data controller when no data is being
received from an external source. If clock edges are
continually being received, or if at least one clock edge
is received between every frame sync, the bi-phase mark
missing detector flip-flop will always be reset and will
never be able to drive the signal FH. If no transitions
are received iII the input line for two frame syncs then
the flip-flop will come on on the first FSO signal and the
NAND-gate will be inhibited. If no clock edges have
occurred by the next FSO signal, then FH will be forced to
be true and will stay true until the edge clock occurs
~5 again. The FH signal is communicated to the PCI status
logic and forces the status bit frame error in hunt
signals to be true.
Figure 33 illustrates the input message control (IMC)
logic 381, shown more generally at Figure 13(b). This
~0 circuit functions to search out and locate the message
synchronization. Three different versions are
illustrated. The circuit in the dashed box in the upper
center of the figure may be replaced by the two circuits
on the lower left and lower right hand portions of the
figure. The embodiment illustrated in the principal
figure includes a 5-bit counter which counts from zero to
-115-
23. The alternative embodiments, which accommodate
different data rates, include the 6-bit counter, on the
lower right hand side, which counts to 47, and the 7-bit
counter on the lower left sideJ which counts to 9~. The
circuit operates to compare the BMD and PCI signals a the
exclusive OR-gate in the upper left portion of the figure
to see if there synchronization bits are in an alternating
state. If the synchronization bits are opposite,
indicating proper synchronization, then the hunt (H)
flip-flop will not get reset and the H signal will not go
active. When the hunt flip-flop is reset, a signal is
sent to the frame error (FE) flip-flop which indicates the
frame error condition. Once the frame error flag is
active it can only be reset by the PSRS signal from the
external processor. However, the hunt signal can go
inactive once synchroniæation occurs. The 5, 6 or 7-bit
counters function to time the BMD and PCI comparisons at
the proper moment in view of the data rate configuration
in which the QPLS is operating. The different counting
circuits are necessary to accommodate different data rate
configurations. The output LBXC is the line buffer
transfer clock, which represents the frame signals on the
highway side of the frame sync in and frame sync out
circuits, which may include a variable delay depending
upon the time that is involved in the circuit between the
remote device and the PLS. The PDC signals facilitate
shifting the line in data and the packet channel input
into the bit assembly register. Once a bit is there
assembled it is transferred to the FIFO, as previously
described.
Figure 34 illustrates the input/output control and
decode logic that form a portin of the control Interface
Logic 595. The figure contains the decode logic for all
the different addresses here utilized. Some addresses
require a single read or write to accomplish the operation
and others require two reads or two writes to accomplish
-116-
the operation. If an operation is going to be an 8-bit
operation, then it is completed in a single read or
write. Data enters the circuit in the upper left 'nand
portion of the figure (DAT 7-0) where it is communicated
to an I/O transceiver that determines what signal will
drive the internal data bus, or the external data bus.
The transceiver is controlled by the signals read/write
(R/W) and strobe (STB). The R/W signal sets the direction
and the STB signal enables the transceiver. When the R/W
signal is low, the data on the DAT lines will appear on
the DBA lines. The strobe signal then enables the
particular decode address that is applied. The decoder
logic is shown on the right side of the figure. The upper
decoder, RDOP, forms a read operation and the lower
decoder, WROC, performs a write operation. Those decoders
are controlled by the state of the addresses 0-4. E3 on
the 2-4 decoder is derived from the AD 1-4 inputs on the
; lower left side oE the figure. The other enabling inputs
on the decoders are STB and R/W. The two other decoders,
RD8F and WRIF, to the immediate left, decode the double
write and double read sequences. Those decoders utilize
an 8-bit data bus from the external world from an internal
16-bit data bus. To write to a 16-bit internal data bus
the address for that location is from the AD 1-4 inputs on
the lower left hand side of the figure, would be strobed
through the NAND-gate and communicated to the 2-4 decoder
in the lower portion of the figure. The address signal
also clocks the SA flip-flop at the lower portion of the
page which inputs to the 2-4 decoder. The 2-4 decoder
sets the 8-bit shift registers and 8-bit drivers in the
center of the figure to receive two bytes of 8-bit data
from the DBA inputs and clock that data simultaneously, in
a 16-bit group to the DBC and DBB lines. The output
sequence on the DBC and DBB lines is reversed for the read
and write operations.
-117-
On the left side of the figure are the AD0-AD4 input
buffers for the address lines. On the lower right side of
the figures is an inverter circuit that inverts the WR 8
signal that is communicated to the PCI to develop the
packet status reset signal.
Figures 35-40 are timing diagrams illustrating the
signals previously described in connection with the
earlier diagrams.
Figure 41 illustrates several timing paths in the QPLS
circuitry. Three simplified logic diagrams are presented,
the circuitry for which is shown in more detail in
connection with t'ne previous logic diagrams. In the upper
left portion of the figure, a critical timing path for the
signal HOC is illustrated. The heavier lines represent
the path that is assumed to be critical. In that path the
highway output clock (HOC) is input to a 10-bit counter
that is developing the HORC circuitry that goes into an
exclusive OR comparator, and through an inverter to enable
the clock shift register connected to FSOE. The slgnal
from the inverter also enables the demultiplexer to allow
data that is in the shift register to appear at the input
of the highway resync register one-half a bit after the
leading edge of the HOC clock. The trailing edge of the
HOC clock will clock that data into the highway
register. Therefore, the data must be valid at the
register input before the clock changes state.
The logic dia8ram illustrated at the lower left hand
portion of the figure illustrates a critical path for
accessing data from the highway. Data appearing at the
~0 highway inputs (HIWI) passes through a demultiplexer,
through an OR-gate into a shift register. The highway in
clock passes through an inverter, a counter, a colnparator,
enables an AND-gate that will allow the edge of the clock
to clock the data into the shift register before the
highway data has changed. Also, the SRCO signal must go
high within a half-bit time while the FSID slgnal is true,
~2
-118-
in order to load the data into the line out shift
- register.
The logic circuit for developing the SRCO signal at
the critical is shown in the right portion of the
figure. In that circuit, the line-in clock is
communicated to a counter which is cleared by a flip-flop
to allow the line-in clock to pass throug'n the
multiplexers and through an inverter to permit SRCO to go
high as necessary in connection with the previous
drawing.
While the principles of the QPLS have been described
above in connection with specific apparatus and
applications, it is understood that this description is
made by way of example only and not as a limitation on the
scope of the invention.
Description of the
Microtelephone Controller (MTC)
As previously indicated, the microtelephone controller
(MTC) i9 adapted to receive the serial output from the
QPLS to one or more digital telephone and/or voice
stations. The MTC demultiplexes data from the node, and
multiplexes signals to the node so as to integrate circuit
and packet switched data into a single signal stream
transmitted and received by the local station. The
discussion below initially presents an overview of the
functions of the MTC and the relationship of the various
signals passing therethrough. After that discussion a
more detailed description is given of the components in
the MTC that facilitate the specified functions.
3~ In a preferred embodiment, the MTC can be a large
scale integrated circuit in a 40-pin package. As shown in
Figures 42, 43, and 44, the MTC 611 may interface with a
system node 602, a microprocessor 643, a voice CODEC 613,
and a clear channel communications device 645. The MTC
can also provide enable signals to other devices such as
keyboards 646, 647 and to a display unit 648. The MTC can
_l 1 g_
communicate control information from the system node 602
to the microprocessor 643. Microprocessor commands can,
in turn, enable the selected devices to gate data to or
from the system node 602 via the MTC.
Figure 43 illustrates a typical implementation of the
MTC 642 and its function as the interface between the
system node 602 and the voice and/or data devices at the
local station. The system node 602 may function to
interface the voice and/or data communications between the
local station and the system network, as previously
described. The MTC 611, disposed in telset 601, may
receive serial biphase encoded data from the station port
of system node 602 and reformat the data, in accordance
with internal register configurations for transmission to
one or more voice CODEC's 613 and/or to one or more clear
channel devices 645. It can also receive serial data from
one or more voice CODEC's 613 and/or clear channel devices
645 and can transmit that data to the system node 602 as
biphase encoded data. The MTC 611 may also receive
parallel address and data information and control from the
microprocessor 643 or other control means and generate
enable signals to the CO~EC 613, keyboards 615 and 616,
and display 617. The MTC 611 may also respond to commands
from the microprocessor 612 by reconfiguring its internal
2~ registers or by sending internal MTC status information to
the microprocessor 612. In a typical implementation, the
- MTC 611 can also receive parallel control and signalling
information from t'ne microprocessor 612 and send that
information to the system node 602 in serial form, or
receive control and signalling information from the system
node 602 in serial Norm and send that information to the
microprocessor 612 in parallel form.
The MTC functional block diagram in Figure 44 shows
the MTC as six functional units for description
purposes. It should be understood, however, that the
enumerated functions are typically dispersed through the
~2~
-120-
device in the actual implementation. The system interlace
621 can receive the biphase encoded data (BPMI~) at a 192
kHz rate from node interface 165 and a 768 kHz clock from
the clock recovery unit 171. The system interfacè 621
also generates the biphase encoded data out (BPMOUT) to
node 602 via node interface 165. The serial information
stream on BPMIN from node 602 typically has the format
shown in Figure 45(a). In the preferred embodiment, once
every 125 microseconds node 602 transmits a 24-bit
information frame consisting of a synchronization bit,
seven bits of signal/control information, an eight-bit
voice channel and an eight-bit clear data channel. The
data is continuous, with the synchronization bit of one
frame following immediately after the last clear data bit
of the previous frame.
The synchronization bit, S, alternates between set (1)
and reset (0) in each frame. If this synchronization
pattern of alternating set and reset in the sync bit is
not maintained, the information from the system node 602
is not considered valid and typically is not transmitted
on the voice or clear data channel. As shown in Figure
46, if no messages are being transmitted by the system
node 602, the message frames consist of the alternating
sync bit with the remaining bits in the frame all 1's
except for the eighth bit, which is a constant 0.
The system interface 621 converts the biphase, encoded
data to nonreturn-to-zero (NRZ) data using well known
techniques previously described. That data is then made
available to the other MTC functional units illustrated at
Figure 44 as set forth below. The system interface 621
counts the information bits received from the system node
602. The seven bits following the sync bit are the packet
channel inEormation bits and are transmitted to the packet
channel logic 622 from the system interface 621. The next
eight bits are the voice information bits which are
typically transferred from the system interface o21 to the
-121-
voice interface 626. The last eight bits in a frame are
the clear channel data bits which are typically
transferred froTn t'ne system interlace 621 to t'ne clear
channel serial rate conversion logic 624. The system
interface 621 typically generates a synchronization signal
for each of the three functional subsystems which
indicates to the appropriate subsystem that the serial
data can be gated to that subsystem. See Figure 45(b).
Thus, the packet channel logic 622 typically responds to
data during the packet channel enable (~SEN) time. Voice
data is typically enabled to the voice channel output of
the voice interface 626 during channel 0 enable OVEN)
time. The clear channel asynchronous, synchronous and
terminal rate logic 625 responds to data during the
channel 1 enable time (DEN).
The voice interface 626 typically need not alter the
data received prom systems interface 621 before
transmitting that data to the CODEC 613. If the voice
channel is not disabled, the data received is enabled to
the voice data channel output (RDD) (shown in Figures 43
and 44) during the channel 0 enable time. The presence of
an active signal TSYNC can indicate to the CODEC 613, or
other device connected to the voice terminal output (RDD),
that the data is valid and should be clocked into its
serial input. The signal on TSYNC is typically active
only for the eight bit times when the voice data is
valid. The voice channel interface 626 provides a 19~ kHz
clock (DICLK) to synchronize the data out to the CODEC
613. The voice channel interface 626 also provides a 128
kHz CODEC filter clock (CCI). The 128 kHz CODEC filter
clock can be used internally by the CODEC S13 for digital
filtering. The voice data is clocked out to the CODEC 613
from the voice channel interface 626 on line RDD shown in
Figures 42 and 44. Voice data is clocked into the voice
channel interface 626 from the CODEC 613 on line TDD also
shown in Figures 42 and 44. The data on RDD and TDD is
-122-
typically synchronized with DICLK. The foregoing is more
clearly described in connection with Figure 47, which
illustrates the respective timing signals.
The voice interface 626 can also operate in the
loopback mode for diagnostic purposes. When configured in
that rode, data from the output port of the voice
interface logic 626 is typically gated back into the voice
interface logic 626 without passing through an external
device. Data from the external device to the voice
interface 626 is disabled in the loopback mode.
The first portion of the clear channel logic, i.e. the
clear channel serial rate conversion logic 624, can
provide serial data rate conversion (i.e., convert the
eight or sixteen bit bursts of clear channel data,
received from the system node 602 in at 1~2 kHæ, into a
steady continuous data stream at a lower rate.) T'ne
timing associated with that function is illustrated in
Figure 48. If the clear channel asynchronous, synchronous
and terminal rate logic 625 is configured to be a second
voice channel, the data can be transmitted without
conversion to the clear channel data output rate (XCDO).
(See Figure 47). The voice data enable output (VDEN) 674
from the clear channel asynchronous, synchronous and
terminal rate logic 625 is enabled during the last eight
bits of a message frame. At that tire, the data bits are
transmitted to a CODEC (not illustrated) connected to the
clear channel logic 625 in synchronization with the voice
port data clock output (DICLK). Similarly, data can be
clocked into logic 625 on the clear channel data input
(XCDI) in synchronization with DICLK. Thus, the last
eight bits of data in a frame are transmitted to a CODEC
unchanged in a 192 kHz burst similar to the operation ox
the voice channel.
If not configured as a second voice channel, the clear
channel serial rate conversion logic 624 can convert the
last eight bits of data in a frame, to an eight-bit per
-123-
frame data stream at 64 kHz. (tight bits of data at 64
kHz occupies the same 125 microsecond frame as 24 bits of
data at 192 kHz.) This 64 kHz data stream is transferred
to the clear channel asynchronous, synchronous and
terminal rate logic 625 to be transmitted to the data
device 614. Alternatively, the clear channel logic 625
can be configured to receive the entire sixteen bits of
data in a frame from the system node. (The voice channel
logic would typically be disabled in that mode.) In this
mode, the sixteen bits of data can be transmitted to the
clear channel asynchronous, synchronous and terminal rate
logic 625 from logic 624 at 123 kHz. Data transfer
formats for two modes of the clear channel serial rate
conversion logic 624 are exemplified in Figure 48.
The clear channel logic 625 also functions to generate
data in synchronous or asynchronous formats, and at
multiple data rates or each format. As previously
described, the clear channel asynchronous, synchronous and
terminal rate logic 625 receives data from the clear
channel serial data rate conversion logic 624 as eight
bits of 64 kHz data per frame or as sixteen bits of 128
kHz data per frame. This data can be transmitted directly
to the channel 1 output XCD0 typically after a delay of
one frame. Thus, the data is clocked into the MTC 611 at
192 kHz during one frame and clocked out at the selected
PBX data rate on the next frame. In the 128 kHz PBX mode,
the sixteen data bits are transmitted to the device 614
connected to the channel 1 output, XCD0. Similarly,
sixteen bits of data can be received from the device 614
in one frame and be transmitted to the system node 602
during the next frame. In the 64 kHz PBX mode, eight bits
of data can be transmitted in one frame to the device 614
connected to channel 1 output, XCDO, As shown in Figure
49, the channel 1 logic 624 and 625 can also operate in
kHz, 16 kHz or 32 kHz PBX modes. In those odes, one, two
or four bits, respectively, per frame are transmitted to
~Z~ 9
-124-
and received from the device 645 connected to the clear
channel logic 625. Data is clocked out on the data output
line, (XCDO), and is clocked in on the data input line,
(XCDI) 670. Typically, the output data is clocked out on
the falling edges of XCLKO and the input data is clocked
in on the rising edges of XCLKO.
For non PBX rates (synchronous or asynchronous), the
MTC functions to append framing signals to the signal from
the clear channel device and communicates that combined
signal to the system interface. By the reverse ox that
procedure the receiving station can extract the same
amount of information and thereby duplicate the original
signal through the use of conveniently sized signal
channel. Moreover, as detailed below the number of
appended bits can be monitored and adjusted, as necessary,
to correct for any variations where the local device is
providing the clocking for the signal it transmits to the
MTC, as occurs in the asynchronous mode. Such "bit
stuffing" and bit monitoring is unnecessary where the
~0 local device operates at a PBX rate, which can be readily
synchronized with the entire system.
In the synchronous terminal mode of operation the
format of the data character constructed by the MTC is
typically a start bit, a six-bit character and three stop
bits, for a total of ten bits per character. This is
depicted in Figures 50(a) and 50(b) which illustrate data
received from the system node 602 as 16 kHz data which is
to be transferred to the station device 614 as 9.6 kHz
data. In the synchronous mode the clear channel
asynchronous, synchronous and terminal rate logic 625,
shown in Figure 44, detects the start bit and counts the
number of bits until it receives the first stop bit. The
start bits and stop bits typically are not used by the
device 614 connected to the MTC. The remaining six-bit
character can be buffered for the duration of two
characters, and then shifted out to the device 614
~2
-125-
connected to the channel 1 output XCDO at the selected
data rate. The data rate typically can be 19.2 kHz, 9.6
kHz, 4.~ kHz, 2.~ kHz or 1.2 kHz. The output data can be
synchronized to the device 614 with the data clock output,
(XCLK0).
In the synchronous terminal mode (i.e. MTC provides
clock), the data from the device 614 connected to the
channel 1 logic 625 is clocked into the MTC with the MTC
data clock output, (XCLK0). The synchronous data from the
device 614 is continuous; however, the MTC operates with
the incoming data as if it were 6-bit characters. After
six bits of data are shifted into the MTC, a start bit and
three stop bits are typically added to form a character
consisting of ten bits. (See Figure 50(a).) The MTC can
be programmed to increase or reduce the number of stop
bits depending upon the data rate of the clear channel
device. That data character is typically transferred to
the system interface 621 at the next highest PBX data rate
compared to the data rate of the signal from terminal
614. Thus, if the terminal data rate is 9.6 kHz, the data
is transferred to the system interface 621 at 16 kHz.
Similarly, 19.2 kHz terminal data is transferred at 32 kHz
PBX rate. Terminal data at 4.8 kHz, 2.4 XHz and 1.2 kHz
is transferred at 8 kHz PBX rate. Data is typically
transmitted to and received from the system node 602 at
the same rate (i.e. 192 kHz) for any of the various MTC
internal PBX modes. The data between the PBX data rate
logic and the terminal data rate logic within the clear
channel asynchronous, synchronous and terminal logic 625
can be buffered to allow for the varying data rates.
Although the signal to the system node is typically
maintained at a constant data rate, i.e. one message frame
every 125 microseconds, the valid informational content of
the message frame will vary in accordance with the
particular data rates of the MTC as interconnected to each
given device. At the 32 kHz PBX rate mode, the data is
-126-
transferred to the system node 602 at four-bits bandwidth
per frame. In the 16 kHz PB~ node two bits per frame are
transferred and in the 8 kHz bandwidth mode one bit per
frame is transferred. The system node that receives the
variable bandwidth of valid information typically receives
programming information indicating the number of valid
information bits in each portion of the message frame and
can discard the remaining information. The receiving MTC
is configured the same as the transmitting MTC and is
interconnected to a device typically operating at the same
speed as the transmitting device. Therefore, the same
portion of the message frame that contains valid
information is extracted and communicated to the
interconnected device.
~5 Referring again to Figures 44 and 50, in the
synchronous terminal mode where the external device 614
provides the data input clock, data is received from the
device 614 on the data input line (XCDI). The data is
clocked into the MTC 611 in synchronization with the
terminal data clock (XSCLI). The data is formatted for
transmission to the system node 602 as set forth in the
foregoing description of the synchronous terminal mode
where the data was clocked in using the MTC data clock
output.
Since the XSCLI clock may vary with respect to the MTC
terminal clock output, potentially the variations in clock
rates between the MTC 611 and the terminal device 614 can
cause a loss of synchronization and7 therefore, a loss of
information. If the terminal device clock XSCLI is faster
than the MTC terminal clock by a small amount, the data
from the terminal device 614 will be received on XCDI at a
hi8her rate than the MTC transfers the data to the system
node 602. Similarly, if the terminal device clock is
slower, the MTC will be transmitting data to the terminal
device at 614 a rate slightly higher than the device 614
can receive it. The clear channel asynchronous,
~2
-127-
synchronous and terminal rate logic 625 automatically
corrects for the variations in the data rate from the
terminal device 614 and thereby prevents the loss of any
data. The details of the structure provided to monitor
and correct for variations in the bit rate is provided
below in connection with Figure 41(d). The discussion
immediately below describes the functions performed by
- that structure upon the occurrence of the stated
conditions.
10If the external terminal clock on XSCLI 668 is faster
than the MTC clock, the clear channel asynchronous,
synchronous or terminal rate logic 625 will occasionally
send out a character on the 16 kHz clear channel which has
a stop bit missing. In other words, the formulated
character will consist of a start bit, six character bits,
and two stop bits, rather than three stop bits. The start
bit of the succeeding character will start in the location
where the third stop bit would have been. See Figure
50(c). In this manner, the MTC is able to continue
inputting data at the rate of the terminal. Aster thy
character is transmitted, the remaining characters return
to the typical mode of one start bit, six character bits
and three stop bits per character.
The clear channel asynchronous, synchronous and
terminal rate logic 625 in the MTC 611 receiving the data
with a missing stop bit, can detect the missing stop bit
because the count between start bits will consist of nine
rather than ten bits. When the missing stop bit is
detected, the clear channel asynchronous, synchronous and
terminal rate logic 625 will increase the data clock,
XCLK0, to the terminal by a factor which will allow its
terminal device 614 to maintain pace with the received
data. As illustrated in Figure 50(d), the clear channel
asynchronous, synchronous and terminal rate logic S25 will
35 increase the transmit clock, XCLKO, to the terminal device
614 from 9.6 kHz to 9.~4615 kHz for the duration oE 24
-128-
terminal bit periods. At the end of the 24 terminal bit
periods, the data to the terminal device 614 should be
caught up with the 16 kHz clear channel data and t'ne
transmit clock, XCLK0, to the terminal device 614 is again
adjusted to 9.6 kHz. When the next character wit'n a
missing stop bit is received, the transmit clock, XCLK0,
to the terminal device 614 will again be adjusted or 24
bit periods to re-synchronize with the clear channel data.
If an MTC 611 connected to a terminal device 614 which
~0 supplies its own clock does not receive data fast enough
from that terminal device 614, the clear channel
asynchronous, synchronous and terminal rate logic 625 will
occasionally insert an extra stop bit in the ten-bit
character being transmitted to the system node. This is
illustrated in Figure 50(e). Thus, the MTC will
occasionally transmit a character consisting of eleven
bits. When that data stream is received by the receiving
MTC 611 elsewhere in the system, the clear channel
asynchronous, synchronous and terminal rate logic 625 in
the receiving MTC 611 will temporarily adjust the transmit
clock, XCLK0, for the data being transmitted to its
terminal device 614 to 9~3685 kHz. As seen in Figure
50(f), after transmitting 24 bits of terminal data at the
; lower rate, the clock is again adjusted to 9~6 kHz and the
data transmitted to the terminal device 614 is again in
synchronization with the 16 kHz clear channel data.
The fast clock, which synchronizes the terminal data
as illustrated in Figure 50(d), can be derived from the
768 kHz system clock by first multiplying the system clock
by a factor of two to 1. 536 MXz and then dividing the
times-two system clock by 156 to obtain a 9~84615 kHz
slgnal. The normal data rate clock at 9~600 kHz can be
derived in the like manner by dividing the 1. 536 MHz by
160. Finally, the slow data rate clock of 9~3685 kHz,
which synchronizes the terminal data as illustrated in
Figure 50(f), can be derived by dividing the 1 o536 ~Hz
-129-
clock by 164~ In like manner, if the system is operating
at 19.2 kHz, the fast clock can be derived by dividing
1.536 ~Hz by 78, and the slow clock can be derived by
dividing the 1.536 MHz by 82. Since the clear c'nannel
s data will be received at 32 kHz, the missing or extra stop
bits will be compensated for in 24 terminal rate bit
periods as was done in the 9.6 kHz mode. It should be
clear to those skilled in the art that analogous clock
connection schemes using the same or other clock and data
rates may be implemented without departing from the scope
of the present invention.
The channel 1 asynchronous, synchronous and terminal
rate interface logic 625 can also receive data from and
transmit data to the terminal device 614 in the
asynchronous mode at 19.2 kHz, 9.6 kH7, 4.8 kHz or 2.4
kHz. The data can be typically transmitted and received
in message lengths of 6, 7, 8, 9, 10, 11 or 12 bits. In
the presently preferred embodiment, the MTC 611 has an
internal clock generated by the clear channel serial rate
conversion logic 624 which samples the incoming data from
the terminal device 614. The sampling of the incoming
message is done by using a clock operating at ten times
the incoming data rate and synchronizing on the start and
stop bits. As with the synchronous terminal data, the
data is typically transmitted to the system node at the
next higher PBX data rate.
The clear channel asynchronous, synchronous and
terminal rate logic 625 can also be configured to operate
in the loopback mode. In this mode, the data out of the
clear channel asynchronous, synchronous and terminal rate
logic 625 is gated into the clear channel asynchronous,
synchronous and -terminal rate logic 625 for diagnostic
purposes. Typically, data is not transmitted to or
received from an external device while logic 625 is in the
loopback mode.
-130-
Packet channel data is communicated between the system
node 602 and the MTC 611 in order to monitor the status of
the MTC and interconnected devices, to control the flo~J
and format of data in response to the monitored
5 conditions, and to perform other management functions.
Alternatively, the packet channel can be used as a
separate data channel to communicate data between device
614 and some other device or a portion of the node,
without establishing a circuit path tnrough the node data
10 steering logic. The capability to send data on the packet
channel not only provides further data transport capacity,
but permits direct access to the node processor from the
station device 614. Thus, an operator may utilize the
services ox the node processor to perform analytical or
15 management functions interactively with the transmission
or reception of data via the information channels.
This capability is depicted in Figures 44 and 44A.
Referencing Figure 44, a user who desires data access to
the packet channel would generate a signal at the data
20 device 614 w'nich would be read by the microprocessor
612. The microprocessor would then enable a switch to
communicate the information from the clear channel
interface to the microprocessor, where it could be
communicated to the packet channel logic 622 via the
25 microprocessor interlace 623.
The capacity to send data signals via the packet
channel is further illustrated at Figure 44A. In that
figure data is communicated Erom a station device
connected to RS-232 port 169 to switch 167. The switch
30 167 can either communicate data directly to the
microtelephone controller 611, where it is communicated as
packet switch data. If the user activates designated keys
in the station device, the microprocessor will recognize
that signal as a request to access the packet channel and
35 will disable the packet channel connection to the
microtelephone controller 611. When packet channel access
-131-
is indicated, the data from the RS-232 port 169 will be
communicated to the microprocessor 612 which will format
the data for transmission to the packe-t channel connection
to the microtelephone controller 611. Circuit switched
S data and packet channel data are communicated to the node
via the node interface 165. Voice data is communicated to
analog section 613.
The capabilities provided by the alternative
communication paths dramatically enhance the functional
capacity of the teleterminal without necessitating
cumbersome and inconvenient connections to the system
node. The user may communicate with a distant station via
the packet switch channel while viewing control
information on a display 617, on a printed page generated
by keyboard 616 and/or while conversing with a distant
station via analog section 613. Details of
synchronization of the various communication paths are
provided below.
The synchronization and monitoring provided by the
packet channel logic facilitates synchronization of the
MTC with the operation of the node, and is beyond the
station device synchronization techniques implemented by
the clear channel logic, as previously described. In the
preferred embodiment, packet channel data from the system
node 602 is configured according to the convention
provided below. It is, however, understood that various
other conventions may be implemented without departing
from the scope of the invention.
The packet channel logic 622 monitors the six bits
following the sync bit. Figure 45 illustrates a typical
format for the packet data in a frame. If the second bit
in an information frame is set (0), the packet slag (PF)
is active, indicating that the system node is sending
packet data to the MTC. If the seventh bit, K, is reset
(1), the four bits of packet data are active data rather
than fill data. It PF is set and K is reset, the packet
-132-
channel logic 622 will load the four bits of packet data
into a shift register in logic 622. When an additional
four bits of packet data are received with PF set and K
reset, the packet channel logic 622 sets the input read
S flag which can be read by the microprocessor ~12 by
accessing the status register of the MTC. T'ne
microprocessor 612 then executes a packet data read to
input the data prior to the accumulation of the next eight
bits of packet data by the packet channel logic 622. If
l the microprocessor 612 does not read the packet data
within 250 microseconds and the system node 602 has
transmitted eight additional bits of data, an overrun flag
bit will be set to indicate the occurrence of this
condition. any data received with the packet flag active
and the K flag active (set) can be ignored as fill data.
When the packet flag goes inactive, the packet channel
logic 622 will check a counter to determine whether an
even number of four-bit nibbles have been received by the
MTC. If an odd number of nibbles are received, the
underrun flag can be set to indicate that a complete
message was not received.
The packet data received by the MTC 611 with the
packet flag active and the K slag inactive is also gated
through cyclic redundancy checking logic (CRC) 716 in
packet channel logic 622. (See Figure 51(a).) The last
sixteen bits of data (two bytes) received by the MTC 611
prior to the inactivation of the packet flag are typically
error-checking bits generated by the CRC in the system
node 602. When the inactive packet flag is received, the
output of the CRC should be all zeros, indicating that a
valid message was received. If the output of the CRC is
not all zeros, the CRC error flag is set by the packet
channel logic 643 to indicate the occurrence of an error
in the received data. Notwithstanding the condition of
the CRC outputs, the packet channel logic 643 sets the end
of message status bit to indicate to the microprocessor
612 that the message is completed.
.
-133-
Packet data to the system node 602 typically is
received by the MTC 611 from the telset microprocessor 612
as eight-bit bytes. The eight-bit bytes are typicaLly
accumulated in the MTC 611 and then communicated to the
system node in four-bit nibbles as packet data The data
to the node is routed through an internal CRC generator
described below in connection with Figure 51(a). If the
MTC 611 does not receive an additional eight bits from the
microprocessor 612 before the start of the third frame
following receipt of the first 8 bits, the packet channel
logic 611 typically presumes that the microprocessor 612
has no further data to send to the system node 602. The
packet channel logic 43 then sets a busy flag which
indicates to the microprocessor 612 that the
microprocessor should not send further packet data to the
packet channel logic 622~ The packet channel logic 622
then appends the internally generated CRC data to the last
message sent. Four frames are typically required to send
the sixteen bits of CRC data in the four-bit packet data
location in the message frames. The busy flag remains set
during those four frames and typically for two extra
frames following the completion of the transmission. The
packet flag is typically inactivated at the end of the
sixteen bits of CRC data. The extra two frames of delay
are optionally provided to allow the system node 602 to
perform any processing which it may require at the end of
each message. The MTC packet channel logic 622 need not
utilize the K flag for transmission to the system node 602
since it does not have to send fill data. However, in
alternative embodiments of the MTC, the K flag can be used
to allow the microprocessor 612 to temporarily quit
sending data to the MTC 611 without causing the packet
channel logic 622 to terminate the message as described
above.
Referencing Figures 44 and 51ta), the microprocessor
interface 626 can receive parallel data from and send
-134-
parallel data to the telset microprocessor 612 on eight
data lines, PD7-PDO. The functions performed by the MTC
are typically determined by the address information on
lines PA5-PA0, the select line, IOS, and the read/~rite
5 control line, RW. If the address lines and select line
from the microprocessor 612 select the MTC 611, the
microprocessor interface logic ~23 can cause t'ne MTC to
transfer data to (RW = 0) or receive data from (RW reset)
the microprocessor 612 when the enable line, E, is
10 activated by the microprocessor 612. The microprocessor
interface 623 can also respond to certain commands from
the microprocessor 612 by generating enable signals to
devices connected to the TELSET 601. When an enable
signal to an external device is activated, the MTC 611
15 typically does not receive data from or send data to the
microprocessor 612.
Detailed Descriptions of the Functional Units
A more detailed description of the particular circuits
that may be implemented to perform the above mentioned
20 functions of the MTC will be set forth below in connection
with Figures 51(a)-51(e) and 52.
System Interface
Figure 51(a) shows a detailed block diagram of the
system interface 621 and the packet channel logic 622,
25 shown more generally in Figure 44. Data is received from
the system node in the form of biphase mark encoded data,
sometimes referred to as biphase Manchester encoded
data. The generation and decoding of biphase mark encoded
data is well-known in the art. A brief description of the
30 characterization and manner of processing such data is set
forth below.
As seen in Figure 52, biphase mark encoded data can be
characterized by having at least one data transition per
bit period. Nonreturn-to-zero (NRZ) data can be
35 characterized as having the bit value represented by the
logic level of the signal throughout the duration of the
~2~28
-1 35-
bit time (i.e., a 1 is represented by a high voltage level
and a 0 is represented by a low level), In order to
extract the NRZ data, the receiving device typically must
also receive a clock or other synchronization signal to
define the bit periods. The biphase mark encoded data can
be transmitted without a clock since each bit position has
at least one transition. If two transitions occur in one
bit position, the decode logic 702 (Figure 51(a3) of the
system interface outputs a logic one in the NRZ format.
If only one transition occurs in a bit position, the
decode logic 702 outputs a zero in the NRZ format An NRZ
clock is typically generated by the decode logic 702 to
synchronize the NRZ data with the MTC logic.
The NRZ data received from the system node is shifted
into a 25 bit shift register 704. The twenty-fifth bit of
the shift register can be compared with the first bit of
the shift register by the exclusive-OR gate 706. When the
two bit positions are different, the output oE the
exclusive-OR is a logic one which indicate that the bit
was different in succeeding frames. If this is the first
bit position in a frame, the sync logic 708 will output
the sync signal that controls the timing chains within the
MTC. The timing logic 710 generates three timing signals
as shown in Figure 45. The packet channel enable signal
(BSEN) gates the packet data into the packet channel logic
43. The channel 0 (voice) enable (VEN) gates the voice
channel data into the voice interface logic 626. The
channel 1 (clear channel data) enable (DEN) gates the
channel 1 data into the clear channel serial rate
conversion logic 624 and into the clear channel
asynchronous, synchronous and terminal rate logic 625.
Multiplexor 712 in the system interlace 621 can also
receive data from the packet channel 622~ the voice
interface 626 and the clear channel logic 624. That data
can be gated out of the MTC through the encode logic 714
as biphase mark encoded data.
-136-
Packet Channel
The packet channel logic 622 receives the NP~Z data and
clock from the system interface 621. The data is
typically gated into the control logic 718 when the packet
channel enable signal is active. The control logic 718
detects whether there is an active packet flag ~PF) and
whether the fill flag is inactive. If both conditions are
met, the data is gated into an eight-~it shift register
7~2 in the packet data in logic 732 through AND-gate 720
at a rate of four bits per frame. When eight bits of
packet data are accumulated, the data input ready status
bit can be set and an interrupt request can be sent to the
microprocessor 612 via the microprocessor interface 623
shown at Figures 44 and 41(e). An interrupt is generated
once every two frame times, synchronized with the active
signal on VEN. If the data byte ready bit occurs in the
odd frame, the interrupt will synchronize to it. This
adjustment only occurs once (i.e., on the first byte
received). The output of shift register 722 is loaded
into input register 732. The occurrence of the ready bit
informs the microprocessor that it should perform a status
read to determine what condition has occurred. The
microprocessor reads the packet data input via the
microprocessor interface 623 before the accumulation of
the next eight-bit byte of data in the packet data logic
- 622. If the packet data is not read before the
accumulation of the next eight bits, the overflow status
bit is typically setO
The valid data received by the packet channel is also
gated through the CRC checking logic 716. The CRC
checking logic 716 accumulates the four bits of data
received during each frame in a cyclic redundancy checking
circuit. When the data received from the system node has
the packet flag reset, the accumulated data in the CRC
checker causes the output of the CRC to be zero,
indicating that no errors were received in the incoming
-137-
packet data. If an error was received, the CRC error bit
is typically set in the status register 724.
The receipt of the packet data with the packet flag
reset can also cause the control logic 718 to set the end
of message status bit in the status register 724. If the
end of message occurs when only four bits of data have
been accumulated in the packet data in shift register 722,
a message underflow status bit can be set to indicate that
an incomplete message was received from the terminal
node. The end of message can also indicate to the
microprocessor that the last two bytes of data received
were the CRC check bytes generated by the system node and
can be ignored as packet data.
The packet channel logic ~22 can also formulate packet
data to be sent to the system node. The eight bits of
data from the microprocessor are loaded into shift
register 726 and are shifted out through multiplexer 730
at a rate of four bits per frame. The packet flag can be
set by the packet channel logic 622 to indicate to the
system node that the packet data is valid. The packet
data is also routed through a CRC generator 728 which
generates and accumulates CRC data to send to the system
node 602 at the end of the message.
When the microprocessor does not send an additional
eight bits of data within two frames (e.g, 250
microseconds), the control logic 718 typically resets the
packet flag going to the system node and enables the
output of the sixteen bits of accumulated CRC data from
the CRC generator 728 during the next four frames. T'ne
control logic 718 can also set the busy status bit in the
status register 724 to inform the microprocessor that the
MTC cannot receive any further packet data until the
completion oE the message transfer. The busy flag
typically remains set until two frames following the
transmission of the CRC data. The Eill flag is typically
not used in the above-described mode.
2B~
-138-
In an alternative embodiment, the control logic 718
will set the fill flag when system interface 621 does not
receive an output from the microprocessor within 250
microseconds after the previous microprocessor output.
The control logic 718 will cause all ones to be sent in
the packet channel and will not route the packet data
through the CRC generator 728. The packet flag will not
be reset in this alternative embodiment until the
microprocessor sends a command to the MTC to indicate that
the packet flag should be reset.
Voice Interface
The voice interface logic 626, shown in Figure 44 and
illustrated in more detail as part of Figure 51(b), can
generate signals to the codec 613 and transfer data to and
from the codec 613. If the MTC is not in the 128 kHz PB~
mode, the voice interface generates the TSYNC signal
during the channel O enable time. During the time that
TSYNC is active, the codec 613 can receive the NRZ data
prom the system interface on the RDD line using the 192
kHz clock on the DICLK line. The TSYNC signal also causes
AND-gate 780 to gate NRZ data from the codec 613 (TDD)
through multiplexer 778. This data is typically available
to the system interface 621 as channel O data output to be
gated to the system node 602 during the channel O time.
In the previously described loopback mode, multiplexer 778
selects the NRZ data from the system interface 621 to be
gated back to the system interface 621. In the loopback
mode, the loopback input to OR-gate 776 typically forces
all 1's on the read data line, RDD to the codec 613.
Clear Channel Serial Rate Conversion Logic
The clear channel serial rate conversion logic 624
shown in Figure 4h is illustrated in more detail as parts
of Figures 51(b), 51(c) and 51(d). It can convert the
system clock of 768 kHz to the various clock rates
required by the other logic in the ~ITC. Figure 51(b) is a
block diagram of the clock generation circuitry of the
-139-
clear channel serial rate conversion logic 624(a). The
times-two logic 742 multiplies the system clock by two to
create a 1.536 MHz clock to be used by the clear channel
asynchronous, synchronous and terminal rate logic 625.
The terminal clock is generated by the six-bit counter
744, toe multiplexer 746 and the divide-by-ten counter
748. The counter 744 generates clock rates which are ten
times the terminal clock rate. The multiplexer 746 will
select the appropriate rate, and the divide-by-ten counter
748 will convert the rate to the terminal clock rate. The
output of multiplexer 746 is also available as a times-ten
clock for the start detection logic in the asynchronous
mode.
The divide-by-six counter 750, the four-bit counter
752 and multiplexer 754 generate the PBX clock. The
multiplexer 754 can select the 128 kHz output of counter
750 for the 128 kHz mode. Otherwise, the multiplexer can
select one ox the four outputs of the four-bit counter 752
for the 64 kHz, 32 kHz, 16 kHz, or kHz PBX mode.
The divide-by-five counter 756 and the seven-bit
counter 758 can generate a times-eight clock for the
microprocessor universal asynchronous receiver and
transmitter (UART). The selectable output of 153.6 kHz,
76.8 kHz, etc. can provide the times-eight clock typically
required by the microprocessor UART on line OUCLK. In
addition, the 2.4 kHz output of the seven-bit counter 758
is the input to the divide-by-four counter 770 in the
voice interface logic 626. Counter 770 generates the 600
Hz call waiting signal which is available on line CW.
3~ Clear Channel Asynchronous, Synchronous
and Terminal Rate Logic
Figure 51(c) is a detailed block diagram of the
channel 1 encode logic 625(a) and part of the clear
channel serial rate conversion logic 624(b). The encode
logic 625(a) is part ox the clear channel asynchronous,
synchronous and terminal rate logic 625 shown in Figure
-140-
44. Encode logic 625(a) can receive data from the
terminal device 614 and prepare it for transmission to the
system node 602. In the asynchronous mode or in the
terminal mode where the MTC provides the clock 7 the
terminal clock is selected. In the synchronous mode with
an external clock, XSCLI, the external clock is
selected. In the PBX mode, the internal PBX clock is
selected. Multiplexer 802 selects either the input data
from line XCDI in non-loopback modes, or from the NRZ
output in the loopback mode. The start detector 600 can
be used in the asynchronous mode to detect the occurrence
of the start bit in the asynchronous data. Start detector
800 can utilize the 10~ clock to sample the incoming data
until the start bit i9 detected. The output of the start
detector enables the selected clock through the clock
enable circuitry 806. The selected data from multiplexer
802 is shifted into shift register 812 utilizing the clock
generated by the clock enable circuitry 806. The
programmable bit counter 810 can function to determine
when a full character of data has been received and can
load the data into the synchronous shift register 814 and
the asynchronous shift register 816.
As described above, six bits of data per character are
typically transmitted by the terminal device 1014 in the
synchronous mode. Therefore, shift register 814 is
typically loaded with the six bits of data and the start
bit and the first stop bit. In the asynchronous mode, the
en-tire character of data typically will be transmitted to
the system node 602. Therefore, up to twelve bits of data
can be loaded into the shift register 816 from shift
register 812.
In the terminal mode, control logic 820 can receive
inputs from programmable bit counter 822 and programmable
bit counter 810 to determine when the data in synchronous
shift register 814 and asynchronous shift register 816
should be clocked out at the PBX data rates. Multiplexer
19
-141-
818 can select either the asynchronous data from s'nift
register 816, the synchronous data from shift register
814, or the direct data input from multiplexer 802. The
direct data input is selected in the PBX mode or in the
second voice channel mode. The data from multiplexer l
can be shifted into shift register 824, which is part of
the clear channel serial rate conversion logic 624(b) also
shown in Figure 51(b), at the PBX data rate. If the data
received is an additional channel of voice data, the
output of multiplexer 818 is a direct input to multiplexer
828 to be shifted out during the channel one enable time
at the system data rate. Shift register 826 can be loaded
with the output of shift register 824 and can be shifted
out serially at the 192 kHz data rate. The data shifted
into shift register 824 and shifted out of shift register
826 is typically elght bits length. In the 128 kHz PBX
mode, sixteen bits of data may be shifted into shift
register 824 and out of shift register 826 during the
channel 0 and channel 1 enable times. In the 128 kHz PBX
mode, the channel 0 voice interface logic is typically
disabled.
As previously described, the number of bits
transmitted and received by the MTC in the preferred
embodiment in each 125-microsecond frame is constant, i.e.
24 bits; however, the MTC accommodates the different data
rates by varying the number of valid data bits transmitted
or received during each frame. For example, in the 64 kHz
PBX mode, the eight bits labelled CD7-CD0 are valid data
bits. (Eight bits per frame times 8,000 frames per second
equals 64,000 bits per second.) To accommodate the 128
kHz PBX data rate, the MTC must disable the voice channel
and use the eight bits of voice channel data, V7-V0, as
additional clear channel data bits. Conversely, iL less
than a 64 kHz data rate is required, the MTC does not
utilize all eight bits in the clear channel portion of the
- message frame. For instance, in the 32 kHz PBX mode, the
-142-
MTC will transmit and receive valid data with bits
CD3-CD0, and bits CD7-CD4 will be undefined. Although
bits CD7-CD4 will be transmitted, the system node will be
programmed to ignore them, just as the MTC will ignore
bits CD7-CD4 when received. Since the system node will
ignore the bits, they will not occupy part of a system
time slot.
Figure 51(d) is a detailed block diagram of the
channel 1 decode logic 625(b) which forms part of the
clear channel asynchronous, synchronous and terminal rate
logic 625, and is also a detailed block diagram of the
clear channel serial rate conversion rate 624(c), both
generally shown in Figure 44. In the normal mode of
operation NRZ data and the 192 kHz system clock can be
received from the system interface 621 by s'nift register
900 in the clear channel serial rate conversion logic
624. In the second voice channel mode, the NRZ data can
be gated through multiplexer 908 and multiplexer 918
directly to the output where it is shifted out during the
channel 1 enable time. Circuits within the clear channel
serial rate conversion logic, represented by AND-gate 944,
can generate the voice data enable signal (VDEN) which
gates the data out during the channel one enable time. In
all other modes, the NRZ data from system interface 621
can be shifted into shift register 900 by the 192 kHz
system clock during the channel 1 portion of the message
frame. The output of control logic 902 enables the 192
kHz clock for eight (normal mode) or sixteen (128 kHz
mode) clock periods through the logic represented by
AND-gate 904. Responsive to the output of AND-gate 904,
shift register 900 receives eight bits of data, in the
normal mode, or sixteen bits of data in the 128 kHz PBX
data mode. Shift register 906 can be loaded once per
frame with the output of shift register 900. The data
shifted out of shift register 906 at the PBX clock rate is
input to multiplexer 908.
-143-
In the PBX rate modes, multiplexer 918 of the clear
channel asynchronous, synchronous and terminal rate logic
625(b) can select the output of multiplexer 908 for direct
output to the terminal device. In the synchronous or
asynchronous terminal modes, the output of multiplexer 908
can be shifted into shift register 910 ox the clear
channel asynchronous, synchronous and terminal rate logic
625(b) at the PBX clock rate. The number of clock edges
required to gate shift register 910 can be determined by
the start bit detector logic 924. That logic searches for
the occurrence of the first start bit and can shift data
into shift register 910 until the occurrence of the next
stop bit. In the asynchronous mode multiplexer 918
selects the output from asynchronous buffer 920 for
terminal communication to the terminal devices. In the
synchronous mode, multiplexer 918 selects the output of
shift register 916. In either the synchronous or
asynchronous terminal modes, the output rates may be
monitored and controlled as described below.
The output of the programmable bit counter 926 can
also control the programmable stop bit counter 928.
Counter 928 can count the number of stop bits from the
last data bit until the occurrence of the next start bit
as indicated by detector 924. The output of the stop bit
counter 928 is input to the stop bit error detection and
clock control circuit 930. In the presently preferred
embodiment the stop bit counting and detection circuitry
operates to provide a nominal output when three stop bits
are detected. If three stop bits are detected, the enable
nominal clock rate signal typically enables the output of
register 934 to the seven-bit tri-state bus which is input
to the seven-bit counter 938. If less than three bits are
detected, the enable fast clock output of clock control
circuit 930 can enable the seven-bit output of register
932 to the tri-state bus. If more than three stop bits
are dejected, the enable slow output of clock control
-144-
logic 930 can enable the seven-bit output of resister 936
to the tri-state bus. The tri-state registers 932, 934
and 936, are loaded with a seven-bit value which
represents a value by which the 1.536 MHz clock is to be
divided to generate the terminal clock frequency as
previously described. The registers can be loaded with
the contents of the least significant seven bits on the
data lines (D6-D0) by a write command from the
microprocessor 612. In the preferred embodiment, the fast
frequency register is typically loaded with a value of 39;
the nominal rate register is typically loaded with a value
of 40; and the slow rate register is typically loaded with
a value of 41. At the end of each terminal character
output, the seven~bit counter 938 is loaded with the
seven-bit value from the selected tri-state register. The
1.536 ME~z clock is then divided by that value to result in
a frequency of 39,230 Hz for the fast clock, 38,400 Hz for
the nominal clock and 37,951 Hz for the slow clock. The
clock control logic 930 can enable the fast or slow
register output for the duration of 45 terminal bit
periods. At that time, the nominal clock rate register
will be re-enable until the occurrence of the next extra
or missing stop bit. The output of the seven-bit counter
is counted down by the five-digit counter 940 to achieve
the requisite clock rates for the terminal clock. In the
present embodiment, multiplexer 942 can select one of the
five clock rates from 5-bit counter 940. If the nominal
clock is selected, the output of multiplexer 942 can be
19.2 kHz, 9.6 kHz, 4.8 kHz, 2.4 kHz, or 1.2 kHz. The
particular clock rate employed is selected in response to
the requirements of clear channel device 101$.
The terminal clock output of multiplexer 942 can clock
the asynchronous shift register 920 and the synchronous
shift register 916 and can also be sent to the terminal
device on XCLK0 666. In the asynchronous mode, the
terminal clock is typically the nominal clock frequency,
-145-
and the output of the asynchronous shift register 920 can
be gated through multiplexer 918 to the terminal device on
XCD0. In the synchronous mode, the output of the
synchronous buffer 912 can be gated through buffer 914 and
5 through shift register 916 before it is shifted out
through multiplexer 918 by the MTC terminal clock. As
previously described, the terminal clock may be affected
by the selection of the :East or slow clock rates. The
gating of data from buffer register 912 through buffer 914
into shift register 916 is controlled by control logic 922
to assure that the data is synchronized in the transition
from the PBX clock rate of shift register 910 to the MTC
terminal clock rate oE shift register 916.
Figure 51(d) also illustrates how the MTC accommodates
15 the varying data rates. Shift register 900 receives eight
bits of data per :Erame (sixteen bits per frame in 128 kHz
PBX mode) which are shifted in at the 192 kHz system clock
rate. At the end of each frame, the data in shift
register 900 is parallel loaded into shift register 906.
Although at least eight bits of data are loaded into shift
register 906 in any of the modes, only the valid data will
be serially shifted out of shift register 906. For
instance, at the 32 kHz data rate, shift register 906 will
only receive four clock edges in the interval from the
25 time it is loaded at the end of one frame until it is
loaded again at the end of the next frame. Thus, the
invalid data bits do not get shifted out of shift register
906 to be propagated through the ~ITC.
In the synchx:onous terminal mode, synchronous buffer
30 912 strips the start bits and stop bits from the incoming
data stream by only loading the six bits of data following
the start bit which have been shifted into shift register
910. Thus, orlly six of the ten bits that were shifted
into shift register 910 at 32 kHz will be shifted out of
3~ shift register 916 at 19.2 kHz.
-146-
Microprocessor Interface
The microprocessor interface 623 is shown in Figure
51(e). Referencing Figure 44 also, the microprocessor
interface 623 can receive parallel data prom and send
parallel data to the telset microprocessor 612. The
microprocessor interface 623 can decode the address lines
PA5, PA4 and from the microprocessor 612 to determine
whether it is being accessed by the microprocessor 612.
The microprocessor interface 623 can decode the least
significant four address lines (PA3-PA0) from the
microprocessor 612 to determine the function to be
performed. The two most significant address lines (PA5
and PA4) typically must both be reset (0) to indicate that
the MTC 611 is being accessed by the microprocessor 612.
If either or both are set, the MTC does not respond to any
of the microprocessor commands. The demultiplexer logic
1002 can decode the microprocessor addresses, PA5, PA4,
P~3-PA0, the enable line, E, the input/output select
line, IOS/ and the read/write select line, RW to determine
the operation to be performed by the MTC 611.
The read/write input, OW, informs the MTC which
direction data is being transmitted. If RW is a logic one
(read), the microprocessor 612 typically is initiating a
read cycle which indicates that the MTC 611 or another
device (i.eO, keyboards 615 or 616, or display 617) should
output` data on the data bus. If RW is a logic zero
- (write), the microprocessor 612 will typically be driving
the data bus to provide information to the MTC 611 or to
another device. Data between the MTC 611 and t'ne
microprocessor 612 can be transmitted and received on the
eight bidirectional data lines, PD7-PDO. The enable
input, E, determines when the data lines are active during
a read or write. The input/output select IOS/ is an
additional input which can determine when the MTC should
respond. When it is low, the MTC 611 can respond to
microprocessor commands.
-147-
The operations typically performed by the MTC 611 in
response to commands from the microprocessor 612 are
summarized in the following exemplary MTC Control Register
Definition Table. The addresses shown in hexadecimal
format are whose addresses decoded from PA3, PA2, PA1 and
PA0. The bit assignments refer to PD7-PD0.
. _ . . _
MTC CONTROL REGISTER DEFINITIONS
The following table defines each control resister bit
within the TO Descriptions are from the standpoint of a
microprocessor accessing the MTC's paraliel port, so the
symbol IN: refers to data read by the microprocessor from
th MTC, and OUT: refers to data written into the MTC.
ADDRS BIT DESCRIPTION
. __
00 7-0 IN: SIGNALING DATA
7-0 OUT: SIGNALING DATA
O1 0 IN: SIGNALING DATA IN READY WHEN LOW
1 " " OUT BUSY WHEN LOW
2 " " IN OVERFLOW WHEN LOW
3 " " IN CRC ERROR WHEN LOW
4 " " IN END MESSAGE WHEN LOW
" " IN UNDERFLOW WHEN LOW
7-6 NOT USED
XX OUT: RESET MTC (Does not affect control
registers)
02 7-0 IN: READ KEYBOARD MATRIX #1
7-0 OUT: SIGNAL &AIN AND CALL WAITING CONTROL
03 7-0 IN: READ KEYBOARD MATRIX #2
XX OUT: NOT USED
04 7-0 IN: DISPLAY READ INTERNAL RAM ADDRESS POINTER
(DD &CG)
7-0 OUT: DISPLAY COMMAND WRITE
05 7-0 IN: READS DATA FROM DISPLAY (DD / CG)
OUT: WRITES DATA TO DISPLAY
06 7-0 IN: NOT USED
OX OUT: CLEAR STATUS WORD
07 7-0 IN: NOT USED
XX OUT: CLEAR INTERRUPT FROM MTC
-148~
08 7-0 IN: NOT USED
0 OUT: MODEM MODE WHEN LOW; TERMINAL MODE WHEN
HIGH
1 ASYNCHRONOUS MODE WHEN LOW; SYNC WHEN HIGH
2 LOOP CHANNEL 0 WHEN HIGH
3 LOOP CHANNEL 1 WHEN HIGH
4 PBX RATE ZEN LOW; TERMINAL RATE WHEN HIGH
7-5 RATE SELECTION:
ASYNC PBX SYNC
000 NONE12~K NONE
001 NONE64K NONE
010 19,2K32K 19.2K
011 9.6K 16K 9.6K
100 4.8K 8K 4.8K
101 2.4K 8K 2.4K
1.2K
llx NONENONE NONE
09 7-0 IN: NOT USED
0 OUT: NOT USED
3-1 BITS PER MESSAGE-CXC SIDE
000 12
001 11
010 10
011 9
100 8
101 7
110 6
111 NOT USED
5-4 NOT USED
6 128K MODE WHEN HIGH (USES BOTH CHANNELS)
7 CHANNEL 1 IN VOICE MODE WHEN HIGH
0A 7-0 IN: NOT USED
0 OUT: NOT USED
3-1 BITS PER MESSAGE-TERMINAL SIDE (SEE 109,
BITS 3-1)
5-4 NOT USED
7-6 BITS PER FRAME:
00 1
01 2
10 4
11 8
OB 7-0 IN: NOT USED
2-0 OUT: MICROPROCESSOR UART CLOCK
000 19.2K BAUD
001 9.6K
010 4 8K
011 2 4K
100 1.2K
24L28~L9
-149-
101 .6K
110 .3K
111 .15K
3 UART CLOCK ENABLE WHEN HIGH
4 NOT USED
PWDN OUTPUT HIGH WHEN HIGH
6 NOT USED
7 NOT USED
0C 7-0 IN: NOT USED
6-0 OUT: FAST CLOCK VALUE FOR SYNC TERMINAL MODE
19.2K-4.8 27
2.4K-1.2K 4F
7 NOT USED
OD 7-0 IN: NOT USED
6-0 OUT: NOMINAL CLOCK VALUE FOR SYNC TERMINAL
MODE
19.2K-4.8 28
2.4K-1.2K 50
7 NOT USED
OE 7-0 IN: NOT USED
6-0 OUT: SLOW CLOCK VALUE FOR SYNC TERMINAL MODE
19.2K-4.8 29
2.4K-1.2K 51
7 NOT USED
**NOTE: The last three registers (10C, 10D, 10E) contain
counter pre-load values for varying che outbound clock
what the MTC provides for synchronous terminals that
operate at other than power-of-2 frequencies.
OF 7-0 IN: NOT USED
4-0 OUT: STOP BIT COUNTER PRESET VALUE
19.2K-2.4K lE
1.2K 14
7-5 NOT USED
The data read (address 00) can cause the eight bits of
data from the packet channel input logic 622 to be gated
through the bidirectional gate 1004 to the microprocessor
data bus (D7-DO). The status read (address 01) can cause
the status bits from the packet channel interface logic
622 to be gated through the bidirectional gate 1004. The
format of the status bits transmitted to the
~2
-150-
microprocessor 612 is shown in the MTC Control Register
Definition Table. The packet enable line, activated by a
write to address 00, goes to the packet channel logic ~22
to cause eight bits of data to be gated through the
bidirectional gate 1004 to the packet channel shift
register 726 in Figure 51(a). The reset TO line,
activated by a write to address 01, causes certain initial
conditions of the MTC to be set. The clear status line,
activated by a write to address 06, clears the status
register in the packet channel logic. The clear interrupt
line, activated by a write to address 07, clears the
packet channel logic interrupt.
If the 1nicroprocessor 612 performs a read command on
address 602, the MTC 611 generates an enable signal to a
keyboard matrix 614 which typically causes that keyboard
matrix to enable its data output to the eight
bidirectional data lines. When this occurs, the MTC 611
typically does not drive the data lines. Similarly, a
microprocessor read command on address 603 will cause an
enable signal to go to the other keyboard matrix 615. In
the same fashion, addresses 604 and 605 are used by the
microprocessor 612 to read prom or write to the display
616. The MTC 611 participates in the access by generating
enable signals to the display 616 when either address is
decoded. Typically, the TO 611 neither drives the data
lines nor inputs the data for these two addresses.
If a microprocessor write command is performed on
address 602, the MTC 611 activates the gain signal SGN/,
to the telset 601. This informs the speaker phone or
another device in the telset that the data bus contains
control information for the speaker phone or the handset
speaker. This data is typically used by the speaker phone
or some other device to control the gain and also to
enable the call waiting signal CW. In conjunction with
3S this use, the MTC can also generate a constant 60U Hz
signal on CW which can be gated to the handset speaker or
g
-151-
to the internal speaker to generate the call waiting
signal tone.
A write on command address 0B with bit five set will
generate the power down (PWDN) signal which can be used by
a codec 613 or other device to turn its power off when not
in use,
The multiplexer 1008 generates enables which cause the
eight bits of data from the microprocessor to be gated
through bidirectional gate 1004 into registers 1010, 1012,
1014, 1016, 1018, 102Q, 1022 and 1024. These eight
registers hold the status bits described in the MTC
Control Register Definition Table and are activated by
write commands to addresses 8, 9, A, B, C, D, E, and F
respectively.
The bidirectional gate 1004 is a tri-state gate in
i each direction and does not affect the microprocessor data
bus (PD7-PD0) except when a status read or a data read
activates the enable line to the bidirectional gate 1004
tllrough OR-gate 1006.
Detailed Logic Diagrams of MTC Modules
Figures 43 through 54 are detailed logic diagrams
representing individual logic elements that may be
included in the MTC modules described and illustrated in
connection with the previous drawings.
As one of ordinary skiIl in the art will readily
recognize, the structure and functions described in
connection with the previous drawings may be implemented
by various alternative arrangements of the logic
elements. Although such equivalent detailed
implementations may be used, as a matter of design choice,
the particular arrangement of very basic elements is set
forth in Figures ~3 through 54 in the interest of total
disclosure of the present invention.
Figure 53 illustrates the logic or the system
interface 621, shown more generally at Figure 51a. The
inputs to the system in-ter~ace are the system clock (SCLK)
8 9
-152-
and the biphase Manchester encoded data in (BPMIN). The
output to the system node is the biphase Manchester data
out (BPMOUT). The data in tBPMIN) is input through the
decoder logic 702 through two D flip flops and two divide
by four flip flops, and is output from the NRZ flip flop
as NRZ data (DIN). The decode circuit also drives the 0
clock (OCLK) which operates at 192 kHz. OCLK drives both
the NRZ data in and the data out passing through decoder
logic 714. Data in is communicated to the 25 bit shift
register 704 which operates as a frame synchronous detect
circuit. Shift register 704 detects the alternating
synchronization bit every frame time, i.e. every 24
bits. Comparator 706 compares the first and twenty fifth
bits of the data in and outputs a signal to the detect
flip flop in the synchronous logic 708. As long as output
of the detect flip flop remains active the MTC remains in
synchrol1ization with the data in. The remaining portion
of Figure 43 is the timing logic 710 which generates the
various timing signals used in the MTC. The four bit
counter in the center of the figure enables three timing
windows which are used to formulate the packet channel
enable (SEN), voice (channel 0) enable (VEN), data
(channel 1) enable EDEN). The synchronous output signal
(START) is generated at the upper left portion figure.
The data out signal (DATAO) which is generated in the
upper center of the figure is an OR of everything -that is
generating data in the system. The interrupt output
signal (IRQ) is active every 250 microseconds and operates
to synchronize the MTC with the incoming receive packet
channel data.
Figure 54 illustrates the packet channel receive
logic. This circuit functions to receive data from the 25
bit shift register in the system interface, track the CRC
status, and formulate the data into 8 bit bytes to be read
by the microprocessor. The input from the 25 bit shift
register, which is NRZ data delayed by 25 bits, (SR25) is
-153-
input to a detector which determines whether valid data is
being received. The signal bit active detector also
receives an input from the k bit flip flop which indicates
whether the k bit is active. If the k bit i8 active,
meaning that Jill data is being sent, then the NRZ data
will not be communicated to the microprocessor. The right
hand portion of the figure includes logic circuitry that
keeps track of certain status conditions and generates
signals corresponding to those conditions. The input data
ready (INT) signal indicates that data is ready for
communication to the microprocessor. The overflow error
(OER) slag indicates that there has been an overflow
condition. The end of message flag (OEM) indicates that
no further valid data is to be sent. The CRC error flag
(CER) receives information froln the CRC checking circuit
illustrated at Figure 55 and indicates if there has been
an error in the CRC checking. The underflow error flag
(UER) indicates that an incomplete message has been
received. The REGEN flag enables a bit window to allow
data to clock into the shift register 722 via AND gate
720, shown in the lower left portion of the figure.
Figures 55 and 57 illustrate the CRC checking logic
and the C~C generating logic respectively. The input to
the CRC checking circuit (DDLY) is input to a comparator,
US the output of which is input to the serial network of
shift registers at three different points. Both the CRC
checking circuit and the CRC receiving circuit operate in
accordance with the CCITT polynomial, X16+Xl2+X5+1. If
the received information is properly in accordance with
that standard the CRC error signal (CRCO) will remain
inactive. If the received signal is not in accordance
with that polynomial an error signal will be communicated
to Figure 54 and a CRC error will be indicated.
The circuitry of Figure 57 operates in the accordance
with the same polynomial. The data out (CDATA) is
commlmicated to a comparator simultaneous with its
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transmission. The CDATA signal is used to derive an XX0
signal which is communicated to the serial shirt register
network at several locations. The resulting signal (CP~D)
is appended to the output signal transmitted from the
MTC. When the resulting signal is received at the PLS it
will be checked to insure proper CRC generation, as
described in connection with Figure 55.
Figure 56 illustrates the CRC timing logic. The
microprocessor writes to the timing logic via the U32
buffer, in the upper left portion of the figure. T'nat
operation causes data to be output in the packet
channels. Information from the buffer is communicated the
to U33 8 bit shift register, from which it is output at 4
bits per frame until there is no more information being
written by the microprocessor. The packet data (CDATA) is
multiplexed with the CRC data in multiplexer U72, the
output of which is then multiplexed with a signaling flag
bit (FLG) such that the data is injected at the beginning
of the signaling channel each frame time for as long as
the message is active. The output signal (DATA0) serves
as the input to the flip flop which generates the DPM data
out as shown in the decoder circuit 714, at Figure 53~
The remaining circuitry of Figure 56 includes timing
circuitry to gate the ARC and packet data to the output,
as well as status flip flops. The active signal (ACT)
indicates that there is a message active that can be
output. The CRCLR signal initializes the CRC checker at
the beginning of a message. The status busy signal (SBSY)
indicates that the output channel is busy so that the
microprocessor cannot write a new byte until the SBSY
signal goes inactive. The SBSY signal is derived from the
internal timing which indicates whether the internal
buffer has been emptied.
Figure 58 illustrates the decoding logic for the
MTC. Sixteen addresses are decoded by the MTC. The
decoded signals are placed on an internal bus for use by
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the MTC's internal registers. Address 0 of the read
decoder, shown at the upper left portion of the figure is
SRDI, which is the incoming signaling packet channel
data. Thus, when the microprocessor reads address 0 it is
S receiving incoming packet data. Address 1 is the status
read (STRD) address provides the status of the packet
channel in and the packet channel out. KYRDl and KYRD2
addresses functions to read the telset keyboards.
Status register 724, shown to the right of the read
decoder, communicates status information to the
microprocessor. INT is the incoming packet data ready
bit. SBSY is the busy packet out bit. The remaining
inputs are monitors for the status of the incoming packet
channel. Those inputs include overflow (OER), CRC error
(CEX), end of message (OEM) and under-run (UER).
The display driver signal (SDPY) is generated from two
addresses from the read decoder and two addresses from the
write decoder. Among the other addresses on the write
decoder is SWR, which enables writing to the packet output
register. OPCLR clears all the timing circuits associated
with the incoming and outgoing serial bit streams in the
MTC. The OPCLR sig-nal is gated with an enable signal (EN)
to generate the PCLR signal synchronous with the system
clock, as shown in the lower left portion of the figure.
The signal GDWR is gated with the enable signal (EN) in
order to produce the signal SGN which enables writing to
the gain register. The clear status signal (CLRS) serves
to clear the packet status bits illustrated at Figure
54, The clear interrupt signal (CLRI) occurs when the
3~ microprocessor has performed a read operation after an
interrupt flag has become active.
Below the write decoder is further decoding circuitry
for the read and write circuitry. Also illustrated is the
Logic circuitry to generate the call waiting signal (CW),
which is a 600 Hz output used for a call waiting tone. To
the right of the figure is an 8 bit bidirectional buffer
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which is normally in the input mode. There are only two
pertinent read operations, which occur when the
microprocessor effects a status read and data read. Those
operations are accommodated via the STRD and SADI signals,
respectively.
Figures 59-64 all pertain to the circuit switch data
paths in the MTC. Shown more generally in connection with
Figure 41d. In Figure 59 the NRZ data in is communicated
on the DATAI line to one or both of the '1~4 shift
registers, depending upon the mode the MTC is operating
in. If the MTC is in the 120 kHz mode, both s'nift
registers will be loaded with 8 bits. At the end of the
frame the 164 shirt register will load into the 165
buffers. The 165 buffers are clocked by the PBX clock
rate (PBCLI). Thus, the incoming 192 kHz clock rate is
smoothed to whatever the PBX clock rate is. The outgoing
data is communicated at a continuous rate via the SPDTO
output. The signal VCMD enables the MTC to use channel
one as a voice channel by turning on the VCMD signal. In
so doing, the 192 kHz DATI signal is gated directly out on
the SPDT0 line and the clock out (PBCL0) would be a
function of the 192 kHz clock (DICLK).
Figure 60 illustrates part of the clear channel serial
rate conversion logic directed to outputting information
to the system interlace, or transmlssion to the QPLS.
The circuit is shown more generally at Figure 51(c), The
input to the circuit is labeled SPDTI, which may again be
8 or 16 bits depending upon whether or not the TO is in
the 128 kHz mode or not. The bits FB0 and FB1 are two
resister bits which configure a multiplexer arrangement to
arrange the incoming data such that the least significant
bit is in the proper location in the '374 register. In
view of the way t'nat the MTC affects variable bandwidth
transfer to the system node, i.e. not all of the
transferred bits necessarily have valid dates, the TO
must least significant bit justify the data transmitted to
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the node such that the valid data is contained within the
first bits transferred to the system node. The remaining
bits will comprise Jill data, which is transparent to the
receiving station, that operates at the same rate as the
transmit station. When the TO is configured or voice
mode operation the signal VCMD enables the SPDTI signal to
bypass the register circuitry and be communicated directly
to the output (DATO). As presently configured the node
will allocate one to four 8 or 16 bit spaces for
communications with the MTC. The '374 register will
accommodate the 1, 2, 4 or 8 bit modes. The 16 bit mode
is accommodated by the '374 register and the 8 bit, 164
register directly above.
Figure 61 illustrates some of the logic in the clear
channel asynchronous, synchronous and terminal rate logic
625, illustrated more generally at Figure 41d. The data
into the circuit is communicated on the SPDTO input line
to the 164 shift registers located in the center of the
Eigure. The number of bits loaded into the 16~ shift
registers is a function of the 4 bit counter connected to
the station inputs OCBOS, OCBlS, 1CB2S, and OCB2S, The
information in the 164 registers is communicated to the
194 registers and clocked out at the clock rate OACLO.
Thus, data is brought in at the PBCLK clock rate and is
output at the clock rate of the device (OACLO). In
asynchronous operation the stop bit is detected by the STT
flip flop at the upper left portion of the figure. The
character is then clocked into the 164 shift registers
previously described. In synchronous operation much of
the logic circuitry is omitted and the input SPDTO signal
is communicate to the XCTO output via the AND gate
network in the upper right portion of the figure. In the
PBX mode the output is selected from the SOD input to the
AND gate network which i9 derived from the 6 bit latch
3~ output MDO-MD~ as shifted through the 6 bit SLID shift
register in the lower center portion of the page. The
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output timing signal (XCLKO) is derived from the logic
circuitry shown in the lower right portion of the
figure. When in the PBX mode the timing signal PBCLK is
selected as the output timing signal. In the terminal
mode the signal ACLO is selected. The ACLO signal is
derived at Figure 64 in the drawings and is the product of
the timing checking circuitry used in the terminal mode.
The timing checking circuitry includes the 5 bit counter
shown at the center left portion of the figure which is
used to monitor the contents of the incoming data stream
to determine whether a proper number of stop bits are in
the input characters. If an incorrect number of stop bits
is detected the timing checking circuitry functions to
enable the slow clock (SSL) or the fast clock (FSL) as
described previously in connection with Figure 51(d). If
the incomin~s data contains the proper number of stop bits
the nominal clock rate signal (NSL) enables the ACLO
clock.
Figure 62 illustrates a portion of the clear channel
asynchronous, synchronous and terminal rate logic for
receiving data from a device and rate converting that data
for transmission to the circuitry illustrated at Figure
60. The circuitry at the upper left portion of the figure
is the asynchronous start bit detect circuit 800, the
output which is STRT. The input signal XTDI is also
communicated to the 164 shift registers 812 at the
terminal clock rate. The asynchronous mode at the signal
in the register 812 is then communicated to the 1~4
registers 816 and is output from the multiplexor network
818(b) at the PBCLO clock rate. In the synchronous mode
the output from the 164 shift registers is communicated to
the '165 s'nift register 814. The output from that shift
register is then communicated to the multiplexer 213a and
218(b) for output on the SPDTI line. The output from the
asynchronous shift register 8t6 is communicated to a '151
multiplexer which enables a correct number of bits to the
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multiplexer 818(b). In the presently preferred embodiment
the '151 multiplexer enables passage of between 7 to 12
bits in the asynchronous mode.
Figure 63 illustrates further decoding logic in the
MTC. The write decoder at the upper left portion of the
figure illustrates the decoder addresses for the signals
WR1-7. The '374 registers illustrate the various
addresses that can be written from the microprocessor to
set up particular data operations. The top most '374
~0 register begins with the address number 8 which correlates
to the terminal modem mode (TMM) that determines whether
the device's clock or the MTC clock is to be used. The
SAM signal is the synchronous asynchronous mode flag. The
LPO and LP1 bits are for the loop back channel 0 and loop
back channel 1 signals respectively. The TPX~ bit is the
terminal or PBX clock flag. RS0-2 are the 3 bits used to
select the asynchronous clock rate (ACLI) and the PBX
clock rate (PBCLK), illustrated at the right hand portion
of the figure.
In the second most '374 register the bits OCBOS, OCB1S
and OCB2S are used to determine the system side number of
characters. Similarly, the signals OCBT, OCBlT and OCB2T
detennine the character size on the terminal side. The
0128M mode is the 128 kHz flag. The VCMD bit is the voice
clear mode data flag. The FB0 and FB1 bits represent the
number of bits per frame that are beiDg used. The bits
UCL0, UCL1 and UCL2 determine the rate of the clock signal
UCLK. The bit UBN is the enable signal for the UCLK
signal. The bit PWDN is used to select a data multiplexer
and external circuitry.
Figure 64 illustrates t'ne logic of the output clock
generation signals. The three '374 registers on the left
hand portion of the figure are the preload registers to a
7 bit down counter. The three preload registers contain
the preload values to enable the fast clock, nominal clock
or slow clock to increase or decrease a nominal clock
2~
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rate, as previously described in connection with Figure
51(d)- The preload values in the '374 registers are
initialized by the microprocessor. The output of the 7
bit down counter is transmitted to a '151 multiplexer to
S enable selection of the ACL0 clock rate. The S clod
logic operates to double the clock doubler which is
communicated to the 7 bit down counter to obtain high
resolution of the counter. The '374 register at the lower
left portion of the figure is loaded according to the rate
of operation to indicate the number of stop bits between
synchronous terminal characters. The logic in the upper
right portion of the figure illustrates the signals
communicated between the codec and the MTC. The T sync
signal to the codec is the 128 ~Hz signal enabled by t'ne
voice enable signal (VEN). The data I signal is
multiplexed at the righthand portion of the Figure
according to whether or not the MTC is in the diagnostic
mode causing the loop back bit (LP0) to be active. If not
looped back the data I signal becomes the codec data in on
the RDD input. The signal from the codec is fed into the
MTC on the TDD input and becomes the DATA0 input to the
microprocessor.
The foregoing description represents the presently
preferred embodlment of the MTC. It should be understood
that features such as the data rates and the message
lengths described above are exemplary and do not represent
limitations on the invention. The message lengths, data
rates and other design criteria can be changed within the
scope of the invention, which is defined only by the claim
appended below.
VIDEO INTERFACE MODULE
The Video Interface Module (VIM) illustrated in Figure
65 is substantially similar in structure and operation to
the station interface module. The VIM 63, illustrated at
Figure 6(a), provides a structure for incorporating
digitized video communication capacity to the system. VIM
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63 differs from the construction of the SIM, sho~m at
Figure 10, in that the QPLS's do not attach to the
transmit and receive highways, but rather to t'ne alternate
transmit and receive highways in the general purpose
bus. A second difference between the construction of VIM
63 and the SIM is t'nat the VIM includes dual QPLS chips
243 operating in a highway-to-highway switching mode,
carrying eight channels from the receive transmit highways
to the alternate transmit and receive highways and the
general purpose bus. T'ne control processor section 11~ is
similar to that found in the SIM or the NIM and functions
in a similar manner.
The VIM is used in fully redundant (i.e., dual ring)
systems where dual counter directional network loops are
employed and each node has two NIM's. Typically, the
forward ring could carry circuit switched voice and data,
and the backward ring could carry high-speed video
channels operating at 488 kbps~ In this manner the
backward ring could carry seventy-two channels of 448 kbps
digitized video that is accessible through the NIM on the
alternate transmit and receive highways. The QPLSs,
operating in high-speed mode, can switch 764 kbps channels
for an aggregate of 448 kbps to the peripheral loop. A
voice channel may be switched to and from the transmit and
receive highways to the alternate highway and receive
highways by the dual QPLS. In this manner each VIM
supports eight integrated work stations with 44~ kbps of
digitized video, 64 kbps of digitized voice, and a 32 kbps
packet channel
