Note: Descriptions are shown in the official language in which they were submitted.
~2~ 0;~4
IMAGE SIGNAL TRANSMITTING SYSTEM
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to an image signal
transmitting system for giving information, such as
letters and graphic patterns produced by a CPU, to a
display such as a CRT and, more specifically, to an image
signal transmitting system capable of giving image signals
to a display so that images are displayed in a plurality
of separate display divisions in the display screen of a
display.
Description of the Prior Art
An image signal transmitting system which provides
image signals to be displayed in a plurality of separate
display divisions in the display screen of a display is
disclosed, for example, in Unexamined Patent Publication
(Kokai) No. 58-35592.
To enable the prior art to be described with the aid
of a diagram, the figures of the drawings will first be
listed.
Fig. l is a block diagram of an image signal
transmitting system according to the present invention;
Fig. 2 is a logical circuit diagram showing the
details of a priority rearranging circuit and a data
selecting circuit employed in the image signal
transmitting system of Fig. l;
024
Figs. 3a and 3b are diagrammatic illustrations of
exemplary patterns formed by the image signal transmitting
system of the present invention on a display screen; and
Fig. 4 is a block diagram of a conventional image
signal transmitting system.
Fig. 4 is a block diagram of such an image signal
transmitting system. Referring to Fig. 4, there are shown
image memories la, lb and lc, a vertical division assigning
register 2, a horizontal division assigning register 3, a
vertical scanning position counter 4, a horizontal scanning
position counter 5, a vertical position detecting circuit
6, a horizontal position detecting circuit 7 and a
selecting circuit 8.
In this image signal transmitting system, the vertical
position detecting circuit 6 compares the output signal of
the vertical scanning position counter 4 and the output
signal of the vertical division assigning register 2 to
detect the vertical position of a display division in the
display screen, while the horizontal position detecting
circuit 7 compares the output signal of the horizontal
scanning counter 5 and the output signal of the horizontal
division assigning register 3 to detect the horizontal
position of the display division on the display screen.
Then, the selecting circuit 8 selects one of the image
memories la, lb and lc according to the detection signals
of the vertical and horizontal position detecting circuits
6 and 7, and then provides the image signal of the
selected image memory.
-- 2 --
"~
Jo~
The conventional image signal transmitting system
divides the display screen in the above-mentioned manner
by means of the division assigning registers 2 and 3, the
scanning position counters 4 and 5, and the position
detecting circuits 6 and 7. When a display screen dividing
pattern is required to be changed, the contents of the
division assigning registers 2 and 3 must be rewritten.
Accordingly, it has been impossible to cnange an existing
divisional pattern shown on the display screen for a new
one without manipulating the data of the existing
divisional pattern displayed on the screen.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an
image signal transmitting system capable of easil~ changing
an existing divisional pattern for a new one without
manipulating the data of the images of the existing
divisional pattern.
According to the principle of the present invention,
each one of the image data read from a plurality of image
memories is given to a display according to a priority
given to a data effectiveness signal corresponding to the
image data. Although each image memory has a preset
priority, the preset priorities are rearranged by a
priority rearranging circuit according to external
instructions.
The invention consists of an image signal transmitting
system for feeding image data corresponding to a plurality
of images including letters and/or graphic patterns to
-- 3 --
y ~ ~
~ 0~ 4
display a divisional pattern on a display, which comprises:
a plurality of image memories storing different image data
and data effectiveness signals, corresponding to the
respective images; a priority setting circuit for assigning
predetermined priorities to image data read from the
respective image memories and to the corresponding data
effectiveness signals; a priority rearranging circuit
which receives the data effectiveness signals from the
priority setting circuit and rearranges the priorities of
the data effectiveness signals according to external gate
signals; and a data selecting circuit which selects image
data corresponding to one of the images and gives the
selected image data to the display, according to the data
effectiveness signal having the highest rearranged
priority.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to Fig. 1, an image signal transmitting
system according to the present invention comprises, to
simplify the description, three image memories lla, llb and
llc. However, the number of the image memories may be an
optional number not less than two.
A priority setting circuit 12 is connected to the
image memories lla, llb and llc to receive image data 21a,
21b and 21c, and data effectiveness signals 22a, 22b and
22c from the image memories lla, llb and llc, respectively.
,~
024
The priority setting circuit 12 assigns predetermined
priorities to the image data and the corresponding data
effectiveness signals, respectively. The priority
setting circuit 12 gives image data 51a, 51b and 51c to a
data selecting circuit 14, and gives data effectiveness
signals 52a, 52b and 52c each having a priority to a
priority rearranging circuit 13. The priority rearranging
circuit 13 has three gates which are controlled by external
gate signals 23a, 23b and 23c. One of the three data
effectiveness signals 52a, 52b and 52c given to the
priority rearranging circuit 13 allowed to pass the gate
is fed to a data selecting circuit 14 to specify the data
among the three image data 51a, 51b and 51c to be selected
by the data selecting circuit 14.
Fig. 2 illustrates the details of the priority
rearranging circuit 13 and the data selecting circuit 14.
The priority rearranging circuit 13 includes three AND
gates 41, 42 and 43 which are controlled by gate signals
23a, 23b and 23c, respectively. The data effectiveness
signals 52a, 52b and 52c are given to the AND gates 41,
42 and 43, respectively. The data selecting circuit 14
comprises AND gates 31, 32 and 33, an OR gate 34, AND
gates 35 and 36 and inverters 37 and 38.
The first, second and third priorities are assigned
to the image data 51a, 51b and 51c, or the image data 51a,
51b and 51c have the first, second and third priorities,
respectively, and the first, second and third priorities
._
-- 5 --
024
are assignea to the data effectiveness signals 52a, 52b
and 52c. At this stage, the image data 51a, 51b and 51c
and the data effectiveness signals 52a, 52b and 52c are
not regarded as those stored in the image memories lla,
llb and llc, respectively, and hence the image data 51a,
51b and 51c and the data effectiveness signals 52a, 52b
and 52c are treated on a conception that the image data
51a, 51b and 51c and the data effectiveness signals are
data having the first, second and third priorities and
the corresponding data effectiveness signals, respectively.
Figs. 3a and 3b show an exemplary pattern including
divisional images displayed on a display screen by the
image signal transmitting system of the present invention.
In Fig. 3a, it is assumed that images A, B and C
correspond to image memories lla, llb and llc,
respectively. The truth-value of the data effectiveness
signal 22a of the image memory lla is "1" only within
the region of the image A, the truth-value of the data
effectiveness signal 22b of the image memory llb is "1"
only within the region of the image B including a portion
overlapping the region of the image A, and the truth-value
of the data effectiveness signal 22c of the image memory
llc is "1" within the region of the image C, namely, the
entire region.
The priorities of the data effectiveness signals 22a,
22b and 22c of the image memories lla, llb and llc are
decided by the priority setting circuit 12 under the
-- 6 --
' - ~
0~4
control of a CPU, now shown, or the like. In the case
shown in Fig. 3a, the image A > the image B > the image C
in priority. Therefore, the highest priority, the
secondary priority and the lowest priority are given to
5 the data effectiveness signals 22a of the image memory
lla, 22b of the image memory llb and 22c of the image
memory llc, respectively. In this state, when the
divisional images are displayed in a pattern 3A as shown
in Fig. 3a, the values of the gate signals 23a, 23b and
23c are "1". When the pattern 3A is required to be
changed for a pattern 3B shown in Fig. 3b, the gate
signals 23a, 23b and 23c corresponding to the images A,
B and C are set at "1", "0" and "ln, respectively. This
gate signal setting operation will be described more
specifically with reference to Fig. 2. With particular
reference to lines Q and m shown in Figs. 3a and 3b, in
the pattern 3A, only the data effectiveness signal 52c
of the lowest priority is "1" in sections [a, bl and
,
le, f], while the data effectiveness signals 52a and 52b
of the highest and the secondary priorities are "0", and
all the gate signals 23a, 23b and 23c are "1". Therefore,
the outputs of the AND gates 41 and 42 are "0", while the
output of the AND gate 43 is "1". Accordingly, the
outputs of the inverters 37 and 38 are "1", the output of
the AND gate 35 is "0", and the output of the AND gate 36
is "1". Consequently, only the AND gate 33 among the AND
gates 31, 32 and 33 is open, and hence the image data 51c
~.,
-- 7 --
024
of the lowest priority that passed the AND gate 33,
namely, the image data 21c of the image memory llc,
appears at the output of the OR gate 34.
In a section ~b, c]~ the data effectiveness signal
52b of the secondary priority and the data effective signal
52c of the lowest priority are "1", while the data
effective signal 52a of the highest priority is "0".
Since all the gate signals 23a, 23b and 23c are "1", the
AND gate 41 is "0" and the AND gates 42 and 43 are "1".
Accordingly, the output of the inverter 37 is "1", the
output of the inverter 38 is "0", the output of the AND
gate 35 is "1" and the output of the AND gate 36 is "0".
Consequently, only the AND gate 32 among the AND gates
31, 32 and 33 is open, and hence the image data 51b of
the secondary priority that passed the AND gate 32,
namely, the image data 21b of the image memory llb,
appears at the output of the OR gate 34.
In a section [c, d], all the data effectiveness
signals 52a, 52b and 52c are "1" and all the gate signals
23a, 23b and 23c also are "1". Therefore, all the outputs
of the AND gates 41, 42 and 43 are "1". Accordingly, the
outputs of both the inverters 37 and 38 are "0".
Conse~uently, only the AND gate 31 among the AND gates
31, 32 and 33 is open, and hence the image data 51a of
the highest priority that passed the AND gate 31, namely,
the image data 21a of the image memory lla, appears at the
output of the OR gate 34.
0~4
In a section [d, e], the data effectiveness signal
52a of the highest priority and the data effectiveness
signal 52c of the lowest priority are "1", while the
data effectiveness signal 52b of the secondary priority
is "0". Since all the gate signals 23a, 23b and 23c are
"1", the outputs of the AND gates 41 and 43 are "1" and
the AND gate 42 is "0". Accordingly, the output of the
inverter 37 is "0", the output of the inverter 38 is l'l"
and the outputs of the AND gates 35 and 36 are "0".
Consequently, only the AND gate 31 among the AND gates
31, 32 and 33 is open, the hence the image data 51a of
the highest priority that passed the AND gate 31, namely,
the image data 21a of the image memory lla, appears at
the output of the OR gate 34.
Thus, the image data of the image memory llc, the
image memory llb and the image memory lla are displayed
in the sections [a, b] and [e, f~, in the section ~b, c]
and in the section [c, el, respectively. Consequently,
the divisional pattern 3A is displayed on the display
screen.
The pattern 3B shown in Fig. 3b will be described
hereinafter.
In sections [g, h] and [k, p], only the data
effectiveness signal 52c of the lowest priority is "1"
and the rest are "0". Since the gate signals 23a and 23c
are "1" and the gate signal 23b is "0", the AND gates 41
and 42 are "0" and the AND gate 43 is "1". Accordingly,
0~4
the outputs of the inverters 37 and 38 are "1", the
output of the AND gate 35 is "0" and the output of the
AND gate 36 is "1". Consequently, only the AND gate 33
among the AND gates 31, 32 and 33 is open, and hence the
image data 51c of the lowest priority that passed the AND
gate 33, namely, the image data 21c of the image memory
llc, appears at the output of the OR gate 34.
In a section [h, i~, the data effectiveness signal
52b of the secondary priority and the data effectiveness
signal 52c of the lowest priority are "1" and the data
effectiveness signal 52a of the highest priority is "0".
Furthermore, since the gate signals 23a and 23c are "1"
and the gate signal 23b is "0", the AND gates 41 and 42
are "0" and the AND gate 43 is "1". Accordingly, the
outputs of the inverters 37 and 38 are "1", the output
of the AND gate 35 is "0" and the output of the AND gate
36 is "1". Consequently, only the AND gate 33 among the
AND gates 31, 32 and 33 is open, and hence the image data
51c of the lowest priority that passed the AND gate 33,
namely, the image data 21c of the image memory llc,
appears at the output of the OR gate 34.
In a section [i, j], all the data effectiveness
signals 52a, 52b and 52c are "1", the gate signals 23a
and 23c are "1" and the gate signal 23b is "0", hence the
AND gates 41 and 43 are "1" and the AND gate 42 is "0".
Accordingly, the output of the inverter 37 is "0", the
output of the inverter 38 is "1" and the outputs of both
-- 10 --
12~0~4
the AND gates 35 and 36 are "0". Consequently, only the
AND gate 31 among the AND gates 31, 32 and 33 is open,
and hence the image data 51a of the highest priority that
passed the AND gate 31, namely, the image data 21a of the
image memory lla, appears at the output of the OR gate 34.
In a section lj, kl, the data effectiveness signal
52a of the highest priority and the data effectiveness
signal 52c of the lowest priority are "1" and the data
effectiveness signal 52b of the secondary priority is "0".
Since the gate signals 23a and 23c are "1" and the gate
signal 23b is "0", the AND gates 41 and 43 are "1" and
the AND gate 42 is "0". Accordingly, the output of the
inverter 37 is "0", the output of the inverter 38 is "1",
and the outputs of the AND gates 35 and 36 are "0".
Consequently, only the AND gate 31 among the AND gates
31, 32 and 33 is open, and hence the image data 51a of
the highest priority that passed the AND gate 31, namely,
the image data 21a of the image memory lla, appears at
the output of the OR gate 34.
Thus, in the sections [g, i] and [k, p] and in the
section [i, k], the image data 21c of the image memory
llc and the image data 21a of the image memory lla are
displayed. Consequently, the divisional pattern 3B shown
in Fig. 3B ls displayed on the display screen.
As has been described hereinbefore, the divisional
pattern 3A can be changed for the divisional pattern 3B
only by setting the truth-value of the gate signal 23b
-- 11 --
~5~024
at "0" without requiring the change of priority.
Accordingly, the display pattern can be changed from the
divisional pattern 3B to the divisional pattern 3A simply
by setting the truth-value of the gate signal 23b at "1".
The embodiment as provided with three image memories
has been described hereinbefore, however, the number of
the image memories need not necessarily be limited to
three. Furthermore, the circuit constitution shown in
Fig. 2 is for example only and is not limited thereto.
The image data itself may be used as the data effective-
ness signal. When the image data is used as the data
effectiveness signal, an image consisting of a plurality
of images superimposed over another is displayed on the
display screen.
The superimposition of images may be easily understood
when considered with reference to the display of letters
over a background picture. As is apparent from the
foregoing description, in the embodiment, the data
effectiveness signal is explained as representing a
rectangular shape. In this case, the actual display is
a window shape as shown in Fig. 3. When the data
effectiveness signal represents the same shape as that
represented by the image data, for example, when the
image data is a letter data and the data effectiveness
signal represents the same shape as that represented by
the letter data, the shape represented by the data
effectiveness signal is can be most efficiently displayed
- 12 -
125~024
by using the image data as the data effectiveness signal,
and thereby the output data is changed according to the
shape of the letter, a portion of the background picture
corresponding to the letter is erased to display the
letter therein, which is called generally as
superimposition.
As apparent from the foregoing description,
according to the present invention, data effectiveness
signals are provided by image memories, respectively, and
priorities are given to the data effectiveness signals to
use the data effectiveness siqnals as data selecting
signals; and the transmission of the data effectiveness
signals is controlled by gate signals independent of
priority setting. Accordingly, the divisional pattern
: 15displayed on a display screen can be easily changed
without manipulating the priority setting.
: - 13 -
.~
