Note: Descriptions are shown in the official language in which they were submitted.
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~ACKGROU~D OF THE INVENTION
Field of the Invention:
This invention relates generally to a digital
signal transmitting and receiving system and, more
specifically, to a system for use in transmitting a digital
~ignal such as might be derived by digitally converting an
analog ~tereo signal, announcement ~ignal, facsimile data
signal, or a computer game program, on a ~able television
transmi~si~n line using a single, unused television channel
havinq a bandwidth of approximately 6MHz~.
BRI};F DESCRIPTION OF THE DRAWINGS
Fig. 1 is a schematic in block diagr~m form of a
~igit~l data tran~itting cystem using ~ cable television
tran~micsion line suitable for u~e with the present
invention;
Fig. 2 is a digital signal receiving ~ystem
employing a cable television transmission line suitable for
use with the present invention;
Figs. 3A and 3B represent digital signal formats
used in a digital signal transmitting ~ystem according to
the present invention;
~ igs. 4A-4D ~chematically represent digital signal
formats for use in an embodiment of a digital ~ignal
transmitting system according to the present invention;
~ ig. 5 is a block diagram of a digital signal
generator according to an embodiment of the present
invention;
Fis. 6 is ~ block diagram of a digital signal
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generator ~ccording to another embodiment of the present
invention;
Fig. 7 is a block diagram of a digital signal
generator according to another embodiment of the present
invention;
~ ig. 8 is a block diagram of a digital signal
generator according to another embodiment of the present
invention;
~ ig. 9 is a block diagram of a digital signal
generator acoording to a another emhodiment of the present
invention;
Fig. 10 iE a ~lock diagram of a demodulator for
u8e ~n the present ~nvention;
Fig. 11 is a block diagram o~ a another embodiment
of a demodulator for use in the present invention;
~ igs 12A-12~ are timing waveform diagrams showing
the operation of the demodulators of Figs. 10 and 11; and
~ ig. 13 is a block diagram of an embodiment of zn
addressing circuit according to the present invention;
Description of the Background:
In order to better understand the signal
transmitting system of this invention an overall ~ystem
suitable for employing the present invention is first
described. The present invention is intended to employ a
cable television ICATV) transmission line and ~ig. 1 shows a
digital signal transmitting system for use with such
transmission line. Input terminals 201-204 are arranged to
lZ513521
rec~ive nnalog ~ignals, which might be analog stereo
signals, and such input ~ignals are fed to analog-to-digital
convertors 207-210, re~pectively. The resultant digital
~ignals from analog-to-digital co~vertors 207-210 are then
fed to a multiplexer 213 that produces at its outputs two
~erial data streams that represent the four input ~ignals
having been time division multiplexed. Time division
multiplexing being a known approach to ~ransmitting a number
of ~ignals over a commmon path by using different time
inter~ or ~he transmission of the-intelligence of each
~essage ~isnal. Then, the time division multiplexed digital
~ignals from multiplexer 213 are fed to a filter 214, which
i~ provided to ~uppress intersymbol interference that cau~es
code ~rror. Filter 214 may advantageously comprise a binary
transversal filter having tap coefficients adjusted ~o that
the modulation ~ignal 6atisfies Nyquit~' 8 first ~riterion.
The output of $ilter 214 is fed to a four-level convertor
215 which ~ay be thought of as operating as a
digital-to-analog conver~or so that it converts the input
digital ~ignals to a four-level, base-band ~ignal. This
four-level analog signal produced by four-level convertor
215 has four different amplitude values ~anging from zero to
three, which are respectively expressed as ~o" + ~on = no~
no ~ ~ln ~ ~ 0" ~ ~2", and ~ n ~ ~3~. This
pseudo-analog output ~ignal is fed to an
amplitude-modulation (AM) modulator 216 wherein it AM
modulates an intermediate fre~uency signal (IF~ having a
frequency of 38.9M~z, for example, supplied by oscillator
-- 3 --
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217. The output of the AM modulator 216 is fed through a
vestigial side-band filter 218 to a mixer 219. This
vestiyial side-band modulation is the same as in
conventional television transmissions. Thus, the fil~ered
signal is mixed in mixer 219 with an RF ~ignal (fc + fif)
supplied by a local oscillator 220. The output signal of
mixer 219 represents a modulated signal havinq a carrier
frequency fC of 97~25M~z, for example, and ~uch output
~ignal is fed through a bandpass filter 221 to output
terminal 222 as the modulated, fiystem output ~ignal, the
bandwidth of which i~ limited to 6M~z~ The output Eignal
~eveloped at output terminal 222 is then fed to a head end
of a CATV system (not shown~. Thus, the original input
~ignals are placed in an unused television channel on a
conventional cable television transmission line and require
no more bandwidth (6MHæ) then a typical 6ingle television
channel.
Fig. 2 shows a system for ~receiving" a signal as
might be placed on the CATV transmission line by the sytem
of Fig. 1, in which the modulated ~ignal transmitted through
the transmission line of the CATV ~ystem is supplied at
input terminal 231 to a wide bandwidth receiver front end
232 where it is amplified and converted to an intermediate
frequency tIF) signal of 58.7 ~z, for example, and this
intermediate frequency rignal is ~upplied to a phase-locked
loop tPLL) synchronous detector 233, which functions as an
~M detector, so thPt the four-level, base-band signal, as
produced ~y the four-level ~onvertor 215 of Fig. 1, is
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demodulated. An automatic gain control (AGC) circuit 246 i5
provided with an input from PLL detector 233 and produces an
output control signal fed to front end 232 to prevent
overloadin~ of the front end amplifier. The output ~ignal
from the phase-locked loop detector 233 is fed to a level
comparator 234, which operates an a kind of
analog-to-digital convertor, by demodulating the detected
6ignal and produces a series digital ~ignal having four
po~sible values, ~0", ~ 2W, and ~3", on the basis of
whether the output signal from the PLL detector 233 exceeds
a referenc2 level, as represented by a ~o-called eye
pattern. The eye pattern i~ generally known in data
tr~nsmission by an oscilliscope display of the detector
voltaqe waveform in a data modulator/demodulat2r. ~his
pattern gives a convenient ~epresentation of cross-o~er
distorti~n and can be derived in the known fashion, based
upon the overall ~reque~cy characteristics of the ~ystem and
the relationship thereto between the Nyquist frequency and
the transmission capacity of the system in bits per second.
The digital ~ignal thus essentially demodulated by
level comparator 234 is fed to a demultiplexer 235. Also
produced by the level comparator 234 is a bilevel
synchronizing ~ignal fed to a clock reproducing circuit 245
that produces a bit clock ~ignal applied to demultiplexer
235 to control the output thereof in the appropriate
time-division manner. Also produced by clock reproducing
circuit 245 is a synchronizing signal fed to both the
automatic gain control circuit 246, as well as to
125~3S~l
demultiplexer 235. Demultiplexer 235 then produces a
plurality of digital signals in a time-division manner that
are supplied, respectively, to digital-to-analog (D/A)
convertors 239 - 242, so that analog signals corresponding
to the original input signals as applied at inputs 201 -
204, (Fig. 1) ar~ respectively developed at output terminals
243 - 246.
Nevertheless, even though the system is described
hereinabove would appear to be B workable and feasible
system in actuality such ~ystem is not avaiable for use in a
effective and usable fcrm, principally because of the lack
of an economical method of addressing the receiver
ter~inal
The problem being that in a transmission system,
such as cable television, in which the signal i8 transmit~ed
through a cable, that is, hard wired, at the receiving side
at which-the ~ignals are being distributed there may be
fewer than several hundred receivers, or there may be up to
~everal tens of thousands of receivers. In other words,
there is a wide spread in the number of receiving units that
may be connected to the cable television transmission line.
In the proposed systems, each of the receiver terminals
usually has an individual address signal and the transmitter
side then transmits a control signal corresponding to each
address number, wherein the receiving state of each receiver
terminal can be controlled.
In the systems proposed to use cable television
tranmission lines as outlined above, the control signal that
12S85;~1
corresponds to each address is formed as a bit series, which
can cover the maximum number of receiver terminals and in
most cases this involves a bit series of approximately 20
bits. The control signal used ~o perform such addressing is
then transmitted using a ~pecial address network line that
is different from the data network line. Accordingly, if
~uch address network line is designed to permit it to
accommodate a ~y~tem having a large number of receiver
terminals, for example, ranging from ~everal tens of
thousands to ~everal hundred-thousands, then this address
network line will be uneconomical and will be too
Eophistica~ed and expensive for systems having a
substantially fewer number of ~erminal receivers. On the
other hand, if the address network line i8 designed to
accommodate a system havin~, for example, less than several
hundred terminals then ~uch address network line is almost
unusable when applied to a ~ystem having a subt2ntially
greater number of receiver terminals and, thus, the address
network lines must be increased correspondinsly.
Accordingly, as described above, while the concept
of a system for transmitting digital signals on a cable
television transmission line is feasible, the data
addressing s~stem is not available such that the address
network lines need r,ot be changed in accordance with the
scale of the Eystem, in order to eliminate the redundancy
and uneconomical provision of more address network lines
than required for the smaller size system. Furthermore,
because special address network lines must he provided, the
l'~S8SZl
data ~ddressing system becomes complex in its circuit
arrangement and is thereby expensive in view of the
associated manufacturing costs.
OBJECTS AND SUMMARY OF THE INVENTION
-
Accordingly, it is an object of the present
inventi~n to provide an improved digital signal transmitting
and receiving ~ystem that can overcome the above-noted
~hortcomings inherent in the prior art.
It is another object of the present invention to
provide a digital signal ~ransmitting and receiving system
for traDsmitting a digital audio signal or digital data
~ignal using the transmission line of a cable television
network.
It is a further object of the pre~ent invention to
provide a digital ~ignal transmitting and receiving system
suitable for transmitting digital audio signals or digital
data signals in which a large number of receiver terminals
of a cable television system can be addressed without
requiring ~pecial addressing ~etwork lines~.
~ ccording to one aspect of the invention a digital
signal transmitting system is provided including a circuit
generating digital word signals in a first mode in which
each of the signals consists of a word synchronizing signal,
and data signals having a first bit code znd being sampled
at a first sampling frequency and a circuit for generating
digital word signals in a ~econd mode, each of the word
~ignals in the second mode consisting of a word
~ynchronizing signal ~nd data ~ignals having a second bit
t 1;2S8~21
code and being sampled at a æecond sampling frequency and a
selective transmitter that selectively transmits the first
mode of digital word cignals and the second mode of digital
word signals through a transmission line of a cable
television æystem.
According to another aspect of the present
invention a digital æignal receiving system is provided that
includes a circuit ~o receive digital æignals in a first
mode in which the first mode digital æignals consist of a
word ~ynchronizing ~ignal, a first æerYice bit æignal, and
data signals having a firæt bit code and being æampled by a
first sampling freguency and for receiving a æecond mode of
digital word ~ignals, each consisting of a word
synchr~nizing signal, a ~econd service bit æignal, and data
. . _ . . .
~ignal~ including second bit codes and being æ2mpled at a
~econd æampling frequency. ~ ~emodulator is connected to
the signal input terminal of the receiver and latches the
first mode of ~he digital word æignals and converts the
digital word ~ignals to analos signals. A second
demodulator is provided that is connected to the signal
input terminal of the receiver and latches the second mode
of digital word ~ignals and also converts such signals into
analog signals. A control æystem is provided that controls
the mode of the first and second demodulators in order to
æelectively enable one or the other in response to a mode
control æignal.
In yet another em~odiment of the invention the
transmi~er and receiver are combined into a complete system
12~85;2~
in which a single transmitter can provide digital data for a
plùrality of receivers and ~uch plurality of receivers may
be accessed or addressed using only the cable television
transmission line over which the actual data signals are
transmitted~
The above and vther objects, features, and
advantages of the present invention will become apparent
from the following detailed description of illustrative
embodi~ents thereof to be read in conjunction with the
~ccompany~ng drawings.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
~ hile Figs. 1 and 2 have been described
hereinabove as being exemplary of digital data transmission
and receiving systems the present invention as it relates to
the addressing network is described in relation to Fiss. 3
through 13 and, in particular, Figs. 3A and 3B represent a
data format according to the present invention. In Fig. 3A,
one frame i8 ~hown as being formed of 256 words, which at
the preferred transmission rate corresponds to 5.81ms. Each
frame begins with a frame synchronizing signal FS formed of
eight bits and is followed by a service bit word of four
bits and a first data word W0 of 156 bits. Thereafter, are
the remaining 255 data words, Wl to h'255, each word being
formed of 156 bits, each beginning with word synchronizing
signals WSl to WS255 and each being formed of eight bits,
and ~ervice bit words SBl to SB255, each being formed of
four bits, respectively. Note that the frame
synchronizing signal FS also serves as the word
-- 10 --
~2S8SZ~
cynchronizing signal (WSO) for the first data word WO.
Fig. 3B represents one of the 256 words of a frame
and, as shown therein, the eight bits of the ~ynchronizing
signal SYNC are at the beginning of the word followed by the
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four service bits and then the data word is made up of four
data channels, CHl - CH~, each data channel having a data
length of 32 bits and a sampling frequency of 44.lRHz, and
an error correction code ECC. An error correction code is
added at each of the respective data channels CHl - C~4 and
may comprise a Bose-Chaudhuri-Hocquenghem (BCH) code or
Extended Hamming Code, each having a length of seven bits.
Figs. 4A - 4D illustrate data ~orma$s for a
plurality of different operating modes of $he present
invention and, ~pecifically, Fig. 4A represents a first mode
~A1 in which 32-bit data represents a stereo digital audio
signal such that a left channel stereo signal L includes 16
bits and a right channel stereo signal R includes the
si~ilar 16 bits. This l6-bi~ data format is based upon a
sampliny frequency of 44~lKHz and is the ~ame data forma~ as
the presently available compact audio disc (CAD), which is
fast becoming a very popular music source for high quality
stereo music progxams.
Fig. 4B represents a second mode IB) in which the
data format of 32 bits are divided into four sets of eight
bits and can represent two channels of stereo signals La, Ra
and Lb, Rb. This format provides data suitable for
multichannel stereo music, not quite of the extreme high
quality of mode A represented in Fig. 4A. The quality of
sound according to mode B is the equivalent to, or better
than, conventional FM broadcasting.
Another mode (C) is represented in Fig. 4C, in
which an 8-bit data format is provided and in which the
sampling frequency of 44.lKRz of Figs 4A and 4B is halved
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to provide a supplying frequency of 22.05KHz. This
results in a data format that can provide eight monaural
channels a to h which are suitable for monaural voice
service, such as news, weather forecasts,
communications,and the like. Mode (~) is represented in
Fig. 4D and is a combination of modes (B) and (C) and can
be used to transmit one high fidelity stereo program and
four monaural audio programs. In such case, the 8-bit
stereo channels employs a frequency of 44.lKHz resulting
in two channels of eight bits, each intermixed with four
monaural mode channels, having a frequency of 22.05KHz.
The mode represented in Fig. 4D realizes a plurality of
modes within a single data channel and, thus, provides an
elaborate service capability. Note that in Figs. 4A-4D
no attempt is made tolshow the exact time relationship
between the various modes, and the various modes in these
Figs. are not drawn to scale.
There are twenty five different combinations of
the above-described modes, that is, twenty five different
systems can be specified simply by altering the
programming of both the transmitting and receiving sides,
without modifying the hardware. Nevertheless,
considering a data output system according to
combinations of these modes in which the sampling
frequency iæ either 22.05KHz, or 44.lKHz, the data length
is either eight bits or sixteen bits and the signal
system is either monaural or stereo, then eight different
mode combinations can be tabulated. These are set forth
in the following Table I.
TABLE I
signal transmission _ _ _ ~
system S S S S M M M M
data length 16 16 8 8 16 16 8 8
~ _, __._ ___ ~ _._.~. ___ _._ ____
sampling frequency 4 2 4 2 4 2 4 2
. - _ ._ . _ __
mode Sl64 Sl62 S84 S82 Ml64 Ml62 M84 M82
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As seen in Table I, letters S and M designate
stereo mode and manaural mode, respectively, reference
numerals 4 and 2 designate fiampling frequencies of 44.lKHz
and 22.05KHz, respectively, and the bottom row containing
notations S162, S84, S82, M164, M162, M84, M82 designate
different modes that are formed by combining the signal
system, the data length, and the sampling frequency. For
example, S164, indicates a mode wherein the signal is a
stereo signal, the data length is six~een bits, and the
sampling frequency is 44.lRHz, while M82 indicates a mode in
which the ~ignal is monaural, the data length is eight bits,
and the sampling frequency is 22.05KHz. The indications
representing the other modes are similarly deduced.
Encoders suitable for generating the various modes
as described above in relation to ~igs. 4A-4D and in Table
I, are shown in Figs. 5 through 9 and, of the above
different modes sho~n in Table I, the fundamental m~des
~hereof are S164, S84, S82, and M82 and, accordingly, an
example of an encoder corresponding to each of such
fundamental modes is described hereinbelow.
Fig. 5 is a block diagram of an encoder for
transmitting the S164 mode of Table I in which 32 bits of
one data channel are divided into left and right channel
stereo signals of sixteen bits each, with the sampling
frequency of 44.lKHz. This is the mode represented in Fig.
4A hereinabove. In Fig. 5, a left channel audio analog
signal L is applied at input terminal 1 and a right channel
analog signal R is supplied to input terminal 2, and the
thus supplied analog signals are fed to respective
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analog-to-digital convertors (A/D) 3, 4 in which they are
converted to di-gital signals based upon a sampling frequency
of 44.1~Hz. The resultant digital signals are then the
sixteen bit data words as shown in Fig. 4A. The respective
digital signals from A/D convertors 3 and 4 are fed to a
parallel-to-serial convert~r (P/S) 5, wherein they are
converted from two parallel signals to a serial signal,
which is developed at output terminal ~ as the data output
signal. Subsequently, this ~erial data ~ignal at output
terminal 6 can be further processed in accordance with any
specific or particular use requirement, for example, when
this data output signal i8 intended to be further
transmitted using the transmission line of the cable
television system the output data signal is amplitude
modulated using the vestigial side-band system, as done in
tandard television systems, and then transmitted to the
appropriate receiving side at the customer location.
Fig b is a block diagram illustrating another
example of an encoder and, ~pecifically, an encoder
corresponding to the S84 mode, which as set forth
hereinabove is a fundamental mode of this system, in which
32 bits of one data channel are divided into four segments
of eight bits, representing two left and two right stereo
channel ~ignals having a sampling frequency of 44.lKHz. The
input terminals for the left channel audio analog signals La
and Lb are provided at 11 and 12, while the right channel
analog signals Ra and Rb are supplied, respectively, to
input terminals 13 and 14. The analog signals thus applied
are fed to respective A/D convertors 15-18 in which they are
~ SO2021
l'~S85Zl
converted based upon a sampling signal ha~ing a frequency of
44.lKHz and thereby produce digital signals each data length
of which is eight bits, as shown for example in Fig. 4B.
These data signals in this "B" mode are then fed to a
parallel-to-serial convertor 19 and are developed into a
serial bit stream made available at output terminal 20.
Again, this serial digital output signal can be modulated in
accordance with the known televi~ion techniques and placed
on a transmission line of a C~TV system.
An encoder for producing the "C~ mode as
represented in Fig. 4C, is ~hown in Fig. 7 in block diagram
form in which the S82 ~ode is produced having 32 bits of one
data channel divided into four Eets of eight bits
representing four channels of left and right stereo signals,
with a sampling frequency of 22.05XHz over two data words.
Left channel analog ~ignals La, Lb, Lc, and Ld are supplied
respectively to input terminals 21, 22, 23, and 24 and right
channel analog ~ignal~ Ra, Rb, Rc, and Rd, are supplied to
input terminals 25, 26, 27, and 28, respectively. The
analog ~ignals applied to input terminals 21-28 are supplied
to respective A/D convertors 29-36 wherein they are
converted to digital signals based upon a sampling signal
having a frequency of 22.05KHz. In this mode then the
signals La, Lb, Lc, Ld, Ra, Rb, Rc, and Rd are sequentially
provided within a period of 45.4 micro seconds,
corresponding to the reciprocal of the sampling frequency,
to a parallel-to-serial convertor 37, in which they are
converted from the parallel signals to the serial signal
stream which is then made available at output terminal 38,
lZS85~:1
and again which can be signal processed according to any
desired end use.
Fig. 8 is a block diagram of ~n example of an
encoder corresponding to the M82 mode, in which 32 bits of
one data channel are respectively divided into four sets of
eisht bits representing eight channels monaural ~ignals and
having a sampling frequency of 22.05KHz over two words. The
eight channel monaural signals a to h are fed in at input
terminals 41 - 48, respectively, and are supplied to
respective A/D convertors 49-56 wherein they are converted
to digital signals on the basis of a sampling signal having
a frequency of 22.05XHz. Such digital signals will each
have a data length of eight bits, as shown in Fig. 4C, and
accordingly, this encoder produces the "C" mode discussed
hereinabove. The digital ~ignals are then fed to
parallel-to-serial convertor 57 in which they are converted
from the parallel ~ignals to a serial bit ~tream which is
then made available at output terminal 58 as the required
data output ~ignal~ -
Fig. 9 is a combination or a hybrid encoder
capable of producing mode ~D" as discussed above in which a
plurality of different modes, for example, two modes such as
the S84 mode, as shown in Fig. 6, and the M82 mode, as shown
in Fig. 8 hereinabove. Thus, in Fig. 7, ~eft channel analog
signal La is fed in at input terminal 61 and right channel
analog signal ~a is fed in at input terminal 62. These
analog signals are then applied to respective A/D convertors
67 and 6B wherein ~hey are converted to digital ~ignals
based upon a sampling signal having a frequency of 44.lKHz
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and are then fed to parallel-to-serial convertor 73. Analog
signals a to d of respec~ive monaural channels are fed to
input terminals 63-66 and are then applied to corresponding
A/D convertors 69-72, respectively wherein they are
converted to digital signals, all of which have a similar
sampling freguency of 22.05XHz. The output of A/D
convertors 69 - 72 are fed to parallel-to-serial conver~or
73. Accordingly, parallel-to-serial convertor 73 is
~upplied with 6tereo ignals and monaural signals and then
converts the parallel digital signals into ~erial digital
data ~tream and produces at output terminal 74 a mixed
output data sign~l. More ~pecifically, the encoder of Fig.
9 produces one channel of ~tereo signals having a sampling
~reguency of 44.1~Hz and data length of eight bits, and four
channels of ~onaural signals having a sampling frequency of
22.05RHz and also having a data length of eight bits.
Note that one frame is processed at a rate of 22.7
micro-seconds, which is derived as a reciprocal of the
44.lRHz sampling frequency, and result in a transmission
bit rate of approximately 7.4 mega bits per second (MBPS).
This rate corresponds to the general transmission capacity
of a CATV ~ystem.
Upon transmitting, each of the above modes is
selected in advance and its signal is then transmitted. The
receiver at the customer location must employ the
appropriate decoders, and such decoders are represented in
Figs. 10 and 11. In the decoder of Fig. 10, a common
conventional 8-bit digital-to-analog (D/A) convertor is
employed as the convertor, whereas in the embodiment of Fig.
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~ ~J ~ u ~
l;~S8521
11 a conventional 16-bit D/~ convertor is employed.
~herefore, of the four fundamental modes, the decoder shown
in Fig. 10 can be u~ed for the M82 mode, the SB2 mode, and
the S84 modes, while ~he decoder of Fig. 11 is employed for
the S164 mode. As for the ~184 mode, this can be processed
substantially the same as the S82 mode and in which case the
decoder of Fig. 8 is employed.
Referring now specifically to Fig. 10, input
terminal 83 receives a serial da a ~ignal having a data
format according to any of the above-described format modes
produced at the transmitting side, and the ~erial data at
input terminal 81 is fed to a serial-to-parallel (S/P)
con~ertor 82a, which forms a par~ of demodulating circuit
82. Demodulating circuit 82 may be advantageously formed as
a ~ingle integrated circuit. S/P convertor 82A converts the
serial data received at input terminal 81 to parallel
signals based upon a clock siynal produced by a timing
circuit 82b. The ou~put signals thus produced are latched
into a latch circuit 82c on an 8-bit by 8-bit basis, as
determined by a latch signal also produced by timing circuit
82b.
Therefore, latch circuit 82c produces the 8-bit
data of a monaural signal, as might be represented in Fig.
12A, during a period of 45.4 micro-seconds in the M82 mode,
whereas latch circuit 82c would produce each 8-bit data of
left and right channel stereo signals during a period of
45.4 micro ~econds in the S82 mode, as represented in Fig.
12B. Similarly, in the M84 mode, as represented in ~ig.
12C, 8-bits of data of two monaural signals is produce~
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during a period of 22.7 micro-seconds and in the M162 mode,
as represented in Fig. 12D, the lowermost 8-bit data of ~he
16-bit monaural signal is produced during the first half
period of 45.8 micro-seconds, whil~ the upper B-bits of data
is produced in the latter half of the second half of the
45.4 micro-seconds period.
Fig. 12E represents the S84 mode, in which each
8-bits of data of the left and right channel stereo signal
is produced during a period of 22.7 micro-seconds by latch
circuit 8Zc. Fig. 12F represents the S162 mode in which
lower 8-bitc of data ~nd upper 8-bits of data of a left
channel stereo signal are produced during the first half of
the 45.4 micro-~ec~nds period, whereas the lower B-bits of
data and upper 8-bits of data of the right channel ~tereo
~ignal are produced during the latter half of this period.
In the M164 mode, as represented in Fig. lOG, the lower
8-bits of data of the 16 bit monaural ~ignal are produced
during the former half of ~he 22.7 micro-seconds period,
while the upper 8-bits of data thereof is produced during
the latter half of such period.
The selection of any of the above modes is of
col~rse made in advance by a mode selection signal, which can
then be fed to timing circuit 82b, fed in at input terminal
83. The state of such mode selecting signal as required to
set each of the fundamental modes S164, S84, S82, and M82
has a code indicated in Table II as set forth hereinbelow.
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1;~5~521
TABLE II
_,., . .. .__
Mode Ml M0 C2Cl C0
,... _ _ . ..
S1~4 0 0 x ~ x
. ,
S84-~ 0 1 x x
.. - _
S82-1 1 ~ ~ 0 0
-2 1 0 Y 1
. .__ . __ . _ _
M82-1 1 1 0 1
1 1 1 0 0
-B 1 1 1 1 1 1
Table II represents that each of the fund~mental
modes may be specified by two bits (Ml, ~0) and the channel
of each mode ~ay be cpecified by three bits (C2, C1, C0).
Thus, in the decoder of Pig. 10, for example, because the
S84 mode, the S82, and the M82 are able to be processed, the
mode 6election signal corresponding to each of the above
modes, and formed of bit sequences as indicated in Table II,
must be ~upplied at input terminal 83. The various states
in Table II in which the result is irrelevant, that is,
~don't care~ are represented by an x.
In all events, the output ~ignal from a latch
circuit 82c is fed to B-bit D/A convertor 84 wherein the
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l~S85Zl
data are converted from digital parallel signals t3 a single
analog signal fed to a ~elector input of 6witch 85.
Switching circuit 85 is operable to change the input signal
betwen two separate outputs in response to a left/right
switching signal produced by timing circuit 82b, so that the
output signal from D/A convertor 84 is fed to output
terminals 86a and 86b, alternately. Thus, in the case of a
stereo mode signal the left channel signal is delivered to
one of the output terminals, 86a or 86b, and the right
channel ~ignal is delivered to the other output terminal.
Conversely, in the case of the monaural mode, the monaural
signal is delivered to both output terminals 86a and 86b by
a bxidging action of switching circuit 85 (not shown).
The decoder of Fig. 11 is required for the S164
mode and employs two latch circuits 87 and 88, which
correspond to the lower 8-bits and upper 8-bits of the
16-~it ~ignal, respectively, are arranged at the output
stage of latch circuit 82c and a 16-bit D/A convertor 89 is
connected at the outpu~s of la~ch circuits 87 and 88. A
timing circuit 90 is provided that receives inputs from
timing circuit 82b and provides latch ~ignals for latch
circuits 87 and 88 and also provides the left/right
switching 6ignal fed to switching circuit 85. Timing
circuit 90 provides the appropriate control signals based
upon the sampling signals having frequencies of 22.05KHz,
44.1~z, and the left/right switching signal, as applied
thereto from timing circuit 82b. In order to have timing
circuit 82b provide the appropriate timing signals to timing
circuit 90, and because the selected mode is the S164 mode,
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the mode selection sigr.al formed in accordance with the bit
series shown i~ the first row of Table II must be fed into
terminal 83. As in the decoder of Fig. 10, the serial data
is fed in at input ter~inal 81 and input to
serial-to-parallel convertor 82a, in which it is converted
in accordance with a control signal from timing circuit 82b
and then latched into latch circuit 82c. Output of data
from latch B2c is performed in accordance wi~h latching
circuit from timing circuit 82b such that the lower 8-bits
of data of the 16-bit data is latched into latch circuit 87,
while the upper 8-bits of data is latched into latch circuit
88. Accordingly, at the output of latch circuits 87 and 88
are the lower eigh~ bits and the upper eight bits of the
left channel ~tereo signal during the first half of the 22.7
micro-second period and the lower eight bits and the upper
eight bits of the right channel stereo signal during the
second half thereof. This arrangement is represented in
Fig. 12~. The ou~puts of latch circuits 87 and 88 are fed
to D/A convertor 89 wherein they are converted to analog
signals and ~ed as inputs to switching circuit 85.
Switching circuit 85 is changed in position in response to
the left/right switching signal produced by timing circuit
90 and, accordingly, the left channel signal is produced at
either one of output terminals 86a or 86b and the right
channel signal is produced at the other output terminal.
Although in the above-described embodiment of the
present invention four data channels are all divided into a
plurality of data word lengths this need not be the case and
all that is required in ~hat one data channel be divided
12S~S~l
into ~uch data lengths. ~or example, an arbitrary
combination of the various modifications in which only one
data channel is divided could be provided with the remaining
data channels being continuous data instPad of being
divided. Additionally, it should be understood that while
the sampling frequency, data length, and the like are set
forth above relative to the different embodiments these
parameters are merely examples and the present invention is
not limited to these particular values but can be varied as
required.
Referxing back t~en to Figs. 3A and 3B it is noted
that service bit signals SBl to SB255 were added ~o the word
synchronizing signals WSl - WS255, respectively as being
formed of four bits and so one service bit ~ignal is
employed over two words. Eight bits of such service bit
signal can then be used as the above mode selection signal
as might be fed in ~t terminal 83, for example, the most
~ignificant bit (MSB) is as~igned to a parity check
function, the second significant bit l2SB~ i8 assigned as
emergency broadcasting, the third significant bit (3SB) is
assigned to facsimile broadcasting, the fourth significant
bit (4SB) is assigned to communication broadcasting, the
fifth significant bit (5SB) is assigned to stereo broadcast
in which the data length is 16-bits, as shown for example in
Fig. 4A, the sixth significant bit (6SB) is assigned to
~tereo broadcasting, in which the data length is 8-bits, as
represented in Fig. 4B, the seventh significant bit (7SB) is
assigned to monaural broadcasting, in which the data length
is 8-bits, as represented in Fig. 4C, and the least
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lZS8521
significant bit ILSB) is assigned to the transmission of
computer software, such as computer games or the like. In
the use of such service bit signals employing 8-bits as
described hereinabove, when any one bit is a a ~1~ then the
terminal on the receiving side is controlled to carry out
the operation corresponding thereto. The logical state of
this signal may be chosen as required.
Because the frame synchronizing signal and the
word cynchronizing signal can be easily discriminatea one
from another at the receiving side, it is possible to
readily identify 256 addresses for 256 words comprising one
frame, for example, as 6een in Fig. 3A. Thus, on the basis
of the contents of the service bits added to each word
~ynchronizing signal, it is possible to carry out the
various services corresponding thereto, as explained
hereinabove. Nevertheless, when it is required to provide
addresses that exceed 256 in number, some further action
must be taken. Therefore, the 6ervice bit SBf which is
added to the frame synchronizing signal FS is provided ~ith
and desired 4-bit pattern, which can represent, for example,
a start pattern involving the beginning of addre~sing, a
continuous pattern representing the continuity of
addressing, and an end pattern which represents the end of
addressing and so forth. These patterns can then be
followed by the frame synchronizing ~ignal FS of an
~rbitrary number in accordance with the scale of the system.
Accordingly, when the word synchronizing signals are
seguentially counted from the frame synchronizing signals
that are added with the ~ervice bits of the start pattern, a
1258S2~
large number of addresses can be uitable assigned. ~ig. 13
schematically illustrates in block diagram form an
embodiment of a practical circuit to accomplish this.
In Fig. 13, input terminal 100 receives
information having the above-described signal format and
~uch information is fed to a cervice bit latch 102, to a
word synchronization detector 103, to a frame
synchronization detector 104, and to a service bit detector
105 ~or detecting the sexvice bit that is added to the frame
~ynchronizing signal. Word synchronization detector 103
seguentially detects the word synchronizing fiignal arranged
between respec~ive frame synchronizing signals, as seen for
example in Figs. 3A and 3B, and supplies the detected word
synchronizing signal as a clock 6ignal to a counter 106, in
which such clock signals are counted up. The frame
synchronizing detector 104 operates to detect the frame
synchronizing ~ignal added at the beginning of each frame,
as represented in Fig. 3A, and produces an output signal fed
to service detector 105 that operates as its drive signal.
Service bit detector lC5, when receiving the output signal
from frame synchronizing detec~or 104, detects the service
bit added to the frame synchronizing signal and identifies
the particular pattern, that is, the pattern of the start,
continuous, and end patterns, to which such service bit
belongs. In the event the service bit belongs to the start
pattern, service bit detector 105 produces at its output a
reset signal, whereby the cGntentS of counter 106 are
cleared. Thus, in synchronism with the frame synchroni~ing
signal added with the service bits that represents the start
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pattern, counter 106 will ~equentially count up the word
synchronizing signal following the frame synchronizing
signal. If the identified pattern represents the continuous
pattern, then the count operation of counter 106 is
continued and ultimately ended when the frame synchronizing
signal is added with the service bit, which indicates that
the end pattern is detected.
The output of counter 106 is fed to one input of
coincidence circuit 107 and operates as the address data
therefor. ~his input is compared with another address data
signal fed into the other input of coincidence circuit 107
from an addressing circuit 108, in which ~elf-addressing
data, that is, the address number, has been stored in
advance. When the two address data signals fed into
coincidence circuit 107 are in agreement, ~oincidence
circuits 107 produces an output signal fed to service bit
latch 102, which operates as the latching signal. Because
6ervice bit l~ch 102 is con~inuously 6upplied with the
received data at input terminal 130, when the latching -
~ignal from coincidence circuit 107 is received, service bit
latch circuit 102 will latch the service bit added to the
word synchronizing signal at that time as its self-service
~it. The latched service bit is then supplied to a
microcomputer 109, which produces system control signals at
it output terminal 110 in accordance with the contents of
the service bit. As a result, based upon the system control
~ignal, operation of the corresponding apparatus (not shown)
is controlled by the microcomputer 109.
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12S8SZl
As seen rom the ab~ve, because the service bit is
used to control the state of each receiving terminal,
communications, emergency broadcasting, facsimile
transmission or the li~e are possible only to the specified
user and, moreover, in the situation where charges are made
for the various services, such as pay audio, pay channel
television, or pay computer games, the receiver at the
terminal side can be controlled (addressed) to allow only
the appropriate subscribers to enjoy the appropriate
service.
Accordingly, with the present invention because at
least one channel of digital signals among a plurality of
channels is divided into a series of shor~er data lengths
and each divided data length transmitted within a constant
time interval, which interval can be selected, ~he signal
can be transmitted in various modes such as high quality
stereo music, multi-channel stereo music, audio services
such as news, weather forecasts, communications
broadcasting, and the like each requiring segmented multiple
channels. For example, in a cable television transmission
line where the bandwidth of a typical television channel of
6MHz is employed, a 16-bit signal having a sampling
frequency of 44.lKHz will permit a music program of up to
four stereo channels to be transmitted. When one such
standard bandwidth television channel is provided with an
8-bit signal having a sampling frequency of 44.lRHz then up
to eight stereo channels of music can be transmitted
simultaneously. Thus, subscription music service is quite
possible.
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l~S~3SZ~
Furthermore, in making facsLmile transmissions,
and employing the M82 mode, for example, eight channels of
facsimile signals can be transmitted simultaneously though a
single data channel. This permits use of extremely high
speed facsimile receivers and, thus, even greater facsimile
transmissions become possible. When transmitting computer
software and assuming the M82 mode is being employed, for
example, when one bit is assigned to one particular computer
software routine 64 different computer software programs can
be transmitted simultaneously through one data channel.
According to the present invention, because the
~ervice bit added to the frame synchronization ~ignal as a
auxiliary information is detected and the word
~ynchronization ~ignal is sequentially counted thereby to
identify the address state, addressing over a plurality of
frames is possible. This means that when a system has a
very large number of receiver terminals it is possible to
easily control the receiving state at each of these
terminals, because a very large number of addresses are
afforded by spreading the addressing over a plurality of
frames.
Although illustrative embodiments of the present
invention have been described in detail abo~e with reference
to the accompanying drawings, it is understood that the
invention is not limited to those precise embodiments, and
that various changes and modifications can be effected
therein by one skilled in the art without departing from the
scope or spirit of the invention, as defined by the appended
claims.
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