Note: Descriptions are shown in the official language in which they were submitted.
s
1 10.^.8
Selectively accassible memory having an active load.
The inventio~ relates -to a selectively accessible
memory (RA~) having an active load for storing binary
informations and comprising a plurality o* cells organized
in lines and columns, each cell comprising a first and a
5 second transistor of a firs-t type each comprising on the
one hand a first and a second emitter, the ~irst emitters
being connected to each other and the second emit-ters being
each connected to a column selection conductor, and on the
other hand a base connected to the collectors of a third
and a fourth transistor,respectively9 o~ a second typa
opposite to the said first type, and finally a collector
connected to the bases of the third and the fourth -tran-
sistor, respectively, the collector of the third transistor
being connected to the base of the fourth transistor and
conversely and the emitters o~ the third and four-th
transistors being connected to each other and to a line
selection conductor.
Semiconductor memories of the type indicated
are well known -to those skilled in the art bo-th as to their
general organization and as to the operation of each o~ the
elementary cells in which the information is stored in the
form of -two possible conduction states, i.e. one conduction
state in a half-cell (for example first and -third
transistors), this state imposing the blocked state of the
other half~cell associated with it (in this case second and
fourth transistors).
A cell of the type comprising complementary
transistors is described in US-PS No.4,257,059.
I-t is known that, when a half-cell is connected
in the forward direction9 the two complementary transistors
of this half-cell are saturated at the point a-t which the
product of their respective amplifica-tions is equal to 1.
~l2~
PHF.~5-519 2 1~ 2.86
This holds independently of -the value of the current which
flows through it so that even at the low current levels
used for maintaining the informa-tion9 of the order of a few
microamperes, the transistors of the half-ce~ concerned are
still strongly saturated.
The saturation phenomenon involves a disadvantage,
which will be explained in greater detail. In the following
description, for the sake of simplicity and with reference
to common practice, the first and second transistors of the
first conductivity type (multi-emitter transistors) are
chosen to be of the NPN type and the -transi stors of the
second type are PNP transistorsO
Among a column of cells, the selection of a
particular cell, for example with a view to reading, is
considered. This selection has been determined by an
increase of the voltage of the line selec-tion conductor~
which is connec-ted to this particular cell. Insidethis
particular cell, one of the half-cells is in the on-
condition so that the corresponding read/wri-te conductor
or column selec-tion conductor has also its potential in-
creased because the second emitter of its NPN -transistor
(for example the first transistor) gives up -the selection
current at -this read/write cond-uctor. The other cells of
-the same column which are not selected at this instant are
only subjected to the hold current. Some of these other
cells have -their half-cells in -the on~state on the same
side as -the particularly selected cell. The second emitter
of their first NPN transistor, as should be borne in mind,
is connected to the same read/write conductor. From this
it follows that for these other cells of the column each
second emit-ter is polarized in -the reverse or forward
direction a-t a voltage less than a diode direct vol-tage
(Vbe). These transistors operate in the inverse mode,
because the first emitter brings -them into saturation and
hence opens their base/collector junction. This resul-ts in
an undesired inverse current, which flows in these emitters,
which act as collectors.
3~
PH~.S5-519 3 10 2.8~)
In addition to -the fact that the said inverse
current can increase for a single cell to a substantial
fraction of the value of the hold current, which involves
the risk of seriously disturbing the operation of this cell,
this current is also cumulated along a read/write conductor
and can thus be multiplied by a number which can reach the
number of cells (minus one) contained in a column. In the
case of memories of high capacity, the overall leakage
current in a column can thus become a non-negligible
10 fraction of the selection current itself, thus causing
considerable disorders especially a-t the level of -the
peripheral read/write circuits.
Moreover, the value of th~ said inverse current
depends upon the value of the inverse amplification of the
15 NPN transistors, which inverse amplification can be
mastered only with difficulty in practice and can fluctuate
from one production series to another.
The invention has ~or its object to mee-t to a
great extent the difficulties mentioned above.
A selectively accessible memory according to the
invention is characterized in that, in order to reduce the
inverse current of the non-selected cells, an additional
diode is conriected parallel to -the emitter/base junc-tion of
each of the third and fourth transistors of each cell and
25 in the same direction as the said emitter/base junction.
The cell modification according to the invention
as defined above is not only compatible with the improvement
known per se ~rom British Patent GB 1,L~05,285 in the fairly
different context of the cells having a resistive load,
30 but it also permits of obtaining wi-th this improvement
a cumulation of effects on the inverse current. The said
improvement consists, as should be borne in mind3 in that
the first and second transistors of each cell are provided
with a third emitter shortcircuited with the base of the
35 corresponding transistor. This does not reduce -the
overall value of the inverse current in the half-cell
concerned, but a substantial part of the latter is generated
~L2~i9~35
PHF.85-519 ~ 10.2.86
from the base current of the corresponding transistor
reducing accordingly the undesired curr0nt in the column
conductor.
According to a modifica-tion, the said diode is
constituted by the collector/base junction of a shunt
transistor of the first type, whose emitter and base are
shortcircuited with each o-ther and are connected to the
said line selection conductor.
According to an embodiment of this modification,
each of the first and second multi-emitter transistors of
each cell is a vertical transistor, whose collector is
constituted by a buried layer and whose base is constituted
by a first surface adjacent region in which the said
emitters are provided, each of the third and fourth
transistors of each cell is a lateral transistor, whose
collector is constituted by the said first surface adjacen-t
region and whose emitter is constituted by a second
surface adjacent region separated from the first surface
adjacent region by a first narrow surface adjacent portion
which prolongs locally by the surface the buried layer and
constitutes the base of the lateral transistor, and the
shunt transistor is a second vertical transistor, whose
emitter region is provided in the second surface adjacent
region~ which constitutes its base and whose collector
is constituted by the said b-uried layer This embodiment
permits of using the invention without enlarging the
dimensions of the cells.
The emitter region of the second vertical
transistor can be disposed at least in part un~er -the
selection conductor, which thus ensures the shortcircuit
between its emitter and its base.
The invention will be more clearly understood
when reading the following description given by way of
non-limitative example in connection with -the drawings,
in which:
- Fig. 1 shows a scheme of the organization of the
cells inside a memory according to the prior art,
~2~3t~31Si
PH~.~5-519 5 10 2~86
- Fig. 2 shows an electric circuit diagram of a cell
according to the invention, and
- Fig 3 shows a diagram of the latter incorporating
the said known improvement,
- Figures 4 and 5 show two variations of the elec-tric
circuit diagram of the invention, Fig. 7 incorporating the
said known improvement,
- Figures 6 and 7 show in plan view and in vertical
sectional view AA, respectively, an embodiment of the
circuit diagram of Figures 4 and 5.
Fig 1 shows a diagram of a part of a semi-
conductor memory according to the prior art. The rectangles
la,lb,lc... each represent one of the cells of a column,
while the rectangles 2a,2b and 2c .. represent the cells
lS of the following column. The cells of a line, 1a~2a~
are connected in parallel between a line selection conductor
1Oa and a hold current source 20a. Likewise, the cells
lb,2b,... o~ the following line are connected between a line
selection conductor 1Ob and a hold current source 20b.
The same holds for the following ~ines of cells, such as
1c,2c..., the line selection conduc-tors, such as 10c,
and the hold current sources, such as 20c.
With regard to the cell 1a, the eleme~ts
constituting a cell are shown9 i.e~ a first $ransistor Tla
of the NPN type having two emi-tters, the first of these
two emitters designated as "hold emitter" being connected
to the hold curren-t source 20a The base and the collector
of the transistor T1a are connected to the collector and
the base, respectively, of -the transistor T3a of the PNP
type in order to form a half-cell. The emitter of the
transistor T3a is connected to the line selec-tion conductor
1Oa. The second emitter designated as "selection emitter"
of the transistor T1a is connected to a read/write
conductor 15 for reading or writing the memory. The assembly
formed from the transistors T1a and T3 constitutes a first
half-cell9 while a transistor T2a of the NPN -type having
two emitters is associated with a transistor T4a of the
~2~ L35i
PHF.S5-51~ 6 10.2.~6
PNP type in order to form a second half-cell identical to
the first half-cell. These two half-cells are thus connected
in parallel between the line selection conductor 1Oa and
the hold current source 20a. The first and second half~cells
are connected to each other in known manner by cross-
coupling, the base and the collector of the transistor T1a
being connected to the collector and to the base,
respectively, of the transistor T2a. The hold emitter of the
transistor T2a is connected to the hold current source 20a,
10 while the selection emitter of the same transistor is
connected to another read/write conductor 16 for reading
or wri-ting an information state, which is inverse to that
of the conductor 15.
The other cells of the memory are constituted by
15 similar elements. Inside the cells lb and 1c, only the NPN
mul-ti-emitter transistors T1b9T1C and T2b,T2c are shown~
whose operation is similar to that of the transistors T1a
and T2a, respectively.
The conductors 15 and 16 of -the first column have
20 connected to them the read/write transistors T151 and T161,
respectively, associated with this column. Likewise, for
the following columns, such as represented by the cells
2a,2b,2c..., other read/write transistors are connected
to the column conductors, which transistors are represented
25 by T152 and T162 in the Figure, In -the assembly of the
transistors T151,T152. .., the bases are connected to each
other and this also holds for -the collectors. A similar
arrangement is utilized with regard to the assembly of the
transiStors T161'T162
By means of the numerical values indicated in a
practical embodiment, -the difficulty arising with the use
of such a memory according to the prior art will now be
precisely defined, which difficulty will be met in
accordance with -the invention.
It is assumed that the line 1Oa is selec-ted and
that at-tempts are made to read the column 1a,lb,1c by means
of the conductors 15 and 16. Le-t it further be assumed that
~2~ 3~i
Pl1~.~5-519 7 10.2 86
at this instant, all the hal~-cells are in the on-state
on the lefthand side of the Elgure, that is to say that
1a,T3a,T1b,T1C are conducting (the base
of T1a,T1b... is at the high level H and that of T1b,T2b...
is at the low level L).According to common practice in ECL
technology7 the high level H is at -1.6 V and the low level
L is at -2.4 V.
The hold currents per half-cell have been chosen
to be about 25/u~, while the reading current is ensured
lO to be of -the order of 1000/uA. The selection conductors
10b, 10c of the non-selected lines are brought to -2.6V,
while the selected conduc-tor 1Oa is brought to a potential
of -1.6 V. The column conduc~or 15 is a-t -204 V, i.e. 0.8V
lower than ~I, this voltage drop essentially being repre-
15 sented by the Vbe of the transistor Tla, whose emitter feedscurrent to the column conductor 150 The reading level 2+
is present at the base of the transistor T15~.
The voltage of the line selection conductors 1Ob
and IOc of -2.6 V is returned with a slight vol-tage drop
20 to the base of the transistor T1b and to that of the
transistor T1C because hypothetically -these transistors
are in an on-state by their hold emitters. Since the
transistors T1b and T1C are otherwise in a saturated state
produced by the hold current given up by their hold emitters,
25 their base/collector junctions are polarized in the proximity
of the forward direction o~ these junctions.
The unfavourable condi-tions are -then combined in
order that the transistors Tlb and T1C opera-te in the
inverse mode, i.e. this time unsaturated~ at the level
30 of their selection emitters E2, that is to say -that the
func-tions of the selection emitters E2 and of the
collectors are inverted wi-th respect to their usual
polarization.
It can be ascertained that in practice an undesired
35 "inverse" current effcctively enters into the selection
emitter E2 of each of the transistors T1b and T1C, the value
of this current being of the order of several microamperes
L3S
PHF.$5-5-l9 8 10 2.86
- per emitter. Besides the fact that at -the level of a cell
this current is not negligible with respec-t to the hold
current and can adversely affec-t the operation of the
associated PNP transistors due to the fact that the latter
should operate at a current considerably smaller than
expected, the inverse currents of the cells 1b,1c etc.
of the same column are added at a column conductor, such as
theconductor 15. In the case of memories of high capacity
having, for example, 64 cells per column, the sum of the
l0 inverse current can become a non-negligible fraction of the
selection current itself, thus involving serious distur-
bances of the operation of the read/write circuits of a
column.
Fig. 2 shows a particular cell denoted by 1b and
15 not differing from the cell lb of Fig.1 modified in
accordance with the invention, the corresponding elements
of -the prior art arrangement being otherwise provided with
the same reference numerals. According to the invention,
a diode (D1,D2) is connected in parallel in each of the
20 emitter-base paths of the transistors T3b and T4b,
respectively, and in the same direction. In other words:
for transistors T3b and T4b of the PNP type the diodes D1
and D2 are connected in forward direction between the line
selection conductor 1Ob and the bases of the said
transistors.
It could be supposed a priori that -this adjunction
would be penalizing due to the fact tha-t these diodes D1
and D2 9 because -they derive current that has to flow through
the transistor, have the effec-t that the amplification
decreases, the associated assembly of diode and transistor
having in fact an amplification which is substantially
lower than the transistor alone and is the lower as the
diodes derive more current.
< The invention is first based on the fact that,
whilst the product of the amplifications of the two -tran-
sistors rernains sufficiently higher than 1, it is possible
of maintaining the stability of the cell.
PHE.S5-519 9 10.2.86
The second important point is that the Applicant
has found that the parameter directly de-termining the value
of the reverse current is not a current parameter, as in
the case of the prior art, but a voltage parameter. The value
of the collector/base voltage Vbc of the transistor T1b or
T2b, dependent upon the condition of -the cell, is concerned
and the variation of the reverse current is very quick
(division by two for a reduction of the voltage Vbc of 18 mV).
The third important point is that the fact is
10 utilized tha-t, if, for example, the transistor T1b is
traversed bythe said reverse current, the other transistor
T3b of the same half-cell is in the saturated state. In this
case, the diode D1 produces a derivation of the emitter
current I from the transistor T3b and the emitter/base
5 voltage Vbe decreases (by 18 mV for a division by two of
the current Ic).
The emitter/collector voltage Vce, which is already
low (of the order of 50 mV~, also decreases, but by an
amount smaller than the decrease o~ the Vb of T3b because
20 the saturated state of the -transistor T3b is only slightly
modified. The voltage of the collector of the transistor
T~b being smaller than that of its base ~the base/collector
junction is almost opened), the collector/base voltage Vbc
of the transistor T1b decreases, which leads to a decrease
25 of the leakage current.
A diode D1 is taken by way of example, which
derives 60 % of the emit-ter current from the transistor T3b,
i.e. a division of the current I by 2.5, the base voltage
e
of T2b increases by 25 mV, like that of the collector of T1b,
30 and the voltage of the collector of T2b increases only by
10 mV, like that of the base of T1b. Roughly, the voltage
Vcb of the transistors T1b decreases by 25 - 10 = 15 mV.
This leads to a reduction of the leakage current in a
ratio approximately equal to 1.79~
According to Fig. 3, the -transistors T1~ and T2b
are each provided with a third emi-tter E3 and E~3,
respectively, shortcircuited with the base, as is shown
~2~ S
PH~.S5-5l~ 10 10.2.86
per se from British Patent GB 1,405,2~5 men-tioned aboveO
In a remarlcable manner, a cumulation is obtained of the
results provided by the diodes D1 and D2 on the one hand
and by the emitters E3 and E~3 on the other hand. In fact,
as has been stated above, the collector/base voltage Vbc of
the transistors T1b and T2b is determinative of the value
of the leakage current. The supplementary emitter E3
supplies, if the lef-t-hand half-cell is saturated7 a part
of the leakage current, for example 50 /~ thereof, if the
10 emitters E2 and E3 have thesame surface area, the overall
value of the leakage current remaining the same as in the
case of Fig.2. In the above example, the leakage current
in the column conductor 15 is further divided by two with
respect to the case shown in Fig.2.
According to Figures 4 and 5, in which the same
elemen-ts are provided with the same reference symbols as
in Figures 2 and 3, the diodes D1 and D2 are constituted
by the collector/base junction of the transis-tors T5b ancl
T6b, respectively, of the type opposite to that of the
20 transistors T3b and Tllb. T~e emitter and the base o~ the
transistors T5b and T6b are shortcircuited and connected
to the line selection conductor 10. The collector of the
transistors T5b and T6b is connected to the base o~ the
transis-tors T3b and Tl~b, respectively. In the case in which
25 the transistors T3b and T4b are of the PNP type, the
desaturation is facilitated to a great extent by the
presence of the collector/base junction of the transistors
T5b and T6b, which is intrinsically quicker.
According to Figures 6 and 7, each half-cell is
30 realized at a surface of a substrate 50 in an insulating
island 51 and 52, respectively, limited by an insulating
layer 33 consisting, for example, of SiO2o The island 51
comprises, for example, in the case of a substrate of the
~-type, a highly N -doped contact layer forming the bottom
35 of the island 51 on which is disposed a semi-conducting
buried layer 34 which is N-doped and forms the collector
of the transistor T1b. At the surface are provided:
L3~
PH~.85-519 11 10.2.86
a first surface adjacent region 36 of the p type consti-
tuting the base of the transistor T1b comprising emit-ter
regions E1, E2 and, as the case may be, E3 of the n~-type;
a second surface adjacent region 35 which is also of the
p -type and is separated from the first region by a first
surface adJacent narrow portion 31 prolonging locally at
the surface the buried collector layer 34.
In other words: the transistors T1b and T2b
(E1,E2,E3,36,34) are vertical and the transistors T3b and
b (35,31,36) are lateral.
Fig. 6 shows more particularly how the
metallizations are disposed.
It should be noted that the drawing of Figures 6
and 7 are only diagrammatic and that for the sake of clarity
15 the proportions are arbitrarily not taken into account.
In these Figures, certain insulating surface layers are not
shown, For -the sake of simplicity, the metal strips serving
as contacts on the various regions of the semiconductor
body are shown -to be narrower than the corresponding regions,
20 whereas in practice they are realized to be wider than the
contact windows and partly bear on an insulating layer.
Consequently, with reference to Fig. 6 9 it should
be noted that the buried layers 30 and 4O, which ex-tend
beneath the islands 51 and 52, respectively, are prolonged
25 under collector contac-t points C and C'. The deep oxide 33
has a pattern such that a considerable part of the buried
layer subsists in the zones in which both islands are
simultaneously formed7 especially in the said collec-tor
contact zones C and C'.
The emitter E1 is made in two parts. A hold current
source conduc-tor 11 interconnects -these parts of emitters
E1 and E'1 of the cells of the same line and is insulated
from the base region 36 be-tween these two parts by an
insulating layer of, for example, oxide. This measure is
35 known from French Paten-t No.2,4137782 in the name of the
Applicant.
The other line interconnection 10 is obtained by
a line selection conductor connecting electr~cal1y the
PHE.~5-5l9 12 10.2.~6
emitter regions 35 and 45 of the cells of the same
line.
The column connections are obtained by the column
selection metallizations 25 and 26, which interconnect the
emitters E2 of the same column for the metallization 25
and the emitters E'~ of the same column for the
metallization 26.
The internal electrical connections of the cell
are obtained by metallizations 130 and 140. The metalli-
zation 130 connects the base 36 of the transistor T1b to
-the collector C' of the transistor T2b and the metallization
140 connects the base 4~6 of the transistor T2b to the
collector C of the transis-tor Tlb.
The emitters E3 and El3 that may be present are
l5 disposed beneath regions 133 and 143 of the metalliza-tions
130 and 140, which short circuit them with the base 36
and 46, respectively, of the transistors T1b and T2b.
The emitter regions E3 and E~3 are generally narrower than
the regions 133 and 143, which project on either side at
20 131 and 132 and 141 and 142, respectively.
Consequen-tly, the operation of -the transistors
T1b and T2b is not disturbed with regard to their emitters
E1 and E2 by their base resistance pinched by the
supplementary emitter E3.
5b and T6b are vertical
transistors, whose emitter is constituted by a region of
the n~ type 135 and 145, respectively, whose base is con-
stituted by the regions 35 and 45, respec-tively, that is to
say the emi-tter ofthe -transistors T3b and T4b, and whose
collector is constituted by the afore-men-tioned regions 3L~
and 30. The regions 135 and 145 are situated at least in
part beneath the metallization 10, which realizes the
emitter-base shortcircuit of the transis-tors T5b and T6b.
Preferably, the regions 135 and 145 are situated completely
beneath the metallization 10 under the same conditions as
the emitter regions E3 and E~3. They occupy a frac-tion of
the surface of -the regions 35 and 45 and their doping may
PHF. ~5-519 13
advantageously be the same as that of the emitter regions E
to E3.
The method of realizing a semiconductor memory
integrating a plurality of cells as described in Figures 6
and 7 does not involve particular difficulties and utilizes
the known techniques used in the manufacture of integrated
circuits with lateral insulation by deep oxide, especially
ECL circuits. For example, reference may be made to the
information given in the French Patent Application No.
2,413,782, mentioned above, as the general manufacturing
techniques.
When a self-alignment method should be used and
especially the contact windows of the emitters at the same
time serve for the ion implantation of these emitters, it has
to be ensured that for forming emitters or supplementary
regions a window having the width of the base contact is
provided, then -the latter is reduced by a mask of
photosensitive lacquer to the dimensions desired for the
emitter or the supplementary regions and subsequently its
implantation is effected. When the lacquer mask is withdrawn,
a base contact window is obtained which includes the emitter
or the supplementary region. When a conductor is used which
projects on all sides at the periphery of the contact
windows, it is ensured that the shortcircuit aimed at between
the base and the supplementary emitter is obtained.
