Note: Descriptions are shown in the official language in which they were submitted.
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1 MAXIMAL LENGTH IMMEDIATES WITH FIXED SIGN POSITION
~3Backqround and Summary o~ the Invention
4The present lnvantion rel~te3 to th~ 6tructure of
lnstructions within an instruction sat of a computer.
6 Some computer instructions contain immediates. What is
7 meant by an "immediate" i~ data embedded in ~n instruction
8 itself. This data may be used as an operand in an arithmetic
9 operation or as a displacement or of~set value for calculating
addresses. Immediates are stored in i~mediate ~iald~ which are
11 with1n instruction~. A sign bit within an immediate field is
12 usually the most significant ~l~ft~ost) bit o~ th2 l~mediate
13 ~ield. A computer instruction s~t may havs immediata ~ield~ o~
14 di~erent lenqths ~or dlf~erent lnstructions wi~hin the
instruction set. As a result of the above, the ~ign bit ~or
16 1mmediate ~ield~ ~ay vary in location from instruction to
17 instructlon. This can unduly lncr~ase the complexity of the
18 instruction decoding proc~ss and can bQ especially burdensome if
19 the sign bit contains informat~on to control operations or
subop~rations specified by the instruction.
21 When instructlons them~elves are of variable length,
22 extensive decoding ls already required to select eac~ field of an
23 instruction. Complexity required to extract and decode a sign
24 bit may b~ negligibl~ in relation to the decod$ng overhead
required for each instruction. Howsver, instruc~lon ~etching and
26 decodlng overhead r-quirad often makes variable length
28 in~Sructions unaeer~ctive.
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1 ¦ When lnstructions are o~ ~lxed length, various ~eans to
2 ¦ select a ~ign bit may be employed. For instance, ~ultlplexors
3 ¦ may be used to selQct a slgn bit. However, the US8 0~ a
4 ¦ multlplexor requires additional hardware and may add additional
5 ¦ dalay to a critical timing path.
6 Alternatively, signed immediates may not be permitted to
7 vary in length and must occupy the same bit pos~ tions in all
8 instructions in which they occur. Then the customary leftmost
9 position of a sign-bit within an immediate field would place the
sign bit in the same position for each instruction. This,
11 however, may unduly restrict the number of immediate values that
12 may be represented.
13 In accordance with the pre~erred embodiment o~ the present
14 invention, in an instruction set immediate ~ields are allowed to
vary in length ~rom instruction to instruction. In particular,
16 an i~m~diate ~leld is allowed to ~ill up all unused blts in a
17 fixed-length instruction. Howaver, a ~ign bit within each
18 immediate field is placed in a fixed position within the
lg instruction. For example, the sign bit may be right jUstified,
that is the sign bit is put in the least signi~laant (rightmost)
21 bit position o~ an immediate field r~ghtmost bit in the wheru the
22 immediate ~leld is in a fixed location for every instruction in
23 tha ~nstruction set which has A s1gned immediate value. This
24 allow~ time-critical suboperation~ to proceed without waiting for
the value o~ the ~ign bit to be located. At execu ion time, an
26 i~mediate valus may be reassembled with the ign bit ~n the
27 le tmost posltlon by appropriate computer hardware and/or
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software. For instance, the placement of the sign bit can
be moved by merely rearranging the order o~ wires carrying
data. The immediate value may then be sign extended to any
desired number of bits.
Furthermore, in accordance with the present invention in
an instruction an immediate value may be placed in
non-contiguous variable portions of an instruction. This
is done in order to allow a fixed~length instruction to use
a maximal number of bit positions within the instruction to
represent immediate values without writing over fixed bit
positions in other fixed fields.
Other aspects of the invention are as follows:
A computer instruction set comprising:
a first instruction containing a first immediate value
within a first immediate field, the first immediate field
having a first bit position reserved for a sign bit; and,
a second instruction having a second immediate value at
least partially within a second immediate field, the second
immediate field having a second bit position reserved for a
sign bit, wherein the first instruction and the second
instruction have the same number of bits, wherein the first
immediate field and the second immediate field have a
different number of bits, and wherein the first bit
position is in the same location within the f irst
instruction as the second bit position is within the second
instruction.
A method for minimizing the time it takes to decode an
instruction within an instruction set of a computer, the
method comprising the steps of:
reserving a location for a sign bit in every instruction
within the instruction set which contains a signed
immediate value, wherein, for every instruction within the
instruction set which contains a signed immediate value,
the location reserved for the sign bit is in the same bit
position relative to the sign bit location in every other
instruction within the instruction set which contains a
signed immediate value.
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A computing device comprising:
storage means for storing instructions; executing means
for executing instructions, wherein the
executing means executes instructions containing signed
immediate values, and wherein a first slgn bit within a
first instruction containing a signed immediate value is in
a same bit position relative to sign bits within every
other instruction containing a signed il~mediate value; and,
transferring means for transferring :instructions from
the storage means to the executing means.
Brief Descriptions of the Drawings
Figures 1-7 show, for an instruction set, instruction
formats with embedded signed immediate fields in accordance
with the preferred embodiment of the present invention.
Figure 8 is a partial block diagram of a computer which
executes the instruction set shown in Figures 1-7 in
accordance with the preferred embodiment of the present
invention.
Description of the Preferred Embodiment
Figures 1-7 show seven fixed length instructions within
an instruction set. Instructions 10, 20, 30, 40, 50, 60,
and 70 within Figures 1-7 may instruct a computer to, for
instance, load data from a memory location, store data in a
memory location, branch conditionally or unconditionally to
a new section of code, place a long immediate value in a
register or perform an arithmetic compl~tation~ In each of
instructions 10, 20, 30, 40, 50, 60, and 70 fixed fields
may contain values which function as, for instance,
operation codes, reqister addresses, immediate.
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1 ¦ valu~8, ~uboperakion codes, condition 6peoifiers and statuQ
2 ¦ ~ields.
3 ¦ Flgur~ 1 shows instructlon 10 ~avlng 8iX ~ixed positlon
4 ¦ fi~lds 11, 12, 13, 14, 15, and 16. Instruction 10 ha3 no
lmmediats field.
6 Figure 2 shows instruction 20 having f ive ~ixed positlon
7 fields 21, 22, 23, 24 and 25. Instruction 20 al80 contains a
8 maxlmal length immediate value contained in an immedi~te ~ield 27
9 and a sign-bit field 28. Slgn bit field 28 i5 right justified
with respect to immediate fie~d 27.
11 Flgure 3 shows instruction 30 having five fixed position
12 ~ields 31, 32, 33, 34 and 35. Instructlon 30 al80 contains a
13 ~aximal length immediate value contained in an i~mediat~ ~ield 37
14 and a sign-bit field 38. Slgn bit fleld 38 is r:Lght ~ustified
with resp~ct to i~mQdiate field 37. Fixed posit:Lon ~iQld 35 is
16 shorter than fi.xed position ~ield 25 in instructlon 20.
17 Immediate ~ield 37 has expanded to ut~lize the additional room in
18 instruction 30.
19 Figure 4 shows instruction 40 having three fixed pssition
fi~lds 41, 42, and 43. Instruction 40 ~l~o contains a Maximal
21 length immediate value contained in an immediate field 47 and a
22 sign-bit ~iQld ~8. Sign-bit ~ield 48 is right ~ustigted with
23 respect to immediate ~ie}d 47. Instruction ~0 has no fixed
24 position fields corresponding to fields 34 and 35 of instruction
~5 30. Immediate ~ie}d 47 has expanded to utilize the additional
26 room ~n instruction 40, caused by the reduced nu~bsr of ields.
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1 ¦ FigurQ 5 ~how~ in8tru~tlon 50 havin~ three ~ixed poslt~on
2 ~ ld3 51, 52, 55. Inst~uction 50 also contain~ a ~aximal length
3 ¦ l~medi~t~ v~lue contain~d ln ~n i~edlate ~ield 57, an ~m~ediate
4 ¦ field 59 and a sign-bit fleld 58. Sign bit field 58 is rlght
5 ¦ ~ustified with respect to im~ediate f:Leld 57. For maximal
6 ¦ utlllzatlon of available ~pace within instruction 50, the maximal
7 ¦ length immediate value is contained iII immediate fiald 57, in
B¦ sign blt field 58 and in immediate fie~ld 59 even though immediate
9¦ ~ield 57 and immediate field 59 are noncontiguous. .
Pigur~ 6 shows in~truction 60 having four fixed position
11 fields 61, 62, 65, and 66. Instruction 60 al~o contains a
12 maximal length immediate value contained in an immediate field
13 67, an i~mediate ~ield 69 and a ~ign-bit ~iald 68. Sign bit
14 ~ield 68 i5 separated ~rom immediate field ~7 hy ~ixad position
~ield 66. For maximum utllizatlon of available space wlthin
16 instruction 60, the maximal length immediata value i8 contained
17 in immediate fi~ld 67, ln 8ign blt ~ield 68 and in i~ediate
18 field 69 even though immediats field 67, sign bit field 68 and
19 immediate field 69 arQ noncontiguous with respect to each other.
Figure 7 shows instruation 70 having two fixed position
21 fields 71 and 72. Instruction 70 also contains a maximal length
22 immediate value contained in an immediate ~ield 77 and a sign-bit
~3 Pleld 78. Sign-bit ~ield 78 i8 right justi~ied with respect to
24 i~ediate ~ield 77. Instructlon 70 ha~ no Pixed position ~ields
corresponding to field 43 o~ instruction 40. Immed~at~ field 77
26 has expanded to utilize the additional room in ins~ruction 70,
27 caused by the reduced number of fields.
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1 ¦ In~tructions 20, 30, 40, 50 60 and 70 ~hown ln Flgures 2-7
2 ¦ ,tll have the sam~ number o~ bits. ~aximal length im~dlat~
3¦ values contaln~d ln instxuctions 20, 30, 40~ 50, 60 and 70 have a
4 varying bit length, depending upon the nu~ber and length of fixed
position fi~lds within each instruction. All available bit
6 locations, not utillzed ~y ~ixed location ~ields may be utilized
7 to contain maximal length immedlate values.
8 In Figure 8, a computer is shown to contain an instruction
9 and data memory 80, an instruction unit 81, an execution unit 82
and a register file 83. Typically, when executin~ an
11 instruction, instruction unit 81 calculates an address o~ a next
12 instruction to b~ executed. Thls addrQss i~ ~ent via a memory
13 addres~ bu~ 85 to instruction and data ~emory 80. U~ing the
14 rec~ived addres6, memory 80 locatQs th~ nsxt instruction and
sends the next instruct~on to instruction unit 81, execut~on unit
16 82 and register fila 83 via an instruction bus 84.
17 I~ the instructlon requires no additional data, or 1~- all
18 data 1s contained withln an immediate field, or within a
19 plurality o~ immediate fields, execution ~tnit 82 executes the
instruction.
21 If the instruction requires additional data not within an
22 i~mediate field, either memory 80 or reglst~r ~ile 83 must be
23 acce~sed to obtain the data. I~ the data i~ located in memory
24 80, instruction unit 81 or execution unit 82 generates an address
in memory 80 whera the additional dat~ may be ~ound. The address
26 is sent to memory 80 via m~mory addres~ bus 85. Using the
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1 recaived address, memory 80 locates the data and ~ends the data
~ to execution unit 82 via operand bus 87.
3 I~ t~a data i~ located in regi~ter file 83, an addre6~ in
4 register ~ile 83 where the additional data may be found i6
usually embadd~d in an ins~ruction on instruction bus a4. The
6 address i~ s~nt to register file 83 vi.a register addre ~ bus 86.
7 Using the received address, register file 83 locates the data and
8 sends the data to execution unit 82 via operand bus 87. As the
9 addressable data stored in register ~il8 ~3 i8 t~pically ~any
magnitudes less than the addressable data stored in memory 80,
11 retrieval o~ data from register ~ile 83 is much fastar than
12 retrieval o~ data from memory 80. Furthermore, when no data
13 needs to be retri~ved, but all iB rasident within the lnstruction
14 itsel~, executlon time o~ the instruction i~ minimized.
Therefore lt is advantageous to provide ~or ~axlmal length
16 immediate valucs.
17 Even in case~ where retrieval o~ data ~rom register ~ile 83
18 takes no more time than extracting an immediate ~alue e~bedded in
19 the instruction itsel~, it i8 still advantageous to provid~ for
maximal length immediate values since this minimizes the usage of
21 the storage in register file 83, which is usually a scarca
22 resource. ~he opt~mization o~ the regi~ter usage in register
23 file 83 need not then include allocatlon for constant values,
24 which may ba contained in maximal length i~mediate values
25 ~ bodded ln e ln-t~uotlon lt-el~.
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