Note: Descriptions are shown in the official language in which they were submitted.
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Field of the Invention
The invention relates to generating timing signals.
Background of the Invention
Stable clocks such as crystal oscillators have been
used to generate a sequence of timing signals of variable
signal-to-signal interval by programming digital counters to
~rigger the timing signals at predetermined counts of the
clock. Although tapped delay lines having resolution (e.g., 1
nanosecond~ higher than that ~e.g., 16 ns) of the clock have
been used to additionally delay signals relative to the start of
the sequence, timing signal interval resplution has in such
systems been limited by the clock resolution, with the timing
signal period equal to the crystal oscillator period or an
integer multiple thereof.
In St. Clair U.S. Patent No. 4,231,1Q4, desired period
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values that were not even multiples of the crystal period were
obtained by dividing the desired period into a number of crystal
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periods plus a remainder and a residue~v~lu~, which was added by
:a-delay line. The remainder was simply the remainder of
dividing the desired period by the crystal period (e.g., 2 ns
remainder for dividing a 50 ns desired period by a 16 ns clock
period). The residue values accounted for the fact that
subsequent output pulses were not beginning at a clock signal.
(E.g., if the first 50 ns period output appears 2 ns after a
clock signal, the next output will have this 2 ns residue in
addition to the 2 ns remainder, and will appear 4 ns after a
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clock signal, ;n order to be 50 ns after the preceding output.)
A plurality of timing edge generators, emp:Loying further delay
lines, were driven by thesP desirecl period output pulses plus
delayed clock signals, obtained by passing clock signals through
a delay line delayed by the residue value. The circuitry
employing the timing edge generators thus had both the crystal
clock signals and asychronous delayed clock signals distributed
through it.
In some other timing signal generators, desired periods
that are other than integer multiples of a crystal oscillator
period are provided by splitting the clock signals into plural
phases, and proqrammably selecting signals from a particular
phase to trigger an output (e.g., a 4 ns clock split into four
phases to obtain 1 ns resolution).
'r 15 Summary of the Invention
It has been discovered that, by distributing crystal
clock signals directly to local timing edge generators and
selecting a desired clock signal and ad~gng the residue and
remainder delay Ito come up with pulses having periods other
~ than integer multiples of the clock period~ in the edge
generators near the final pulse used for edge g~neration/ using
local programmable counting and delay means, important
advantages would be obtained. Specifically, the timing system
would be synchronous (promoting simplicity of manufacture and
reliable operation); transmission line inaccuracies would not
contribute to timing inaccuracies; there would be reduced
crosstalk (owing to the need to distribute only one crystal
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phase), and there would be a small number of gates (whieh tend to
distort signals) between the clock signal and the final timlng
signal, yielding improved accuracy.
According to a broad aspect of the invention there is
provided a system for providing a plurality of synchronous timing
signals having period values that are not even multiples o~ a
clock period comprising
a clock for generating clock slgnals separated in time by a
clock period, and
a plurality of local edge generators receiviny said clock
signals, each said local edge generator including
local programmable coun~ing means to provide local outputs
upon receiving predetermined clock signals,
means ~or generating a deskew value, and
local programmable delay means connected to receive said
local outputs for providing a timlng signal after a delay interval
following each said local output, said local programmable delay
means having a resolution,
said local programmable delay means including a deskew
circuit for receiving said deskew value, said deskew circuit
providing a delay control signal to said local programmable delay
means so that said timing signal is synchronous with timing
signals of other local edge generators,
the resolution of said local programmable delay means being
greater than that of said clock.
In preferred embodimen~s the local programmable counting
means includes l~ local counter and a coincidence detector that
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receives the output of the local counter plus the output of a
first random access memory (RAM) including the most significant
bi~s of the desired period value (i.e., the integer number of
clock periods in a desired period); a local end-of-count (LEOC)
output is provided at a predetermined count to a flip flop that ls
triggered upon the next clock signal in order to select a desired
clock signal, and that output is provided to khe local
programmable delay means that adds the residue and remainder
values; the programmable delay means
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includes a delay line that is controlled with a residue and
remainder value provided from an adder that obtains the
remainder value (also referred to as the least significant bits)
from a second RAM and adds to it the residue of the prior output,
both RAM5 being addressed by the same address bus; there is a
master counter that counts clock signals and provides master
end-of-count (MEOC) pulses to reset the local counters; there
also are master R~ls that include the most significant bits
and remainder values for the desired period and adders that
are used to calculate the residue value and distribute it to the
local edge generators; and the local edge generators include
adders which are used to add deskew values (used to account for
differences in transmission paths to and through various edge
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generators) to the residue and remainder values, the summation
being used to provide the delay period in the programmable delay
line. A preferred application of the invention is automatic
circuit testing equipment in which test patterns are provided to
a large number of input nodes of a circuit under test at high
speed.
Other advantages a~d features of the invention will be
apparent from the following description of a preferred
embodiment thereof.
Description of the Preferred ~mbodiment
The preferred embodiment wil-l now be described.
Drawings
Fig. l is block diagram of a period oscillator circuit
used to provide master end-of-count pulses and residue values to
,15 a plurality of local edge generators.
Fig. 2 is a block diagram of a local edge generator
_ using clock sisnals and the master end-of-count pulses and
residue values of the Fig. l circuit to"~enerate a timing edge
pulse.
20 Structure '~
Referring to the figures, in Fig. l is,-shown master
period oscillator 10, which receives as inputs the clock signals
(XTAL3 from 6.4 nanosecond crystal oscillator 12 and 8-bit time
set addresses (for stored desired period values3 and provides
outputs used by the plurality of local edge generators 16, one
of which is shown in Fig. 2. The timing circuitry shown in the
figures is used in an automatic circuit tester in which test
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patterns are provided to a large number of input nodes of a
circuit under test at high speed and the resulting outputs are
detected and compared with expected output.
Referring to Fig. 1, period oscillator 10 includes
presetable 10-bit master counter 18 and MSB period value random
access memory (RAM) 20 (10-bit by 256-bit), the outputs of both
of which are provided for comparison at coincidence detector 22
(plural exclusive or gates, the outputs of which are combined by
or gates), to provide an output to flip flop 24 when the count
at counter 18 matches the period value at the output of RAM 20.
MSB RAM 20 is addressed by addresses provided over 8-bit time
set address bus 19 ~rom address register 14. Flip flop 24 is
cloclced by XTAL signals and provides its output to crystal delay
26, which is also clocked by XTAL signals and can delay its
,15 output by l XTA~ signal when it receives a carry out signal on
its delay input 28 from 6-bit residue adder 30. Time set
.. address bus l9 is also provided to LSB period value RAM 32 (6
bit by 256 bit) and provides its output~to the B input of
residue adder 30. The 6-bit, S summation output, designated
RES(n), of residue adder 30 is connected to the input of
register 33, which provides its 6-bit output, d~signated
RES(n-l), to local edge generators 16 and to the A input of
residue adder 30. ~he S summation output of residue adder 30 is
also provided to proqrammable delay line 34, which provides an
output period pulse each time it receives a master end-of-count
(MEOC) pulse-from crystal delay 26, after delaying it a delay
interval indicated by RES(n). Programmable delay line 34 is a
, . . . . ... .. . ... . . .. _ ...... _ _ . _ .. _ .. . ...
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digital interpolator that has 100 ps resolution and can provide
delays up to 6.4 ns. The MEOC output of crystal delay Z6 is
also provided to reset master counter 18 and to clock address
register address 14.
Referring to Fig. Z, local edqe generator 16 includes
presetable 10-bit local counter 36, which is reset by MEOC
pulses, clocked by XTAL signals, and provides its 10-bit output
to coincidence detector 38, which also receives as an input the
output of MS~ time value RAM 40 (10-bit by 256-bit). The output
of coincidence detector is provided to flip flop 42, which is
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clocked by XTAL signals and provides its output to crystal delay
44, which is also clocked by XTAL signals. Crystal delay 44
includes two delay inputs ~6, 48, each of which is capable of
delaying the local end-of-count (LEOC) output of crystal delay
;~r15 44 to programmable delay line 50 by 1 XTAL signal. Delay input .
46 is connected to receive a carry out signal from 6-bit residue
adder 53, and delay input 48 is connected to receive a carry out
signal from 6-bit delay adder 54. LSB t~ime value RAM 52 (6-bit
by 256-bit) is also addressed by time set address bus l9 and
provides its output, designated REM(T~(n)/XTAL), to the A input --
of residue adder 53. The ~ input of residue adaer 53 receives
the RES(n-l) output from master period oscillator 10, and the
6-bit S summation output of residue adder 53 is provided to the
A input of delay adder 44. The B input of adder S4 receives a
deskew value, D~S, from deskew value generator 56 in order to
deskew the edge provided by edge generator 16 so that it is
synchronous with edges provided by edge generators for other
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channels. Generator 56 is reset by MEOC and receives control
signals, CNTRL, indicating a deskew value to be used. The 6-bit
S summation output (designated DELAY(n)) of deIay adder 54 is
provided by programmable delay line 50, which is a digital
interpolator having 100 ps resolution and provides an output
pulse each time it receives a pulse from crystal delay 44, after
delaying it a delay inter~ai indicated by the value of
DELAY(n).
Operation
In operation, period oscillator 10 provides period
pulses having programmed period values for cycle n, PV(n), that
are other than integer multiples of the crystal period, similar
to the operation described in St. Clair U.S. Patent No.
4,231jlO4. However, the residue value is not used to delay
;~15 crystal signals, to which are added further deïays in the edge
generators, as in St. Clair; instead the crystal signals, the
residue value, and the digital master end-of-count signal are
sent to all of the local edge generator~ 16; in which all delay
is added to the crystal signal at once.
Referring to Fig. 1, the integer values (designated -;
INT(PV(n)/XTAL) in Fig. 1), of dividing PV(n) b~ the crystal
period (XTAL) are loaded into MSB period value RAM 20, and the
remainder values ~in 100 ps increments) of this division
(designated REM(PV(n)/XTAL) in Fig. 1) are loaded into LS~
period value RAM 32. PV(n) can range from lg.2 ns (a minimum of
three crystal periods are needed to accommodate routing through
the circuitry to perform calculations) to 6.5 microseconds
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(2' crystal periods) and is one of the 256 values stored in
RAM's 20, 32. The period value, PV(n), is thus a summation of
the integer values loaded in RAM 20 (in clock period units~, and
. the remainder values loaded into RAM 32 (in 100 ps units).
Master counter 18 counts XTAL signals and provides its output to
coincidence detector 22, which provides a pulse to flip flop 24
when the count on counter 1~ equals the integer values provided
by MSB RAM 20. This is provided to flip flop 24, which on the
next XTAL signal provides a pulse to crystal delay 26, which on
the next XTAL signal (unless delayed by a carry out at input
delay 28) provides an MEOC pulse, which resets counter 18 and
clocks time set address register 14 to provide the next time set
address to RAMs 20, 32. The remainder value provided from LSB
RAM 32 to residue adder 30 is added to ~he value at input-A and
.,15 provided as a sum, RES(n), to delay line 34 and register 33.
Time delay line 34 provides a period pulse each time it receives
_ an MEOC pulse, after delaying it by the RES(n) value. Register
33, upon receiving an XTAL signal, provi~es its output,
designated RES(n-l), to indicate that it is one MEOC cycle
behind the input to register 33. The RES(n) value provided by
residue adder 30 to programmable delay 34 and t~ register 33 has
the value o~ the last 6 bits given by the following equation:
RES(n) = RES(n~ REM(PV(n)/XTAL)
where:
PV(n) = Programmed Period Value for cycle n,
XTAL , Crystal Period Value,
REM(x/y) = remainder of dividing x by y, and
RES(n) = Residue for the nth cycle (RES(0)-0).
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. Thus, if it is the beginning cycle, RES(n) simply
equals the remainder value that was provided by LSB RAM 32. In
subsequent cycles, RES(n) equals the summation of this value
plus the residue value from the precediny cycle, fed back from
the output of register 33. In this manner period pulses with
values PV(n) that are other than integer values of the period of
oscillator lZ are provided ~y counting an integer number of
clock signals to obtain an MEOC pulse and delaying the MEOC
pulse by the remainder value in the first cycle and delaying the
MEOC by the sum of the remainder and residue values in
subsequent cycles, to account for the fact that the prior period
pulse was not synchronous with a clock signal. Because the
oscillator has a ~.4 ns period, and programmable delay 34 adds
delays in increments of 100 ps, when residue adder 30 has
.15 counted to 64, it will overflow and provide a carry out, and the.
MEOC will once again be synchronous with the crystal signal, so
_~ a one-crystal-signal delay is provided at crystal delay 26. The
period pulse is used by a pa~tern gener~tor (not shoNn) to send
the next cycle's data to be foLmatted.
Referring to Fig. 2, edge generator 16 receives MEOC
pulses, XTAL signals, addresses on time set address bus 19, and
the RES(n-1) residue values from period oscillator 10. The MEOC
pulses reset counter 36, which counts XTAL signals and provides
its output to coincidence detector 38. The time value for edge
generator 16 for cycle n, TV(n~, is split up into some integer
number of crystal periods (designated INT(TV~n)~XTAL)) plus a
remainder value (designated REM(TV(n~/XTAL) in RAMs 40, 52, as
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- was the period value. When the value of the output of counter
36 matches the integer values in MSB time value RAM 40, a pulse
is provided to flip flop 42, which provides a pulse to crystal
delay 44 upon the next XTAL signal. The remainder value,
REM~TVtn)/XTAL), is provided to the A input of 6-bit adder 53,
which adds to this the residue value, RES(n-l), provided from
oscillator 10. The 6-bit summation of these values is then
provided to delay adder 54, which adds in any deskew value, DES,
from deskew value generator 56. The summation of these values
is then provided to programmable delay line 50. The delay value
thus is determined by the the last 6 bits of the number provided
by the following equation:
DELAY(n) = RES(n-l) ~ REM(TV~n)~XTAL) + DES
where:
.15 TV~n) = Programmed Time Value for cycle n, and
DES - deskew for local edge generator 16.
-_~ As in period oscillator 10, crystal delay 44 provides its LEOC
pulse to programmable delay 50, which a~ds to it a delay
interval, here DELAY(n). The two delay inputs 46, 48 are used
when ~-bit adders 53, 54 over~low and provide carry outs. The
output of programmable delay line 50 is a timing edge pulse,
which is used to generate an edge, used, e.g., with an edge from
another local edge generator to provide a data pulse to a
digital circuit being tested by automatic test equipment
employing the tim:ing signal generator. Thus the time value
TV(n) may differ from the period values PV(n), depending upon,
e.g., whether the time pulse is a beginning edge or an ending
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edge and the deslred pulse width. The DES values provide deskew
that varies depending upon the path to and through the generator,
whether the edge is used for rising or falling edges and whether
i-t is used in a driver or a detector.
There are substantial advantages associated with
providing pure crystal signals to local edge generators and
adding all delays at once. The timing system is totally
synchronous so that it is simple to manufacture and reliable in
operation. Only a pure crystal is fanned out to the system so
that transmission line inaccuracies do not contribute to timing
inaccuracies; residue and remainder delays are distributed and
added in the digital domain. Because there is only one crystal
phase, crosstalk is xeduced. Deskewed values are easily added
in the digital domain rather than the analog domain. There are
an absolute minimum of gates between the pure crystal signal and
the final timing signals, yielding improved accuracy by avoiding
having the ultimate timing signals based upon signals that have
passed through a plurality of gates, each of which adds some
distortion.
Other Embodiments
Other embodiments of the invention are within the scope
of the following claims. E.g., the timing system would have
application in circuitry othex than multiple-channel automatic
circuit testers, in particular circuitry requiring precise
timing edges that can be varied on a cycle-by-cycle basis.
