Note: Descriptions are shown in the official language in which they were submitted.
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A~l MATIC TF,ST EQU I PMENT FOF< I NTEGRATED CI RCU I TS
Technical Field
This invention relates generally to test
equipment for electronic circuits, and more particu-
larly concerns test equipment which automatically pro-
duces an analog "signature" of selected nodes of the
electronic circuit, such as the pins of integrated
circuits, converts the signature signal into corres-
ponding digital values and then compares those digital
values with stored reference digital values developed
rom the same selected nodes of an electronic circuit
known to be good.
sackground Art
The development of the integrated circuit (IC)
has been one of the most significant technical advances
in the twentieth century. Furthermore, continuing re-
search and development has produced successive signifi-
callt advances. In application, several integrated
circuits are often combined on a single circuit board
to form electronic systems. Further, such circuit
boards a.e also connected together electrically to form
complex electronic systems/apparatus. The use of such
circuit boards is advantageous in that they may be
conveniently replaced when one or more of the individ-
ual ICs on tile board degrades or fails.
The advances of integrated circuit technol-
ogy, however, have brought the challenge of quality
control and circuit repair. This requires apparatus and
methods ~lhich are specially adapted for testing the
" ~ 1~84~33
operating condition of electronic circuits which in-
clude individual ICs, as well as other circuit ele-
ments, both active and passive, which are connected to
the ICs.
The importance of quality control is self-
evident, as the replacement of inoperative boards due
to IC failure is expensivet as well as requiring sub-
stantial valuable time of trained personnel. Prompt
and accurate rèpair of circuit boards is a].so becoming 1-
increasingly important, again due to the cost of repair
time, as wel.l as the large number o expensive circuit
boards.
One significant difficulty in the repair of
circuit boards is that a board may be rendered in-
operative by the failure of a portion of an IC or just
one or more other circuit components, which may be dif-
ficult Jo locate, particularly in-circuit. A large
number of circuit nodes, including the individual pin
connections of the ICs, typically must be tested to
identiy the circuit faults.
Apparatus for testing integrated circuits is
known, and insofar as they are designed to provide an
automatic sequential interrogation of the individual
pin conn~ctions of an IC under test without operator
intervention, such apparatus is referred to as auto-
matic test equipment (ATE). However, such equipment,
which is available from only a few manufacturers, have
the significant limitations of being expensive and
quite sophisticated in operation (usually also includ-
ing sophisticated software), as well as requiring atrained operator. Further, even such expensive and so-
phisticated equipment have proven to be somewhat unre-
liable with respect to accurately ascertaining the con-
dition of the circuit under test a~d identifying its
f a u 1 t s .
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~` 3
As an alternative to expensive and sophisti-
cated ATE, relatively inexpensive ~emiconductor test-
ers have been developed which have proven to be ex-
tremely useful for an individual technician who is
involved in the repair or "troubleshooting" of inte-
grated circuits and other semiconductor devices. Such
apparatus is disclosed in U. SO Patent No. 3l973,198,
issued on 3 August 1976 in the name of Bill Hunt, and
U. S. Patent No. 4,074,195, issued on 14 February
1978,also in the name of Bill Hunt, both of which are
owned by the assignee of the present invention.
The apparatus described in the above two pat-
ents includes circuitry which obtains an analog "sig-
nature" representating the operating condition of indi-
vidual semiconductor junctions when the junction is
in-circuit. The analog signature is displayed on a
CR'r, which is typically an integral part of the appara-
t~s. A trained operator can interpret the signature to
identify failed junctions or components. The rela-
tively low cost of the apparatus permits its purchase
in large numbers by organizations having large repair
facilities as well as by individual technicians.
However, a significant disadvantage of such an
instrument in some instances, such as in the testing of
ICs, is that the testing must be done manually, i.e.
pin-by-pin. The operator is at least required to in-
spect the displayed signature of each pin of the IC
under test and in some cases must manipulate test leads
or switching equipment manually for each IC pin connec-
tion.
Testing of circuit boards which include a
number of ICs is thus quite slow with such apparatus,
which may in effect preclude the use of such apparatus
in many applications, including quality control, even
though the information that may be obtained about the
condition of the ICs and other circuit components by
4~;~3 ~~
us~ of th~ apparat~s is more complete and reliable
than that obtained by much more expensive and sophis-
ticated test equipment. Another disadvantage is that
such apparatus typically does require a trained opera~
tor, who must examine the si~nature of each junction
a~d make a judgment as to whether it is satisfactory.
rrhus~ the~e is a need for test equipment which
is substantially as fast as, but less expensive than,
e~isting ~TE and which reliably and accurately tests
integrated circuits and other elements in electronic
circuits, including identifying those circuit nodes in
the el.ect~onic circuit having signatures which are
sufficiently different than normal to merit further
evaluation.
[~isclosure of the Invention
Accordingly/ the present invention is an appa-
ratu.s for testing electronic circuits which comprises:
me"ns for connecting an electronic circuit to be
tested to the testing apparatus; means for developing
an analog signature signal for selected circuit nodes
of the electronic circuit being tested, the analog
signature being indicative of the operating condition
o~ the circuit relative to the selected node; means
for producing a digital value representative of said
analog signature; means for establishing and storing
reference digital values; and means comparing the
digital representation for each selected circuit node
obtained by the testing apparatus from the electronic
circuit under test with reference digitial values for
those same circuit nodes of the same electronic circuit
and then identifying those circuit nodes which do not
have a di~ital representation which is within a se-
lected range relative to said corresponding reference
digital values.
srief Des~ tion of the Drawings
Figure 1 is a block diagram of the appara~us
o~ the present invention.
Figures 2A-2B are flow chart diagrams of the
firmware which controls the overall operation of the
dpparatUS of Figure 1.
Figures 3A-3D are flow chart diagrams of the
software which controls the testing of the electronic
system under test.
Best Mode For Carrying Out The Invention
The present invention combines the functions
o~ an allalog ;ignature semiconductor tester, such as
that shown and described in the '198 and '195 patents~
with apparatus capable of providing an automatic com-
~arison of the signatures of successive nodes of an
electrorlic circuit (system) under test against a pre-
viously stored standard, referred to as reference val-
ues. The system under test will typically comprise a
circuit board which includes a number of separate inte-
grated circuits as well as other active circuit compo-
nents such as transistors and diodes and passive compo-
nents such as resistors, capacitors and inductors.
1'his requires the conversion of the analog
signatures developed from the circuit nodes into corre-
sponding digital values, as well as the establishment
of reference digital values for each circuit node in
the system under test, wherein the reference values are
typical;ly developed from a known good circuit board.
The apparatus of the present invention, typically util-
izing a' personal computer, automatically compares the
digital values of each circuit node of the system
under test with the stored reference values, under the
control of system firmware and software. Any differ-
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~ences outside of a given range for a particular node results inthe analog s~gnature for that node be~ng d~splaYed for evaluation
by an operator.
F;gure 1 is a structural block diagram of the ATE
apparatus of the present invention, referred to generally at 10.
The ATE apparatus 10 includes a semi-conductor junction test
instrument 12, which i~ designed to provide a visible analog
signature of a selected circuit node. The vislble analog
signature is a display on a CRT 14, which is typically integrated
into the test instrument 12. The analog signature is the
response of the system under test at the selected circuit node to
an interrogating signal from the test instrument 12. The test
instrument 12 supplies the interrogat;ng signal, and produces
"horizontal" and "vertical output signals at outputs 16 and 18
thereof. The characteristics of these output signals depends
upon the condition of the circuit, relative to the selected node.
The signals are applied, respectivelY~ to the
horizontal and vertical inputs 22 and 24 of the CRT 14. The
horizontal and vertical signals produce the analog signature on
the CRT 14. A semiconductor tester generally suitable for use in
the present apparatus i8 shown and described in United States
Patents No. 3,973,198 and No. 4,974,195, referred to above.
The signal information used by the semi-conductor
tester 12 to produce the horizontal and vertical output signals
is obtained by means of a se~ of input connectors 24 located on
the face of the instrument, as well as a set of relay contacts
26, and a set of relay drivers 28. In the embodiment shown,
there are four input connectors, each of which corresponds to the
particular configuration of IC, including a 40 pin zero insertion
force (ZIP) connector for dual-in-line (DIP) packages, a 20 pin
connector for cabling to ICs with
84~3~ ~ J
20 pins or less; a 40 pin connector for cabling to ICs
~ith 40 pins or less, and a 64 pin IDC connector for
cdbling to ICs with 64 pins or less. It should be
~nderstood, however, that other input connectors could
be provided, including edge connectors. The purpose of
the input connector is simply that of a connection
device to provide unique connection to each pin of the
IC.
Typically, the particular circuit nodes to be
tested of the system under test are the pin connections
of integrated circuits on the circuit board, so that
the connection devices of the present apparatus are
typically arranged to accommodate integrated circuits.
However, electronic probes, either fixed or movable,
could be used to connect the test apparatus of the
present invention to the circuit nodes to be tested as
well. Conceptually, a large number of fixed probes
could be used to provide a so-called "bed of nails"
connection approach to a given circuit board under
test.
Typically an individual IC of the circuit
board under test is connected to the correct corres-
ponding input connector by means of a cable 32 which
has a socket on the end thereof which is adapted to re-
ceive the IC to be tested. The input connector circuit
block 24 includes 64 output signal lines, one for each
pin connection for the IC having the largest number of
connections to be tested, which is in the embodiment
shown is 64. It should be understood, however, that
more connections, i.e. 4096 and more, could be pro-
vided, to accommodate other ICs.
The signal lines from input connector block 24
extend into relay contact circuit 26. The relay con-
tact circuit 26 in the embodiment shown comprises two
banks of 64 relays. Such an arrangement permits any one
of the 64 signal lines from the input connector cir-
:.:
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cuitry to be routed to the test line and/or common lineoutputs 36 and 38 of the relay contact circuit and then
to corresponding inputs of the semiconductor junction
tester 16.
The relay driver circuit 28 controls the
operation of the relays in the relay circuit 26 in
conven~ional fashion, under the control of the control
interface circuit 48 which contains the system control
firmware, which in turn will be explained in more de-
tail hereinafterO '~'
The semiconductor tester 12 provides an
excitation (interrogation) signal, such as a triangle
wave or a sinusoid, through the relay contact circuit
26 and the input connector 24 to one circuit node (pin
connection) of the system under test. The test line 36
is for the pin connection to which the test signal is
applied, while the common line 38 is connected to a
reference pin of the IC. The tester 12 produces hori-
zon~al and vertical signals at outputs 16 and 18, in
response to the excitation signal directed to the indi-
vidual circuit node. Those signals are then applied
to the horizontal and vertical inputs 22 and 24 respec-
tively of the CRT 14, which as mentioned above is typi-
cally integrated into the semiconductor tester.
The analog signals at outputs 16 and 18 of
the semiconductor tester 12 are also applied to hori-
zontal j and vertical inputs 40 and g2 of the
integra~or/A-D converter circuit 44. These analog sig-
nals could, as an example, be sinusoids of different
tor the same) magnitudes. Howeverr these signals must
be converted to a digital format for processing by the
remaining circuitry of the present invention. The
func~ion of the integrator/A-D converter circuit 44 is
to produ,ce digital signals representative of the analog
signals àt inputs 40 and 42.
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Digitizing the analog signals at high sam-
pling rates in conventional fashion requires a substan-
tial amount of memory and would slow the signal proc-
essing. In the embodiment shown, the digital values
are obtained by first separating the analog signals
into their respective positive and negative components
over one cycle. Each component is then integrated over
a fixed time interval, using standard analog integra-
tion circuitry, to produce a DC voltage proportional to
the area under the curve of the positive and negative~l-
components of each signal. This integrated signal is
sampled and temporarily stored and then converted into
a digital signal.
These functions all occur within the one cir-
cuit 44, and are accomplished for the positive and
negative components of each signal, so that for one
cycle, i.e. ~ero to 2 ~ , four digital values result.
These four digital values comprise the digital repre-
sentation of the analog siynature of the particular
circuit node being tested.
The digital signals from the integrator/A-D
converter 44 are then applied over a data line 46 to a
control interface section 48. The control interface
section 48 is "intelligent" in the sense that it con-
~ains fir~llware in the form of a microcomputer with a
stored program in a programmable read-only memory
(PROM). Section 48 functions as an interface between
the computer 50 and the rest of the apparatus. Commu-
nication with the computer 50 is by a standard RS-232
interface. In operation, section 48 receives instruc-
tions ~rom the software in the computer 50 and executes
those instructions, thereby controlling the operation
of the apparatus, specifically, the timing and opera-
tion of the relay contacts 26, the relay drivers 28,
the semiconductor tester 12, and the integrator/A-D
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converter 44. The operation of the control interface
48 and the firmware therein will be described in more
detail hereinafter.
I`he digital values at the data input ~9 of the
interface section 48 are applied to the computer 50
through the ports of the RS-232 interface. In the èm-
bodiment shown, the computer 50 is an IBM personal
computer which, under the control of application soft-
ware, compares the digital values obtained by the test
instrument for a particular circuit node with stored 9-
~reference digital values for the same circuit node for
a known good board. The software in the embodiment
shown includes five modules, including a structure
module, a t~st module, a learn module, a report mod-
ule, and a system function module. The software will
be described in more detail below.
In the function of the apparatus, data in the
form of reference digital values is stored in the
memory of the computer 50 for each circuit node of the
electronic system to be tested by the apparatus. The
stored re~erence digital values are those known to be
good and are typically established by actually testing
all electronic circuit known to be operable and then
storing those tested digital values. In a possible
alternative embodiment, the apparatus could be arranged
to directly receive and store reference digital value
information, which may, for instance, be supplied by a
manufacturer of the particular circuit. The reference
values are usually in the form of a range, or accepted
band, i.e. high/low.
As the same circuit board is tested in actual
use of the apparatus, actual operable values may be
discovered which are outside the originally established
range. The reference value range may then be modified
accordingly, if desired.
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These reference ranges are in effect maxirnum
and minimum digital values~ and are referred to as "an
~nvelope" of acceptable reference values. As described
above, the envelope will typically gradually increase
in use of the apparatus~ as thé total number o~ te5ts
by the apparatus increasesO Thus, the more testing of
a particular syste~, the more accurate the boundaries
of the envelope will become, if the testing results are
"learned" by the computer, i.e. if the stored reference
values are changed accordingly. The high/low range
envelopes for each of the four digital values for each
system under test is thus stored in memory in computer
50. Each circuit board or other system under test has
s~ch information in memory.
In the actual test procedure, circuit boards
30 containing individual ICs to be tested are connected
by an appropriate connector clip through a connecting
line 32 to the corresponding input connector 24. The
various pin connections of the lC are then automatic-
ally processed in sequence by testing each node/pin
connection and developing a set of four digital values
for each circuit node representative of the analog sig-
nature thereof, as explained above.
~ The set of digital values for each pin con-
nection~of the IC are then supplied to the PC 50,
where each set of digital values is compared with the
reference digital values for that node (pin connection)
in memory. Each node having digital values which fall
outside the envelope of stored reference values is
flagged, and at the end of the testing of the system,
the complete analog signature of each questionable pin
connection of each IC is presented for review by the
operator. Typically, but not necessarily, the circuit
node having the worst, or most different, values, will
be presented first; i.e. the circuit nodes to be re-
viewed are prioritized in terms of quality~
12 ~ 4~ ~
The analog signature of each questionable
circ~it node is displayed on the CRT 14, permitting
the review which the semiconductor tester 12 typically
provides to the operator for evaluation of a particular
junction. If the analog signature developed at a given
pin connection in the system under test is determined
to be bad by the operator, then that IC is replaced.
The circuit board may then be tested functionally to
determine whether or not the fault has been corrected.
The above process continues for each IC in ~J~'
turn for the board being tested. The testing process
is automatic, and thus quite fast, in the first step of
the test procedure, in which the apparatus accomplishes
the testing of each selected circuit node. The ques-
tionable pin connections are then reviewed by the op-
erator in detail, in the second testing step. The
overall testing procedure is thus substantially auto-
matic, because relatively few pin connections for a
giv~n IC will be questionable, requiring operator re-
view.
Fiyures 2A-2B show a flow chart for the firm-
ware in the control interface 48. The interface 48
receives instructions from computer 50, executes those
instructions, if valid, to control the various sections
in the apparatus, and transfers the digital values for
the particular node being tested generated by the
integrator/A-D converter 44 to the computer 50 for
actual processing.
At the start of operation of the apparatus,
the system hardware is first initialized via the firm-
ware, including the timers, the relays and the various
data ports. The hardware is initialized by setting the
lines to their proper state and clearing/loading the
memories and registers. The firmware then waits for an
instruction from the software.
13 ~ ~4~
~ hen an instruction is received, it is saved
in memory, The instruction is then processed to deter-
mine first whether it is a system instruction. If it
is, then the system instruction subroutine is imple-
mented. The system instruction subroutine is a re-
initialization of the hardware and software. If it is
not a system instruction, the instruction is processed
to determine whether or not it is an invalid instruc-
tion. If it is, the invalid instruction subroutine
(~igure 2B) is implemented. The invalid instruction is~-
ignored and the system returns for the next instruc-
tion.
If it is not an invalid instruction, there isan inquiry as to whether the instruction is diagnos-
tic. If the instruction is diagnostic, it will be one
of the instructions sho~n in Figure 2B. The diagnostic
tests verify operability of certain hardware elements.
For instance, by reading the ROM information, the cor-
rect program infor~ation for that ROM can be verified.
The "Hello message"test verifies the communication link
~etween the computer 50 and the rest of the apparatus.
The test relay controller test results in a checking of
whether or not the relay control logic is functional.
The power supply test instruction tests the voltages on
the circuit cards while the quadrature status instruc-
tion tests the integator/A-D converter.
Referring to Figure 2B, if the instruction is
a test instruction, it is first decoded and then it is
executed. The various test instructions are shown in
the flow chart. The size of the dual-in-line (DIP) or
single-in-line (SIP) connectors is first set. The
range for the tester is then set and the test and com-
mon pins are set or reset as required. The appropri-
ate relay contacts close accordingly and the analog
sigrlature signal is developed and then converted into
corresponding digital values, as explained above~ The
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4;~
read test pin instruction then transfers the digital
test values to the PC 50 for comparison with the refer-
ence diyital values. This processing is carried out by
the software in the computer 50.
The flow chart for the software in the com-
puter 50 is shown in Figures 3A-3D. In the embodiment
shown, computer 50 is a microcomputer, such as an IBM~
PC, XT, or AT, and the software is provided on a floppy
disk. As shown in the flow chart, there are three basic
operation modes, encompassing five main routines, in- ~-
cluding a system routine which concerns security mat-
ters such as passwords and the like. The three modes
include a "structure" mode, a "learn" mode and a "test"
rnode. In the embodiment shown, each mode has a menu
format which is used to guide the user through the
operation of the mode. There is a master menu for each
mode and also a menu for each routine or utility pro-
gram in the mode. Each mode typically will consist of
1 or 2 principal routines and several utility programs.
,The structure mode comprises those routines
and programs (Figure 3A) by which the apparatus obtains
information concerning the structure of the systems to
be tested. The information is divided into a hierar-
chy. "System" refers to the identity of the complete
apparatus, such as for example an IBM PC; "unit" refers
to a separate portion of the system, such as a printer
or keyboard; "board" refers to the particular circuit
board in the unit; "section" refers to a functional
circuit within the board, such as a power supply, and
"comp", or component, refers to an element in the
section, such as a particular IC or other component.
ldentifying information is provided to the
computer 5~ about each of the above under the "enter
structure" routine, as well as special instructions.
rhe amount of disk space that the above information
.
1~4~
requires is automatically calculated by the software
For instance~ the number of pins, the identification of
the comrnon pins and the manufacturing date of the board
is typical information provided a~out the boardD Under
both the system and the unit headings, only the name of
the system/unit and the number of units/boards compris-
ing the system/unit are providedO The "add to struc-
ture" and "edit structure" routines permit the operator
to add or edit information relative to each portion of
the structure. -;
In the "learn" routine, as shown in Figure 3C,
the reerence digital values for each IC are developed.
This is accomplished typically by connecting an oper-
able IC to the apparatus through the input connectors
24 and obtdining digital values concerning each circuit
node. The name for the system is first entered, i.e.
such as an IBM PC, and then the names of the unit,
board and section. The digital values for the circuit
node are then transferred into memory and become the
reference digital values. If the learn mode is to be
used beyond this initial establishment of information
of the same system, a comparison is made between the
new values and the originally stored values, and an
indication is provided if the originally stored values
are exceeded. The new values are not entered unless the
operator operates the "data OK" key. This provides a
safety feature to protect the reference values.
~ he software then requests certain information
concerning the component source of the new values,
including the manufacturer, the date of manufacturer
and the I.D. number of the board.
In the edit routine, the learned values remain
unchanged, but identifying information concerning the
learned board, such as the name of the component manu-
~acturer, the date of component manufacture, etc. may
be changed.
`` 16
In this pdrtieular embodiment, the software is
~omewhdt limited so boards are l~arned by sections,
e~en though the identification is on the basis of an
~ntire board. ~his should not, however, be considered a
limitation on the scope o~ the inventionO
In the "test" mode, the apparatus performs a
test on the electronic circuit under test at a selected
circuit node, as described above. The test mode in-
cl~des three test methods, including a prioritized
fa~lt ~est method, an immediate fault test method, and
a single component test method. The test mode further
includes a "view" operating mode, which permits the
operator to view the analog signature of any circuit
node, without any data comparison or other function,
and also includes a ~Iprobe~ operating mode, in which
relays are disabled so that only the probes of the
apparatus are energized.
In the prioritized fault test method~ all the
circuit nodes in one section are first tested. Then a
tro~blesheet listing in a priority orderO beginning
with the most different, the nodes which did not fall
ithin thc reference ranges is prepared. The analog
signatures for those nodes are then viewed in that
priority order.
In the immediate fault test method, each cir-
cuit node, i.e. pin connection, of a given IC in a
selected section of a board is tested, but no trouble-
sneet is developed. At the conclusion of the testing
of the IC, those pins which did not pass the comparison
are then viewed, typically in priority order.
I'he single component test enables the operator
to test any one component on any one particular board.
If a possible fault is determined, the analog signature
of thdt component will be viewed.
`~ 17 ~ ~ ~4~
, .
ln the report mode, which is set out in Eigure
3C, the operator may examine any of the stored files,
either on the computer display or in printed fo~m~ In
the system report, a list of the systems on file is
displayed~ In the embodiment shown, a single screen
includes 20 systems. The screen information may then
be printed, if desired.
In the "structure" report, the various units,
boards, sections and components are shown in seguence.
All ~he information in the file previously entered into
memory concerning the particular structure selected may
be viewed. In the learn report and learn screen rou-
tines, the informatior. in the report or on the screen
is learned by the apparatus~ i~e. stored into memory as
part of the file.
The software also contains a security routine
by which the passwords are maintained~ Further, the
apparatuls includes a hierarchy of software/hardware
settings which may be varied by the user, depending on
the sophistication of the user. In some instances, the
settings will enable the user to make only relatively
few changes, while in other instances, the user will be
able to make several changes. File maintenance is also
included. The format of the disks may be changed,
entire systems may be deleted, or just certain data
about the system may be deleted.
Thus, an apparatus has been disclosed for
testing electronic circuits which combines an auto-
matic test capability with a capability of reviewing
analog slgnatures of selected circuit nodes, including
the pin connections of an IC which is a part of the
electronic circuit. The apparatus is fast, yet reli-
able in ascertaining circuit faults, and has the fur-
ther advantage of being relatively inexpensive com-
pared to existing automatic test equipment.
4~
Although a preferred embodiment of the inven-
tion has been disclosed herein for purposes of illus-
tration, it should be understood that various changes,
modi~ications and substitutions may be incorporated in
s~lch embodiment without departing from the spirit of
the invention as defined by the clairns which follow.
