Note: Descriptions are shown in the official language in which they were submitted.
~4~
P~-~ 40508 l Zo.1~1987
Display control apparatus.
Background of the invention.
Field of the invention.
This invention is in the field of CRTs (cathode
ray tubes) and more particularly to controls for providing
signals and corrections for controlling the CRT display.
Discription of the Prior Art.
CRTs characteristically have display distortions
including geometric, astigmatism, focus , shading and/or
convergence distortions. As used herein, "geometric"
corrections are those corrections necessary to place a
point displayed on the screen at the exactly correct
horizontal and vertical coordinates. Numerous efforts
have been made to provide corrections and signals for
distortionless CRT displays. The disclosures in the
following U.S. Patent Nos. are representative of such
efforts: 4,095,137; 4,240,073; 4,386,345; and 4,410,841.
While these systems attempt to provide distortion correc-
tion signals and distortionless signals based on data
stored in memories, the manner in which the data are
stored and/or used in the display control system limit the
versatility and application of these systems.
Summarv of the invention.
A CRT has an electron beam that is focussed and
deflected to provide a display as is understood in the art.
The hDrizontal and vertical deflection signals, also
defined as the x and y deflection signals, respectively,
for the CRT display are buffered, sampled at a high samp-
ling rate and digitized and used to address one or more
ROMs (read only memories) in which are stored correction
data or signal data for each of a large number of point
locations on the CRT display. The buffers provided for each
of the x and y deflection signals each have scaling and
q~
'3~
P1lA Lloso8 2 20.12. 1987
centering adjustments that can be made for a one time
setup. Typically for stroke writt;en and raster scan CRT
systems there is a separate ROM for geometric corrections
of each of the x and y deflection signals. In addition
a separate ROM is provided for each group of astigmatism
coils, the dynamic focus coil, shading in the video
amplifier circuitry, and, if a color CRT is used, the
convergence coils.
The ROMs are simultaneously addressed by the x
and y digital signals. The addressed digital corrections or
signals are clocked out by latches at the sampling rate
and converted to analog signals. The x and y digital
geometric corrections are converted to analog corrections
by MDACs (multiplying digital to analog converters)
which are coupled to the x and y deflection signal
sources to provide a sliding reference to the MDACs
resulting in smoothing the steps in the ROMcampled
outputs. The outputs of the MDACs are buffered and
processed by analog delay line filters that break down a
large step to multiple smaller steps to further smooth the
ROM sampled outputs and thus provide a substantially smooth
continuous display which is especially important in
stroke written systems.
The stepped nature of the sampled outputs of the
remaining ROMs, e.g. those having astigmatism, dynamic
focus, shading and convergence data, are not as objectiona-
ble as in the deflection correction data and therefore the
aforementioned smoothing operations are not as critical.
An instantaneous beam current correction ROM is
provided that effectively takes the product of an
operator entered brightness setting and the writing rate
in a stroke written syste~ The digital correction of this
ROM issampled by a strobed latch and then converted to an
analog signal and summed with the dynamic focus signal to
thus provide exact focus corresponding to x, y position
and corrected for instantaneous beam current.
i'3~
20l04-a462
A dec~c)de l-.gic circuit i~ provide-l haviny L~Ds (liyht
emitting diodes) tc, indica~e ~7h~n each of the x and y deflection
waves are properl~l ~caled and centered by means of one time
adjustments to make maxirnum use of the CRT display. The decode
logic also provide~ a signal for momentary offscreen signals for
inhibiting the system during offscreen intervals.
In sumrnary, the present invention provides display
control apparatus for use with a CRT having an electron yun beam
and an electron beam activated screen, x and y analog signal
sources for providing, respectively, horizontal and vertical
deflection of the electron beam, and haviny at least one CRT
display control member, characterized in that it comprises: memory
means for storing and addressing digital data; first analog to
d:igital converter means coupled between the x analog signal source
and said memory means for converting the x analoy deflection
signal to a corresponding x digital deflection signal; second
analog to digital converter means coupled between the y analog
signal source and said memory means for converting the y analog
deflection signal to a corresponding y digital deflection signal;
sampling means coupled to said first and said second analog to
digital converter means for simultaneously sampling each of the x
and y digital signals, whereby an x, y digital sample set is
provided from said first and said second analog to digital
converter means; each of said sample sets corresponding to a
respective predetermined point location on the screen; said point
locations being spaced one from another over a predetermined
portion of the entire viewed area of said screen; said memory
means for storing digital data relating to at least one CRT
display control member for each of said digital sample sets; said
memory means for using said x, y digital sample sets to address
said digital data; digital to analog converter means coupled to
said memory means for converting said addressed digital data to
corresponding analog signals; coupling means for coupling said
digital to analog converter means to the display control member;
whereby each of said digital sample sets provides an address for
respective digital data in said memory means to provide real time
, ~,
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20104-8462
geometrically corrected analoy signals to the display control
memher.
According to anvther aspect, the invention provides
display control appara-tus for use with a cathode ray tube having
an electron gun heam and an electron beam activated screen and
having hori~ontal and vertical deflection windings coupled to x
and y analog deflection signal sources, respectively,
characterized in that :it comprises: firs-t memory means for storiny
digital geometric corrections to the x deflection signal for each
of a predetermined number of x, y signal sets, each x, y signal
set corresponding -to a respective predetermined geometrically
correct point location on the screen; second memory means for
storing digital yeometric corrections to the y deflection signal
for each of said predetermined number of x, y signal sets; first
analog to digital converter means coupled between the x analog
signal source and each of said first and second memory means and
for converting the x analog deflection signal to an x digital
deflection signal; second analog to digital converter means
- coupled between the y analog signal source and each of said first
and second memory means and for converting the y analog deflection
signal to a y digital deflection signal, so that an x digital
correction signal is called from said first memory means for each
x, y signal set and a y digital correction signal is called from
said second memory means for each x, y signal set; first and
second digital to analog converter means coupled to said first and
second memory means, respectively, for converting the x and y
digital correction signals for each of said predetermined number
of x, y signal sets to x and y analog correction signals,
respectively; first summing means coupled to said first digital to
analog converter means and to the x analog signal source for
summing said x analog correction signal to the x analog signal to
provide a corrected x analog deflection signal; second summing
means coupled to said second digital to analog converter means and
to the y analog signal source for summing said y analog correction
signal to the y analog signal to provide a corrected y analog
deflection signal; whereby the x and y analog deflection signals
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2010~-8~6~
are real time geometrically corrected to provide x and y analog
signals to the x ancl y deflection windings respectively so that
the x and y deflection windings ~7ill precisely position the
electron ~Jun beam at said respective predetermined geometrically
correct point locations on the screen.
It is therefore an oh-Ject of this invention to provide a
display control for a CRT that has improved fidelity, versatility
and application.
An objec-t of this invention is to digitally convert ancl
sample the analog horizontal and vertical deflection siynals to
obtain digital x, y sample sets which are used to address a memory
that stores digital corrections for a predetermined number of
point locations spaced over the face of the C'RT display,each
sample set corresponding to a respective point location.
Another object of this invention is to provide a
geometric correction from a digital memory to the analog
horizontal and vertical deflection signals in a CRT for each of a
predetermined number of point locations on the CRT display.
A further object of this invention is to provide in the
apparatus of the previous object an MDAC at the output terminal of
the digital memory to smooth the stepped output from the memory.
A still further object is to couple the output terminal
of an MDAC of the previous object to an analog delay line filter
to provide multiple small steps in place of each larger step in
the output from the MDAC.
An object of this invention is to couple the x, y sample
sets of the previous objects to memories that store data for at
least one of astigmatism, dynamic focus, shading and convergence.
A still further object is to provide in the apparatus of
the previous objects in both a stroke written display system and a
raster scan system a beam
3b
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PJ-TA Ll0508 4 20.12.1987
current correction for the dynamic focus.
Another obJect is to provide in the apparatus
of the previous objects an LE~ for each of the x and y
digital signals to indicate full range operation to aid in
system adjustment and to provide an offscreen signal to
inhibit display data.
The above mentioned and other features and
objects of this invention and the manner of obtaining them
will become more apparent and the invention itself will be
lO best understood by reference to the following description
of an embodiment of the invention taken in conjunction
with the accompanying drawings.
Brief Description of the drawings.
Figs. lA, 1B, collectively, show a block, partly
schematic, simplified diagram of an embodiment of this
invertion, the connection points C-L in Fig. lA being
connected to points C'-L' in Fig. lB, respectively,
Fig. 1C is a block diagram of a reference
voltage generator for providing a reference voltage to
terminals 224' in Figs. 1A and 1B;
Fig. 2 is a block diagram of an analog delay
line and filter used in the embodiment of Fig. 1;
Fig. 3 is a waveform of a signal at the input of
the filter shown in Fig. 2;
Fig. 4 is a waveform at the output terminal of
the filte. shown in Fig. 2;
Fig. 5 is a waveform similar to the waveform of
Fig. 4 but with the capacitor in the Fig. 2 filter made
larger; and
Fig. 6 is a block diagram of a decode logic cir-
cuit and display inhibitor circuit for use in this inven-
tion and having connection points A', B' that are connected
to points A, B, respectively, in Fig. 1A.
Description of the preferred embodiment(s).
Referring to Figs. 1A, 1B color CRT 20 has three
37)
Pl~ 40508 5 20.12.1987
electron guns 24, 26, 28 that emit electron beams for the
red, green and blue phosphor dots, respectively, on CRT
screen or display 30 as is understood in the art. x and y
deflection coil group 32, astigmatism nos.1 and 2 coil
assembly 36, static and dynamic focus coil assembly 40,
and red, green and blue convergence coil assembly 44 are
all positioned about neck 46 of CRT 20 in conventional
manner for a three gun color CRT although other type
CRTs may be used.
x deflection source 50 and y deflection
source 52 provide analog x, y signals respectively for the
horizontal andvertical deflecti~n, respectively, of the
electron beams from guns 24, 26, 28. Source 50 is coupled
to buffer 54 having scaling potentiometer 56 returned
to ground 57 for a one time setup to match the x deflection
amplitude to the horizontal dimension of screen 30.
Source 52 is coupled to buffer 60 having scal-ng
potentiometer 62 for a one time setup to match the y
deflection amplitude to the vertical dimension of screen
30.
Orthogonality potentiometer 66 is coupled
between input terminal 68 of buffer 54 and output terminal
70 of buffer 60 and provides for a one time setup for
establishing orthogonality between the x and y signals
as finally viewed on screen 30.
Flash A/D (analog to digital) converter 72 is
a very high speed converter known to the art and is
coupled to output terminal 74 of buffer 54 and converts
the x analog deflection signal to a six bit digital signal
on six parallel lines76 and a twobit digital signal to
terminal A for overflow and underflow indication on two
parallel lines 78 at a 10 MHz clock or sampling rate
provided by clock generator 80 which is coupled to
converter 72 on line 81. Centering potentiometer 58, retur-
ned to ground 57 , is coupled to buffer 54 for a one timesetup to center the limits of the horizontal signal to
suit the input requirements of converter 72 and scaling
potentiometer 56, returned to ground 57, is coupled to
3~)
PHA 40508 6 20.12.1987
huffer 54 to scale the buffer output to correspond
to screen 30 dimensions. In the drawings parallel
coupling lines are symbolized by a slash "/" .and a numeral
to indicate p~rallel lines of a number equal to the
numeral. Other sampling rates may be used depending on the
application and on the signal frequency.
Flash A/D converter 82 is a very high speed
converter known to the art and is coupled to output
terminal 70 of buffer 60 and converts the y analog
deflection signal to a six bit digital signal on six
parallel lines 86 and a two bit digital signal to
terminal B for oveJflow and underflow signal on two parallel
lines 88 at a 10 MHz block or sampling rate provided by
clock generator 80 which is coupled on line 81 to conver-
ter 82. Centering potentiometer 64, returned to ground 57,is coupled to buffer 60 for a one time setup to center
the limits of the vertical signal to suit the input
requirements of converter 82 and scaling potentiometer
62, returned to ground 57, is coupled to buffer 60 to
scale the buffer ~tput to correspond to screen 30
dimensions,
Lines 76, 86 carrying the digitized, x, y signal
amplitude information, respectively, from converters 72,
82, respectively, are coupled on six parallel lines to each
of x deflection geometric correction ROM 90~ y
.~ef]ectinn geometric correction ROM 91, astigmatism 1
ROM 92, astigmatism 2 ROM 93, dynamic focus ROM 94,
shading ROM 95, and convergence ROM 96. Additional ROMs
for additional functions may be used. In the embodiment
disclosed herein~ each ROM 90~96 has 4096 eight bit data
storage locations, Other size memories and other type
memories, such as PROM (programmable read only memory)
may be used for other applications.
Each x, y sample set of the digitized x, y
signals c~responds to and is the address of a respective
point location on screen 30 of the electron beam from
each of guns 24, 26, :28. Thus in the embodiment disclosed
~ x ~
P~ 40508 7 20.12.1987
there are 4096 different x, y sample sets and each sample
set corresponds to and is the address of a respective
point location on screen 30. Each x, y sample set addresses
a corresponding geometric deflection correction in each of
5 ROMs 90~ 91; a corresponding astigmatism entry in each of
ROMs 92, 93; a corresponding dynamic focus entry in ROM 94;
a shading entry in ROM 95; and a convergence entry in ROM
96 The contents of ROMs 90. 96 may be theoretically
determined on mathematical bases or empirically determined
10 as later described. In general, astigmatism relates to
maintaining roundness of the dots on screen 30 and
shading relates to brightness corrections to the video
amplifier circuits 98, loo, 102 which are coupled to guns
24, 26, 28 respectively, which brightness corrections
5 are typically required near the screen 30 edges due to
CRT electronic lens limitations.
The eight bit parallel outputs of each of ROMs
90-96 are coupled by eight parallel lines to eight bit
latches 100-106 respectively. Each of latches 100-106
20 receives a 10 MHz clock signal from generator 80 and
provides a temporary memory storage of the most recent
ROM output between clock signals to prevent transients from
converters 72, 82 and ROMs 90-96 from distorting the ROM
outputs.
Latches 100, 101 have an eight bit output on
eight parallel lines to MDACs 112, 113 respectively. Delay
lines 116, 118 are coupled to output terminals 74, 70
respectively and provide a predetermined delay to the x, y
analog deflection signals respectively to exactly compensate
30 fo~ the processing time of the signals in ~onverters 72, 82,
ROMs go-gS and latches 100, 101. The inputs of buffers
120, 122 are coupled to the output terminals of delay
lines 116, 118 respectively, and buffer 120, 122 output
terminals are coupled to terminals 128, 129 of MDACs 112,
113 respectively. Offset potentiometers 124, 126, each
returned to ground 57, are coupled to buffers 120, 122
respectively and provide for a one time correction for any
)'3~)
PIIA 40508 8 20.12.1987
I,eam position offset on screen 30 due to DC (direct
current) system errors. The output terminals of buffers
120, 122 are coupled to MDACs 112, 113 respectively to
provide a sliding reference instead of a fixed reference
in order to lessen the abruptness of the steps that are
typical in a digital to analog converter. Without the
smoothing compensation thus provided, the steps would
be noticeable in any continuous line figure such as a
circle.
The outputs of MDACs 112, 113 are supplied to
buffers 130, 132, respectively, each of which has an
amplitude or gain potentiometer 134 returned to ground 57
for a one time adjustment of the signal amplitude at the
buffer output terminal and an offset potentiometer 138, also
returned to ground 57, to provide for a one time
correction for any beam position offset on screen 30 due
to DC system errors. In the following description
buffers, coil drivers and power amplifiers are provided
with gain and offset potentiometers for one time adjust-
ment corrections of signal gain and beam position cente-
ring respectively. Each gain potentiometer is labeled
134 and each offset potentiometer is labeled 138, both
potentiometers being returned to ground 57. The outputs of
buffers 130, 132 are supplied to input terminals 142, 144,
respectively, of analog delay line and filters 146, 148
respectively which act to further smooth the analog
corrections of the x, y deflection signals.
Referring to Figs. 2-5, filter 146, shown in
dashed box outline, will be described, it being under-
stood that filter 148 is identical. Resistor 155 is coupledbetween terminal 142 and input port 159 of delay line
156 which in this example is a 100 nsec delay line having
in succession 25 nsec delay port 160, 50 nsec delay port
161, 75 nsec delay port 162, and 100 nsec delay port
163. Delay line 156 is returned to ground 57. Resistors
166 - 170 couple ports 159_163 respectively to inverting
(-) input 174 of operational amplifier 176, noninverting (+)
P}-IA 40508 9 20.12.1987
~nput 178 being returned to ground 57. Capacitor 180
and resistor 182 are coupled in parallel in conventional
manuler between output terminal 184 and inverting terminal
174 of amplifier 176. Resistor 186 is coupled betwe~
5 ~utput port 163 and ground 57 and properly terminates the
delay line. In this example resistor 155 is 6 kohms,
resistors 166-170 are each 4.7 kohms and resistor 186
is 100 ohms. Thus, the signal at each successive port
160-163 is delayed 25 nsec more than the signal at the next
10 previous port for a given signal at input port 159.
Referring to the wave forms of Figs. 3-5, the
operatiDn of filter 146 will be described. For explanatory
purposes, wave form 190, Fig. 3, at terminal 142 is a square
wave. After being processed by delay line 156, square wave
15 190 is transformed to stepped waveform 192, Fig. 4. Each
step in waveform 192 is 25 nsec in duration, each
~rtical side of waveform 190 being converted into four
steps 160a-163a since there are four delay ports 160-163
in line 156. By increasing the value of capacitor 180
20 steps 160a-163a are rounded and smoothed to obtain
waveform 194, Fig. 5. Since the waveform from buffers 130,
132 have already been substantially smoothed, filters 146,
148 provide substantially completely smoothed x, y
correction signal outputs, respectively, to summers 196,
25 198.
Referring to Figs. 1A, 1B, delay lines 200, 202
are coupled in analog x, y deflection lines respectively
to exactly compensate for the delays occasioned by
signal processing in MDACs 112, 113, buffers 130,132
30 and filters 146, 148. Delay line 200 is coupled between
junction 123 and x size potentiometer 204 in the x
deflection line. Delay line 202 is coupled between
junction 121 and y size potentiometer 206 in the y
deflection line. One time adjustments are made to potentio-
35 meters 204, 206 to fine tune the size of the x, y deflec-
tion signals, respectively, to match them to the dimen-
sions of display 30.
PTiA 40503 10 zo,12.1987
The x, y deflection lines are coupled to summers
196l 198, respectively, where they are summed with x, y
deflection correction signals from filters 146, 148,
respectively. Summers 195, 198 are coupled to power
5 huffer5 208, 210 respectively, which ha7e a gain of one,
and each of which has centering potentiometer 139
returned to ground 57 for centering the x, y signals on
display 30. The corrected deflection signal outputs of
buffers 208, 210 are supplied respectively to deflection
power amplifiers 209, 211 and thence to the windings in
deflection coil 32.
The astigmatism, dynamic focus, shading and
convergence functions are not as sensitive tothe stepped
analog outputs as is the deflection function and therefore
DACs with fixed reference potentials instead of MDACs
having a sliding reference potential may be used and
analog delay line filters are not required.
ROMs 92-96 each have eight bit word digital
outputs on eight parallel lines which are coupled to latches
20 102-106, respectively, which have eight bit word digital
outputs supplied on eight parallel lines to DACs 216-220,
respectively, where they are converted to analog
waveform signals. Reference voltage generator 222 supplies
a reference voltage, in this example 5.00 volts, at
~rminal 224 which is coupled to reference voltage terminal
22~i ' oi` DACs 216-220. The analog output terminals of
DACs 216-219 are coupled to buffers 226-229, respectively,
each of which has an amplitude potentiometer 134 and an
offset potentiometer 138 returned to gro-lnd 57.
Color video signals are applied to terminals
268, 270, 272. Fig. 1B, which are coupled to delay lines
274, 276, 278, respectively, to compensate for the delays
occasioned by signal processing elsewhere in the circuit.
The output terminals of delay lines 274, 276, 278 are
coupled to summers 280, 282, 284 respectively which in
turn are coupled to amplifiers 98, 100, 102 respectively.
4~
PIIA 40508 11 20.12.1987
The output from ROM 95 and hence of buf~er 229
is applied to summers Z80~ 282, 284 for summing with the
color video signals to control video amplifiers 98,
100, 102 so as to change video level, and hence brightness.
The control function may be by simple addition to the
video signals or by a product circuit for multiplying by
the video signals to achieve the desired shading as is
known in the art.
In powerful projection CRTs with high brightness
it has been found that the CRT must be refocussed not only
to account for the position of t~e ~eam on the screen ~ut
to account for the instantaneous beam current as well.
Digital signals designating writing rate (in a stroke
written CRT), which is supplied by the system supplying
the deflection to the video signals, and operator brightness
setting are each of five bit words supplied on five
parallel lines by circuit 238 to ROM 240, which in this
example also has 4096 data storage locations. The five
bit brightness setting digital signal is supplied on five
parallel lines 242 and the five bit writing rate digital
signal is furnished on five parallel lines 244 to ROM 240.
ROM 240 effectively takes the product of the brightness
setting signa~ and the writing rate signal and applies a
further cur~ture for each product that is stored in ROM
240 to correct for the focus v. beam current characteristic
of the CRT system.
Also supplied by circuit 238 are operator entered
two bit digital word flag signals on two parallel lines
246. These flags are for special purpose displays such as
weather system displays where it is desired to defocus and
blur parallel lines to depict a certain weather condition.
The digital focus correction signals from ROM
240 are eight bit digital signals supplied on eight
parallel lines to latch 107. Strobe circuit 248 provides a
strobe signal to latch 107 so that ROM 240 has time to be
addressed and supply the stored correction signals to
latch 107 without transient signal interference. The eight
PHA 40508 12 20.12.1987
bit digital output of latch 107 is supplied on eight
parallel lines to DAC 250 which is supplied at terminal 224'
with a reference voltage from generator 222. DAC 250
supplies an analog signal to buffer 252 which has amplitude
potentiometer 134 returned to ground 57 for a one time
adjustment of the amplitude of buf`fer 252 output and offset
potentiometer 138 returned to ground 57 to provide for a
one time correctinn for any beam position offset on
screen 30 due to DC system errors. The output terminals of
buffers 252 and 228 are coupled to summer 258.
Buffers 226, 227 and summer 258 output terminals
are coupled to coil drivers 260, 261, 262 respectively,
each having a gain of one and each of which has gain
potentiometerl34 and offset potentiometer 138, '~oth
potentiometers returned to ground 57. The output terminals
of coil drivers 260, 261, are coupled to coil 36, and coil
driver 262 is coupled to coil 40 to provide correct analog
signals to the coils. Static focus current circuit 263 pro-
vides an operator adjusted static focus current to coil 40.
The three output terminals of convergence DAC
220 are coupled to coil drivers 230a, 230b, 230c respec-
tively which in turn have their output terminals
coupled to convergence coil assembly 44 for controlling
the convergence of the beams of electron guns 24, 26, 28
respectively.
Referring to Fig. 6, decode logic circuit 300
has input terminals A', B' each of which has two parallel
lines and which are coupled to terminals A, B respectively,
Fig. lA. Lines 78 are coupled to lines 78' and lines 88
are cou~led to lines 88'. Indicator LED's 302-306 are
coupled to circuit 300 and indicate respectively the "up",
"down", "right", "left" and "offscreen" conditions of the
beam on screen 30. Circuit 300 is known to the art and
comprises less than a dozen simple gates that determine
whether the A/D converters have "overflowed", i.e. all "1's"
or "underflowed", i.e. all "O's." Indicator LED's 302-306
provide an indication of each possible condition.
PHA 40508 13 20.12,1987
If sq-uare waves of peak to peak amplitude to
cause maximum desired deflection are impressed on the x and
y inputs, the scaling and centering adjustments on the input
buffers and coil drivers may be adjusted to just barely
extinghuish the "up", "down", "right", and "left" LED~s.
By this means the A/D converters are made to operate over
their full range. These are set up adjustments that do not
need to be reset, If any of the LED's are lighted, the in-
p-ut signal is too largefor offscreen. Besides driving an
10 LED, circuit 300 is coupled to off screen display inhibitor
circuit 310 which is coupled into the preceding circuits
in a manner known to the art in order to inhibit useless
efforts to display data that are outside the viewing screen
area and to protect the deflection amplifiers from being
overdriven. An A/D converter having incorporated therein
a decode logic circuit of the type disclosed herein is
available from Telmos Inc., 740 Kifer Road, Sunnyvale,
California 94086 and having model no. 1070.
Circuits designed with the teaching of this
invention are not hampered or limited by components which
may limit the speed of operation. ECL (emitter coupled
logic) digital devices or multiple digital channels opera-
ting on staggered times can be used to significantly raise
the speed of operation. Very high frequency A/D converters,
DACs and operational amplifiers all of which are commer-
cially available and may be used to greatly increase
the speed of operation and still maintain the accuracy and
other advantages of the slower design. Also, the disclosed
embodiment may be modified by adding or subtracting sec-
tions and channels, depending on the kind and number of
functions desired.
The contents of ROMs 90-96, 240 may be derived
from theoretical considerations or from an empirical
approach of curve fitting of measured data. The latter
approach accounts for all aberrations such as those due to
lens, yoke, CRT, off-axis, and flat face imperfections and
thus in general is more comprehensive than the theoretical
approach. One method of empirical approach comprises
P~ 4050~ 14 20.12.1987
generating a pattern of crosshatches, dots or small
symbols on a regular grid through the system and comparing
the resultan-t display with a geometrically accurate overlay
that is fastened over the viewing screen. All ROMs are
relnoved from the circuit and manual rotary switches
substituted, All of the switches may be set at "half-way"
position as a place to start, although it may later develop
that a position closer to one end is better. Static
adjustments are made to optimize performance at screen
center, these involving focus coil position, static
centering adjustments, and the like. The display will, over
the rest of the screen, be out of shape and somewhat out of
focus. If the process is started at the upper left
corner of the screen, the switches may be adjusted to get
lS exactly the position, focus~ astigmatic correction and
brightness desired at each of numerous points on the screen,
the appearance of the rest of the screen being ignored
during the adjustments for a particular point. The settings
for each point are recorded as well as the digital
output of the A/D converters for that point. Thus, the
displayed pattern on the screen is made to exactly match
at all points the accurate overlay, optimizing each func-
tion at each point. In this way, any interactions are also
accounted for.
After a number of points, e.g. 50 or 100, have
been compared the res~lts may be tabulated and curves
fitted through the points using a computer program or other
means. Interpolations may be made to determine the complete
ROM contents since it is impractical to manually determine
each of the many, e.g. 4096, points where corrections
are desired. When these results are placed in the ROMs, the
circuit will automatically provide corrections for all
points on the screen that hav~ corresponding x, y
signal set addresses in the ROMs, and not just for the
relatively few points for which manual corrections were
made.
~ J~
Pl-lA 40508 15 20.12.1987
In the analysis of the data obtained as above
described, it may develop that the full sweep of the
RO~s and DACs in one or more channels is not being
fully used due to an incorrect starting point. The data may
be proportionally expanded to more fully utilize the
range of the digital circuits and the amplitude and
offset analog adjustments used to correct the display
itself Of course, if tha starting points are correctly
chosen, such rescaling is unnecessary.
While there have been described above the prin-
ciples of this invention in connection with speci~ic
embodiments, it is to be understood that this is by way
of example and is not limiting of the scope of this
invention.
