Note: Descriptions are shown in the official language in which they were submitted.
1~7188
VLSI DEVICES HAVING INTERCONNECT STRUCTURE
FORMED ON LAYER OF S~;ED MATERI~l:,
Fiead of the Invention
This invention relates to methods for making
interconnect structures for Very Large Scale Integration
(VLSI) devices and to interconnect structures made by those
methods.
Backaround of the Invention
Individual semiconductor devices in VLSI integrated
circuits are interconnected by means of one or more patterned
conductive layers overlying the semiconductor devices. It is
particularly advantageous to provide a plurality of patterned
conductive layers separated from one another and from the
underlying semiconductor devices by layers of insulating
material. Th~s practice permits a higher density of
interconnections per unit area than can be provided by a
single patterned conductive layer, and simplifies design by
permitting interconnection paths implemented in one
conductive layer to cross over interconnection paths
implemented in ot~er conductive layers.
Multilevel interconnection structures are
conventionally made by alternately depositing and patterning
layers of condùctive material, typically aluminum alloys such
as Al-Si, and layers of insulating material, typically sio2.
The patterning of underlying layers defines a nonplanar
topography which complicates reliable formation of overlying
layers. In particular, the non-planar topography of
underlying conductive layers is replicated in overlying
insulating layers to provide vertical steps in the insulating
layers. Moreover, small holes are formed in the insulating
layers to permit interconnection to underlying conductive
layers or device contacts.
The subsequent formation of conductive layers
overlying the nonplanar tcpography of the insulating layers
is complicated by thinning of the conductive layers at the
tops of the steps, cusping or microcracking of the conductive
layers at the bottoms of the steps, and formation of voids in
f'~,
~2871~38
the conductive layers in small via and contact holes, all of
which can lead to high resistance interconnections or
undesired open circuits. Moreover, uneven formation of the
conductive layers reduces the resistance of the patterned
conductive material to electromigration, reducing the
reliability of the completed integrated circuit.
Patterning of the resulting conductive layers may
also be complicated by the nonplanar topography. For
example, conductive material at the bottom of steps is
difficult to remove and may provide unwanted conductive paths
between adjacent regions of a conductive layer.
The formation of further insulating layers is also
complicated by the nonplanar topography of the conductive
layers. Weaknesses are present in the insulating layers at
the tops and botttoms of steps. Cracks form at such
weaknesses, providing unwanted conductive paths between
adjacent conductive layers. Narrow troughs between steps in
the conductive layers are difficult to fill with commonly
used insulating materials, such as SiO2 without the formation
of voids.
The Resist Etch Back (REB) technique is frequently
used to modify the nonplanar topography of insulating layers
in an effort to minimize or avoid the above problems. In the
REB technique, a thick layer of photoresist is formed on a
nonplanar insulating layer and the photoresist is etched back
until peaks or steps in the insulating layer topography are
exposed, but valleys or troughs in the insulating layer
topography are filled with remaining photoresist. The
etching process is then c.ontrolled so that the etch rate of
the insulating layer is substantially equal to the etch rate
of the photoresist. Peaks or steps in the insulating layer
topography are etched while valleys or troughs are protected
by the photoresist so the height of the peaks or steps is
reduced. After the etching is complete, remaining
photoresist is removed and additional insulating material is
deposited if required to build the insulating layer up to a
desired thickness. The next conductive layer is then
: . . .
- . . , - : .,
-~
.
'-
~21371l~3
deposited on the insulating layer, which is now relativelysmooth, and the conductive layer is patterned.
In related etch back planarization techniques, the
photoresist may be replaced by other materials, such as Spin
On Glass (SOG).
While etch back techniques reduce the height of
peaks or steps in the insulating layer topography, they do
not necessarily eliminate the sharp edges or vertical
sidewalls of steps. These sharp edges and vertical sidewalls
cause many of the problems referred to above, and such
problems persist when conventional etch back techniques are
used.
Etch back techniques are also subject to
macroloading a~d microloading effects which can have a
considerable impact on the results obtained in a production
environment. The macroloading effect is a run to run or
wafer to wafer variation of the relative etch rates of the
insulating material and photoresist. Because the etch rates
must be substantially equal to obtain an optimum reduction in
step height, such variations cause a reduction in step height
which is less than optimum. In severe cases, macroloading
effects may actually accentuate deviations from a planar
topography.
The microloading effect is enhanced localized
etching of the photoresist in narrow valleys or troughs and
at the edges of steps in the insulating layer. Microloading
is primarily due to oxygen species liberated during etching
of the insulating layer defining the side walls of the
valleys, troughs or steps. The enhanced localized etching
causes formation of sharp notches or trenches which in turn
cause the problems referred to above.
The performance of etch back techniques can be
improved somewhat by combining them with low pressure ion
milling techniques, as described in U.S. Patent No.
4,954,274 and corresponding Canadian Application Serial No.
567,935, both filed May 27, 1988, in the name of Thomas
Abraham. However, even this improved technique seeks
-
,.
-
.
12tj7188
to planarize a nonplanar topography instead of avoiding the
formation of the nonplanar topography in the first place.
Some research facilities are studying the use of
polyimide insulating layers in place of the more conventional
sio2 insulating layers. Unlike sio2 insulating layers,
polyamide insulating layers need not conform to the
underlying topography and can therefore be deposited with
substantially planar upper surfaces. Consequently most of
the problems discussed above can be avoided without the use
of etch back techniques by providing substantially planar
insulating layers. Unfortunately, much more work is required
to prove that polyimides can be used reliably in commercial
device fabrication. As an insulator, SiO2 is still the
preferred dielectric because of its proven compatibility with
silicon devices and the accumulated experience with its use
in commercial device fabrication.
Broadbent et al have recently proposed a Filled
Interconnect Groove (FIG) technique for forming multilevel
interconnect structures tIEEE Transactions on Electron
Devices, Vol. 35, No. 7, pp. 952-956, July 1988). In the
technique proposed by Broadbent et al, a substantially planar
insulating layer of phosphosilicate glass is deposited by
Chemical Vapour Depositon (CVD) over devices formed in a
silicon substrate. The glass insulating layer is patterned
to form grooves which extend through the glass insulating
layer where interconnect metallization is desired. An
adhesion bilayer consisting of 20 nm of tungsten and 20 nm of
titanium is deposited by DC magnetron sputtering over the
glass insulating layer and in the grooves. Tungsten is then
deposited on the adhesion bilayer by CVD to form a tungsten
blanket which covers the entire upper surface of the adhesion
bilayer and fills the grooves. The tungsten blanket is then
etched back to expose the glass insulating layer between the
grooves, thereby providing a substantially planar
interconnect structure.
Unfortunately, loading effects encountered during
the etch back step reduce the effectiveness of the technique
proposed by Broadbent et al. In particular, the local etch
12~7~8
rate of the tungsten blanket is found to be dependent on the
ratio between the surface area covered by tungsten and the
surface area of exposed glass. Consequently tungsten is
removed faster from portions of the structure where a
relatively large surface area of glass is exposed than from
portions of the structure where little or no glass is
exposed. Thus, any nonuniformity in the deposition of the
tungsten blanket which results in nonuniform thickness of the
tungsten blanket can result in total removal of tungsten from
lo grooves on one part of the structure before the glass between
grooves is exposed on another part of the structure. This
results in undesired open circuits and short circuits in the
interconnect structure. Noreover, nonuniformity of the
tungsten etch rate prevents matching of the tungsten etch
rate to the glass etch rate across the entire surface of the
structure as would be required for ideal planarity of the
resulting ~tructure.
Summary of the Invention
This invention seeks to obviate or mitigate the
problems discussed above by providing improved FIG methods
for making interconnect structures and interconnect
structures made by those methods.
Accordingly, one aspect of this invention provides
a method ~or making interconnect structures for semiconductor
devices which are covered with a first substantially planar
dielectric insulating layer. The first insulating layer has
contact holes which extend through the insulating layer over
contact regions of the devices. The contact holes are filled
with conductive material. The method comprises:
forming a layer of seed material on the first
substantially planar dielectric layer at predetermined
locations where interconnect conductor is desired;
forming a second substantially planar dielectric
insulating layer over the first substantially planar
dielectric insulating layer, the second layer having openings
extending therethrough at the predetermined locations to
expose at least a portion of the seed material; and
.
.
. . .
lZ~7188
selectively depositing conductive material on the
exposed seed material to fill the openings.
The step of forming a layer of seed material may
comprise depositing a layer of seed material over the entire
surface of the first dielectric layer, and patterning the
layer of seed material to leave seed material only at the
predetermined desired locations. In this case, the seed
material may be a material in the group consisting of
aluminum alloys, refractory metals and metal silicides.
The step of forming the second substantially planar
dielectric insulating layer may comprise depositing a
substantially planar layer of sio2 over the first dielectric
insulating layer, depositing a layer of photoresist over the
sio2 layer, patterning the layer of photoresist to expose the
sio2 layer at the predetermined locations, etching the SiO2
layer through the patterned photoresist to form openings
through the sio2 layer at the predetermined locations, and
removing the patterned photoresist. In this case, the seed
material may act as an etch stop to inhibit etching of the
conductive material filling the contact holes during etching
of the sio2 layer.
The step of selectively depositing conductive
material to fill the openings may comprise selectively
depositing tungsten on the seed material by selective CVD.
In this case, a layer of metal silicide may be formed on side
walls of the openings extending through the second dielectric
layer before selectively depositing the tungsten and the
tungsten may be selectively deposited on the metal silicide
and on the exposed seed material to fill the openings. This
improves the rate of tungsten deposition, and improves the
adherence of the tungsten to the side walls of the openings.
Alternatively, the step of selectively depositing
conductive material to fill the openings may comprise
selectively depositing a metal which is a member of the group
consisting of nickel, copper, gold and palladium on the seed
material by selective electroless plating.
Where the first dielectric layer is a layer of
sio2, the step of forming a layer of seed material may
. , .: , -. ,
'
lZ87~
comprise selectively implanting silicon ions into the first
dielectric layer at the predetermined locations, and the step
of selectively depositing conductive material on the exposed
seed material to fill the openings may comprise depositing
tungsten by selective CVD.
The steps of the method may be repeated to form a
multilevel interconnect structure.
The methods according to the invention replace the
tungsten blanket deposition and etch back steps in the method
of Broadbent et al with a selective deposition of conductive
material only in the openings where interconnect conductor is
desired. Consequently the methods according to the invention
avoid problems associated with nonuniform etching of the
tungsten blanket as described above in the discussion of the
method of Broadbent et al. In particular, the methods
according to the invention avoid removal of conductive
material from openings on one part of the structure before
dielectric insulating material between grooves is exposed on
another part of the structure. Undesired short circuits and
open circuits are thereby avoided. Moreover, there is no
need to establish a uniform conductive material etch rate
matched to the insulating material etch rate across the
entire surface of the structure to achieve good planarity of
the resulting structure as in the method of Broadbent et al.
Another aspect of this invention provides an
interconnect structure for semiconductor devices which are
covered with a first substantially planar dielectric
insulating layer. The insulating layer has contact holes
extending therethrough over contacts of the devices, and the
contact holes are filled with conductive material. The
interconnect structure comprises:
a layer of seed material on the first
substantially planar dielectric layer at predetermined
locations;
a second substantially planar dielectric insulating
layer over the first substantially planar dielectric
insulating layer, the second layer having openings extending
therethrough at the predetermined locations; and
~2~7188
conductive material filling the openings and
contacting the seed material.
Brief Description of the Drawings
Embodiments of the invention will now be described
by way of example only with reference to the accompanying
drawings, in which:
Figures la - le are cross-sectional views of an
interconnect structure at successive stages of its
manufacture according to a FIG method taught by Broadbent et
al;
Figures 2a - 2e are cross-sectional views of an
interconnect structure at successive stages of its
manufacture according to a method according to a first
embodiment:
Figures 3a - 3d are cross-sectional views of an
interconnect structure at successive stages of its
manufacture according to a method acccrding to a second
embodiment: and
Figures 4a - 4d are cross-sectional views of an
interconnect structure at successive stages of its
manufacture according to a method according to a third
embodiment.
Description of Embodiments
Figure la shows a portion of a silicon gate CMOS
integrated circuit made using conventional silicon gate CMOS
fabrication techniques. In particular, p-type doped wells 10
are formed at desired locations in an n-type silicon
substrate 12, and a field oxide 14 is grown at other selected
locations on the substrate 12. Gate oxide 16 is grown
through openings in the field oxide 14, and n-doped
polysilicon gates 18 are formed on the gate oxide 16. The
polysilicon gates 18 and field oxide 14 are used to perform
self-aligned source and drain diffusions 20, 22. N-type
dopants are used to form the source and drain diffusions 20
in the p-type wells 10, and p-type dopants are used to form
the source and drain diffusions 22 outside of the p-type
- : .
:
'
12~
wells 10. A sidewall oxide 24 is formed on the polysilicon
gates 18, and a dielectric insulating layer in the form of
further oxide layer 26 is deposited over the CMOS devices and
planarized using REB techniques. Contact holes 28 are formed
through the oxide layer 26 to expose contact regions 30 of
the CMOS devices by conventional masking and etching steps
(i.e. by depositing a layer of photoresist over the oxide
layer 26, patterning the layer of photoresist to expose the
oxide layer 2~ at predetermined locations where contact holes
are desired, etching the oxide layer 26 through the patterned
photoresist to form contact holes exposing the contact
regions 30 of the devices, and removing the patterned
photoresist). Al-Si alloy 32 is deposited and patterned to
fill the contact~holes 28 and define contacts for the CMOS
devices.
In the Filled In Groove (FIG) method for making
interconnect structures as proposed by Broadbent et al (IEEE
Transactions on Electron Devices, Vol. 35, No. 7, pp. 952-
956, July 1988), a layer of PhosphoSilicate Glass (PSG) loo
is deposited by Chemical Vapour Deposition (CVD) over the
oxide layer 26 and patterned using conventional masking and
plasma etching steps to form grooves 102 extending through
the PSG layer 100 where interconnect conductor is desired.
The PSG layer 100 and grooves 102 are shown in Figure lb. A
tungsten-titanium adhesion bilayer 104 is deposited over the
PSG layer 100 and in the grooves 102 by DC magnetron
sputtering as shown in Figure lc, followed by Chemical
Vapour Deposition (CVD) of a tungsten blanket 106 as shown in
Figure ld. The tungsten blanket 106 is etched back in a
plasma etcher using NF3/O2 chemistry to leave tungsten
interconnect metal 108 only in the grooves 102 as shown in
Figure le.
As illustrated, this technique provides a
substantially planar interconnect structure which can be
built up to form a multilevel interconnect structure by
repetition of the steps described above. Unfortunately,
loading effects encountered during the etch back step reduce
the effectiveness of this technique~ In particular, the
, "
~2~37~8~
local etch rate of the tungsten blanket 106 is found to be
dependent on the ratio between the surface area covered by
tungsten 106 and the surface area of exposed PSG 100.
Consequently tungsten 106 is removed faster from portions of
the structure where a relatively large surface area of PSG
100 is exposed than from portions of the structure where
little or no PSG 100 is exposed. Thus, any nonuniformity in
the deposition of the tungsten blanket 106 which results in
nonuniform thickness of the tungsten blanket 106 can result
in total removal of tungsten 106 from grooves 102 on one part
of the structure before the PSG 100 between grooves 102 is
exposed on another part of the structure. This results in
undesired open circuits and short circuits in the
interconnect st~ucture. Moreover, nonuniformity of the
tungsten etch rate prevents matching of the tungsten etch
rate to the PSG etch rate across the entire surface of the
structure as would be required for ideal planarity of the
resulting structure.
An improved Fill In Groove (FIG) method for making
an interconnect structure according to a first embodiment is
applicable to the CMOS integrated circuit structure shown in
Figure la, but will be described as applied to an improved
CMOS integrated circuit structure as shown in Figure 2a. The
CMOS structure of Figure 2a differs from the CMOS structure
of Figure la in that titanium silicide contacts 40 are formed
at the gate, source and drain contact regions by depositing
titanium on the upper surface of the structure, heating the
structure to cause silicidation of the titanium at the gate,
source and drain contacts where it comes into contact with
polysilicon or silicon, and selectively etching unreacted
titanium from the field and sidewall oxides 14, 24 before
depositing oxide layer 26 and forming contact holes 28. The
side walls 42 of the contact holes 28 are coated with
tungsten silicide 44 by Chemical Vapour Deposition (CVD) of a
conformal layer of tungsten silicide on the bottoms 30 of the
contact holes 28, the side walls 42 of the contact holes 28
and an upper surface of the oxide layer 26, and preferential
removal of the tungsten silicide from the oxide layer 26 by
12~71~3
11
anisotropic reactive ion etching. Conductive material in the
form of tungsten 46 is then selectively deposited on the
bottoms 30 and side walls 42 of the contact holes 28 to fill
the contact holes 28. The resulting contact structure is
more reliable than the conventional Al-Si contact structure
shown in Figure la, and its fabrication is discussed in
greater detail in co-pending US Application Serial Number
207,568 filed June 16, 1988 and Canadian Application Serial
Number 569,516 filed June 15, 1988, both in the name of Vu
Quoc Ho. Apart from the different contact structure, the
CMOS structure shown in Figure 2a is identical to the
conventional CMOS structure shown in Figure la.
In the FIG method according to a first embodiment,
a layer 200 of t~ngsten silicide approximately 500 angstroms
thick is deposited over the entire surface of the oxide layer
by CVD. The tungsten silicide layer 200 is patterned using
conventional photoresist masking and etching techniques to
leave tungsten silicide only at predetermined locations where
interconnect conductor is desired, as shown in Figure 2b.
A substantially planar dielectric insulating layer
in the form of a SiO2 layer 202 is formed over the oxide
layer 26, and the oxide layer 202 is patterned using
conventional photoresist masking and etching techniques to
define openings 204 extending through the oxide layer 202 at
the predetermined locations to expose at least a portion of
the tungsten silicide layer 200. During etching of the oxide
layer 202, the tungsten silicide layer 200 acts as an etch
stop layer to prevent removal of underlying oxide 26 or
tungsten ccntacts 46. The resulting structure is shown in
Figure 2c.
Side walls 206 of the openings 204 are coated with
tungsten silicide 208 by Chemical Vapour Deposition (CVD) of
a conformal layer of tungsten silicide on the exposed
tungsten silicide layer 200, the side walls 206 of the
openings 204 and an upper surface of the oxide layer 202, and
preferential removal of the tungsten silicide from the oxide
layer 202 by anisotropic reactive ion etching. Tungsten
~;~87~
12
silicide is also removed from the layer 200 at the bottoms of
the openings 20~ during the anisotropic etching step, but the
thickness of the layer 200 is such that the oxide layer 202
is exposed before all of the layer 200 has been removed.
Consequently, some of the tungsten silicide layer 200 remains
at the bottoms of the openings 204 when the etching step is
complete. The resulting structure is shown in Figure 2d.
Conductive material in the form of tungsten 210 is
then selectively deposited on the tungsten silicide 200, 208
lining the openings 204 by selective CVD to fill the openings
204 and produce a substantially planar interconnect structure
as shown in Figure 2e. The tungsten silicide layers 200, 208
act as 'seed layers' during the selective deposition. The
tungsten 210 is deposited only on the exposed tungsten
silicide 200, 208 and not on exposed surfaces of the oxide
layer 202.
The steps of the method according to the first
embodiment may be repeated to build up a multilevel
interconnect structure.
The seed material used in the improved FIG method
described above may be any material in the group consisting
of aluminum alloys, refractory metals and metal silicides,
and the conductive material used to fill the openings may be
any conductive material which can be selectively deposited on
such seed material.
For example, in a method according to a second
embodiment shown in Figures 3a - 3d, the steps shown in
Figures 3a - 3c are identical to the steps shown in Figures
2a - 2c except that the tungsten silicide seed layer 200 is
replaced by an Al-Si seed layer 300. The steps shown in
Figures 2d - 2e are replaced by selective electroless
deposition of nickel on the Al-Si seed layer 300 exposed at
the bottoms of the openings 204 in the sio2 layer 202 to fill
the openings 204, as shown in Figure 3d.
Such a selective electroless deposition process is
described by Pai et al in the Proceedings of the IEEE V-MIC
Conference, pp. 331-337, June 13-14, 1988. The surface of
the Al-Si seed layer 300 is etched in dilute HF to remove
12~'7188
13
native oxide and create surface roughness which improves
adhesion of the plated nickel. A solution of PdCl2 in HCl
and acetic acid is brought into contact with the etched Al-Si
surface to deposit Pd particles on the surface of the Al-Si
5 seed layer 300. The Pd particles act as a catalyst for the
nickel plating reaction which follows. A solution of nickel
ions in sodium hypophosphite having a pH value between 8 and
9 is then brought into contact with the Al-Si seed layer 300
and held at 70 degrees Celsius. Current is passed through
10 the solution to plate nickel 302 onto the Al-Si seed layer
300 until the openings 204 are filled. The plated nickel 302
is annealed at 400 degrees Celsius in N2 and alloyed at 450
degrees Celsius in N2. Other metals such as copper, gold or
palladium can be~ used in place of nickel in electroless
15 plating processes.
In another embodiment shown in Figures 4a - 4d, the
sio2 layer 26 shown in Figure 4a is coated with a 3000
angstrom thick molybdenum film 400 deposited by DC magnetron
sputtering. The molybdenum film 400 is patterned using
20 conventional photoresist masking and reactive ion etching
methods to define openings 402 through the molybdenum film
400 at predetermined locations where interconnect metal is
desired, as shown in Figure 4b. Silicon ions 404 are
implanted at 25 keV through the openings into the SiO2 layer
25 26. The molybdenum film 400 acts as a masking layer during
the implantation process, absorbing the silicon ions at
locations other than those predetermined locations where
interconnect metal is desired.
The molybdenum film 400 is removed in a 1:1
30 H~SO4/H2O2 solution and the SiO2 surface is etched in a 1% HF
solution to bring the implanted silicon closer to the exposed
surface. A further SiO2 layer 406 is then deposited on the
sio2 layer 26 and patterned using conventional photoresist
masXing and etching methods to define openings 408 at the
35 predetermined locations where interconnect metal is desired.
The resulting structure is shown in Figure 4c.
Tungsten 410 is deposited in the openings 408 by
selective CVD to substantially fill the openings 408 as shown
. ~' .
7:188
14
in Figure 4d. The implanted SiO2 which is exposed by the
openings 408 acts as a seed material for the selective
deposition of the tungsten 410.
Further details of selective CVD of tungsten on
silicon implanted sio2 are provided by Hennessy et al in the
Journal of the Electrochemical Society, Solid State Science
and Technology, pp. 1730-1734, July 1988.
In each of the three embodiments described above,
the tungsten blanket deposition and etch back steps of the
method of Broadbent et al are replaced with a selective
deposition of conductive material only in the openings where
interconnect conductor is desired. Consequently the methods
according to the embodiments avoid problems associated with
nonuniform etching of the tungsten blanket as described above
in the discussion of the method of Broadbent et al. In
particular, the methods according to the embodiments avoid
removal of conductive material from openings on one part of
the structure before dielectric insulating material between
grooves is exposed on another part of the structure.
Undesired short circuits and open circuits are thereby
avoided. ~oreover, there is no need to establish a uniform
conductive material etch rate matched to the insulating
material etch rate across the entire surface of the structure
to achieve good planarity of the resulting structure as in
the method of Broadbent et al.
