Note: Descriptions are shown in the official language in which they were submitted.
12~3~63~
B~CKGRQUMD QF ~ INVFINTIQN
1. Field of the invention
The present invention relates to the field of MOS
integrated amplifiers and more specifically to input buffers
utilizing differential amplifiers.
2. Prior Art
Various input buffer amplifiers for bufferin~ an
input signal prior to coupling that signal to other circuitry
are well known in the prior art. Some of these input buffer
amplifiers are also termed as a level shi~ter, wherein input
voltage levels are shifted to be compatible with voltage
levels of the associated circuitry. For example, many input
voltage le~els are specified as being compatible with
standard transistor-transistor-logic ~TTL) logic levels, that
is, a logic threshold of 1.4 volts with a margin of 0.6 volts
.
about the threshold. A typical high lo~ic le~el TTL signal
can be as low as 2.0 volts (VIH parameter), while a low logic
level TTL signal can be as high as 0.8 volts (VIL parameter).
However, when this TTL level signal is ~o be used in
conjunction with complementary metal oxide semiconductor
~CMOS) circuitry, the lnput levels must be changed to be
compatible with the CMOS circuit. Typical CMOS logic
thresholds vary approximately from 2.0 to 3.0 volts, while
the margin around the threshold can be substantially equal to
the difference between the threshold and the supply rails.
An input buffer functions to translate the TTL compatible
levels of the inputs to the CMOS compatible levels for use
with CMOS circuitry inside a CMOS chip. This CMOS chip also
includes the input buffer on the chip.
In design~ng a built-in logic-threshold level translator
in a prior art input buffer, the buffers are built to be
sensitive to input levels which are above or below the
~; ' '
,.~
~L28963~L
typically-specified threshold margin of 0.6 volts. Prior art
implementations of input buffers are characterized by complex
connections of carefully sized devices for obtaining proper
performance. However, problems encountered in achieving
level translation in prior art input buffers result in high
dependence of the DC input parameters VIL and VIH on
variations in processing and temperat.ure. Further, the
complexity of most input buffer configurations results in
circuits which are genera}ly not of high speed. In order to
obtain the requisite speed, the circuits must be increased in
size, which generally is accompanied by an increase of power
dissipation.
~289~3~
The present invention provides for a CMOS input buffer
utilizing a switched-capacitor reference ~oltage generator
and a differential amplifier which functions as a comparator.
The present invention also describes a self-biased, high-gain
differential amplifier which is substantially immune to
process, temperature and supply voltage variations. The
reference voltage generator provides a reference voltage to
the signal comparator and this voltage is utilized as the
switching point for the comparator. An input voltage to the ~;
comparator is typically a TTL level signal and an output
voltage from the comparator provides a CMOS compatible signal
corresponding to the input signal. When the input voltage is
; 15 above the reference voltage level, the comparator generates a
first state of the CMOS output. When the input voltage is
below ~he reference voltage level, the comparator generates a
second state of the CMOS output. A plurality of comparators
are used to provide for a plurality of buffers, but only a
single reference voltage generator is coupled to the
plurality of comparators.
The reference voltage generator of the present invention
utilizes a sw~tched-capacitor voltage divider circuit to
provide the reference voltage. In the switched-capacitor
reference voltage generator, capacitors are charged and
discharged according to activation and deactivation of
~ various switches. These switches are controlled by clocking
; signals, which have their timing determined by a finite state
machine. The voltage division for generating the reference
voltage from a supply voltage is determined by a ratio of ~wo
capacitors, Cl and C2. The preferred embodiment utilizes a
series o~ n-type devices fsr one of the capacitors, and a
series o~ p-type devices ~or the other capacitor. ~y using a
~28963i
grouping of smaller "unit" capacitors for the n- and p-type
devices, the refexence voltage generator is made
substantially immune to process and temperature variations.
Although various prior art signal comparators can be
used to practice the present invention, the preferred
embodiment utilizes a self-biased, high~gain differential
amplifier. The self-biased, high-gain differential amplifier
is comprised of a pair of CMOS transistors for accepting the
reference voltage from the reference voltage generator and
operating in the active region to provide a self-biased
biasing voltage to a second pair of CMOS transistors. The
second pair of CMOS transistors provide a negative feedback
to the input pair. The self-biasing technique and the
negative feedback technique provided assure that the
amplifier is subs~antially immune to process and temperature
variations. A third pair o~ CMOS transistors is coupled to
accept an input voltage and generates an output to drive an
output pair of CMOS transistors. The output driving signal
will depend on the relation of the input voltage to the
biasing voltage, which is determined by the reference
; voltage.
The s~lf-biased, high-gain differential amplifier can be
used in other applications, such as a general-purpose
differential amplifier and front end for an operational
amplifier.
.
,~
~2~963~L
~RIEF ~!EscRlpTTc)N OF T~ G~ `
Figure 1 is a block diagram illustrating a reference voltage
generator and signal comparators of the present invention.
Figure 2 is a circuit schematic diagram of the reference
voltage generator of the present invention implemented in a
switched-capacitor voltage divider network.
Figure 3 is a waveform diagram shcwing various clocking
lS signals which are used to operate switches of the switched-
capacitor network of the reference voltage generator of the
present invention.
Figure 4 is a circuit schematic diagram of the switched-
capacitor network used in the reference voltage generator of
the preferred embodiment.
Figure 5 is a state variable diagram showing the various
states of the reference voltaye generator of the present
invention.
Figure 6 is a circuit schematic diagram showing the
; implementation of the preferred embodiment of Figure 4.
Figure 7 ls a prior art comparator circuit utilized as a
signal comparator of Figure 1.
.
~2~g~3~
Figure 8 is a circuit schematic diagram of a self-biased,
high-gain differential amplifier of the preferred embodiment.
Figure 9 is a circuit diagram of the self-biased, high-gain -
differential amplifier configured for use as a general- !
purpose differential amplifier.
'
, . .
~2~
~TAILED ~EscRIpTIo~ OF T~E I~E~ION
An input buffer configuratiorl for providing CMOS
compatible signals from an input signal and the use of a
self-biased high-gain differential amplifier a~e described.
In the following description, numerous specific details are
set forth such as specific circuit components, signal levels,
etc., to provide a thorough understanding of the present
invention. It will be obvious, however, to one skilled in
the art that the present invention may be practiced without
these specific details. In other instances, processing
steps, control lines, and well-known structures have not been
set forth in detail in order not to obscure the present
invention in unnec~ssary detail.
lS Referring to Figure 1, an input buffer 10 of the present
invention is shown. The buffer 10, as implemented in the
preferred embodiment~ is a single integrated circuit. Buffer
10 is comprised of a plurality of signal comparators 11,
which provide for a plurality of input buffers, and a
reference voltage generator 12. Reference voltage generator
12 generates a reference voltage VREF, which provides for a
reference voltage level to signal comparat~rs 11. The actual
number of signal comparators ll coupled to reference voltage
generator 12 is a design choice. For simplicity, the
following description will refer to a single comparator ll,
but it is to be underst~od that the description applies to
each of the comparators. Further, each comparator 11 has its
own VIN and VouT, as i5 shown ln Figure 1.
Signal comparator 11 is coupled to accept an input
signal V~N and to provide VouT as an output signal. VIN is
typ~cally o~ a signa} Ievel which is compatible with TTL and
~OUT is a CMOS level compati~le signal. However, signal
comparator 11 can be deslgned to function with various input
.
~2~ 3~
signal levels and to translate these signal levels to a CMOS
compatible signal VO~T-
The reference voltage generator 12 provides thereference voltage VREF, which is nominally equal to the
specified logic threshold of VIN. This VREF signal is used
to set the comparison reference signal required by signal
comparator 11. Comparator 11 compares VIN to VREF- If VIN
exceeds VREF, then VouT is at a first output state.
Conversely, if VIN does not exceed VREF then Vo~T is at a
second output state.
For example, when VIN is a TTL level signalr the high
logic level VIH can be as low as 2.0 volts, while the low
logic level, VIL, can be as high as 0.8 Yolts. A threshol~
level of 1.4 volts can be chosen as the value of VREF such
that VIN levels greater than 1.9 ~ol~s are treated as VIH and
- VIN levels be~ow 1.4 volts are treated as VIL. It is to be
appreciated that a TTL level example is chosen here; however,
the present invention can be utilized to opera~e with various
input logic signal level schemes. The value of the reference
voltage VREF is a design choice, chosen to select a threshold
level between VIL and VIH of the input signal VIN-
--~!~
Referring to Fiqure 2, a preferred embod~ment of the
reference voltage generator 12 of Fiqure 1 is shown.
Generator 12 is actually a precision switched-capacitor
voltage divider, which divides a voltage source potential,
`; such as ~CC, to the desired VREF value. Generator 12 of the
preferred embodiment is comprised of a plurality of switches
and capacitors. A switch 16 and a capacitor 20 are coupled
in series between a voltage source, such as VCC, and its
return VSS, which ls ground in this instance. Two switches
17 and lB are coupled ln series between the ~unction of
,
~2~39 Ei;~
switch 16 and capacitor 20 and the output line which provides
VREF. A capacitor 22 is coupled between the ~utput line and
ground. At the junction of switches 17 and ~8, a switch 19
and a capacitor 21 are coupled in parallel between the
function and ground.
As used in the preferred embodiment, switches 16 and 19
operate in conjunction with clock phase PHI1, switch 17 with
clock phase PHI2 and switch 18 with clock phase PHI3. Also,
for simplicity in discussing the various equations as they
apply to circuitry of the various embodiments, references Cl,
C2 and CouT axe also utilized. In Figure 2, capacitors 20,
21 and 22 are equivalent to C1, C2 and COUT, respectively.
Also referring to Figure 3, waveforms for the three
clock phases PHI1, PHI2 and PHI3 are shown in reference to
the timing of system clock CLK. Each of the switches 16-19
is in the closed position when its respective clock phase is
in the high state and, conversely, each of the switches 16-19
is in the open position when its respective clock phase is in
the low state.
The switched capacitor divider circuit of Figure 2
operates as follows. During the positive going portion of
PHI1, switch 16 is closed and capacitor C1 charges toward
VCC. During this period, phase PHI2 is in its low state and
switch 17 is open. However, because switch 19 is closed due
to PHIl being high, capacitor C2 discharges to ground. The
pulsewidth duration of PHI1 is of suf~icient length for the
charging/discharging transients to dissipate completely. At
the end of the PHI1 cycle, the charges appearing on the two
capacitors C1 and C2 are determined by
Q1 = C1*VCC (Equation la~
~ = 0, (Equation lb)
` 9
39631
where Q1 and Q2 are the charyes on capacitors C1 and C2,
respectively.
When switches 16 and 19 open as P~Il transitions to its
low state, PHI2 then transi~ions to its high state closing
switch 17. During the time PHI2 is high, capacitors C1 and
C2 are shorted together and charge flows out ~f C1 and into
C2. After the current transient has dissipated, the charges
on the two capacitors C1 and C2 are given by
Q1 = Cl*VDIV (Equation 2a)
Q2 = C2*VDIV- ~Equation 2b)
.
By charge conservation, the sum of the charges of the
two capacitors Cl and C2 at the end ~f the PHI1 phase must be
exactly equal to the sum of the charges of the two capacltors
Cl and C2 at the end of the PHI2 phase. That is,
C1*VCC = (C1 + C2)VDIV- (Equation 3)
Then, solving Equation 3 fox VDIV~ the following is
obtained.
~DIV = VCC/(1 + C2/C1). (~quation 4)
Then, while PHI2 is still high and PHI1 is still low,
PHI3 goes to its high state closing switch 18. At this point
switches 16 and 19 are open while switches 17 and 18 are
closed, xesulting ~n capacitors C1 and C2 bein~ coupled to
the output capacitor CouT. In reality, capacitor CouT
represents the actual output capacitance, which includes the
com~ned input capaci~ance of all of the input buffer lead
capacitance present on the interconnection between the
reference ~oltage generator 12 and the input capacitance of
~ .
~, 10
~28~ii3~L
the signal comparator 11, as well as any other stray
capacitance present.
Typically, the value of the output capacitance as
represented by capacitor CouT ls much larger than the
combined capacitance of capacitors Cl and C2. Therefore/ the
charge transferred from capacitors C1 and C2 to capacitor
CouT will charge capacitor CouT only slightly. However, with
the repetitive execution of the three phase operation
represented by PHI1, PHI2 and PHI3 as shown in Figure 3,
capacitor CO~T will slowly charge ~or discharge, if for some
reason VREF is greater than VDIv) to V~IV, much in the same
way a capacitor is charged through a large resistance.
From an analysis of the charge transfer characteristic
from capacitors Cl and C2 to capacitor COUT, the voltage on
capacitor CovT approaches VDIV according to
VREF(n) = kn * VREF(0) ~ kn)VDIV, (Equation 5)
where VREF(n) is the voltage on capacitor Co~T after n
xepetitions of the three phase operation, VREF(0) is the
initial voltage on capacitor CouT (usually 0 volts) and k
equals CouT/(C1 + C2 + COUT). Because k is less then unity,
kn approaches 0 in the limit and, therefore, VREF approaches
VDIV in the limit. VREF is the actual reference voltage
provided to all of the input buffers on the chip as an output
of generator 12 to signal comparator 11.
Solving Equation S for n, and letting VREF(0) be 0 volt,
the result obtained is
n = ~n(1 - a~/~n k, ~Equation 6)
'~
where "a" equals VREF~n)/vD~v and ~n is the natural
~ 35 logarithm- By u~ing Equation 6, the time required for VREF
:, : ' ` '
~1
~L2~963~1L
to approach VDIV within an acceptable tolerance can be
estimated.
The actual timing sequence is shown in Figure 3. The
timing separation of the leading and trailing edges of the
various pulses of the four waveforms are distinguished by the
dotted lines. It is to be noted that some finite time period
occurs between the time PHI1 goes low and PHI2 going high, as
well as between PHI2 and PHI3 going low to PHIl going high.
This time separation is necessary to ensure that various
switches are placed in a given position before other switches
change states.
By example, if a reference voltage of 1.4 volts is to be
generated by dividing down a VCC value of 5.0 volts, the
required ratis of Cl to C2 is ~ound from Equation 4 t~ be
equal to 18/7 (2.571428... )O Therefore, it is the ratio of
the capacitance values of capacitor C1 and C2 which
determines the value of VREF in reference to VCC.
In the practice of the present ~nvention VREF has
negligible dependence on temperature and processing
variations, but it is directly dependent on VCC variations,
such that an X% change in VCC causes an X% chanqe in VREF.
For the example, because VCC is specified ge~erally to vary
no more than + 10%, VREF will vary no more than ~ 10%, or i
0.14 volts for V~EF eqyal to 1.4 volts nominal.
The present invention utilizes metal oxide semiconductor
(MOS) technology to implement the circuit shown in Flgure 2.
A MOS capacitor may be implemented with an n-type device
whose source and drain are coupled to VSS, or with a p-type
; d~vice whose source and drain are coupled to VCC. However,
an M~S capacitor ~ehaves in a non-linear fas~1on for gate
voltages below the thre~hold vol~age of that device.
; Spec$fically, for gate voltages bel~w the threshold ~oltage,
the capacitance of ~he dev~ce is typ$cally low, w~ile in tbe ~`~~--
~2
~139~i3~5L
region of the thresh~ld voltage, the capacitance rises
sharply until the capacltance value levels off at its
asymptotlc value.
The charge on the gate of an MOS capacitor is
approximated by
0, for VGATE < VT
C(V - VT), for V > or = y
GATE GATE T (Equation 7)
where Q is the charge stored on the device, C is the
asymptotic capacitance of the device, VGATE is the voltage
applied to the gate of the device, and VT is the'threshold
voltage of the device.
If both capacitors Cl and C2 are implemented as n-type
MQS devices, then Equation 7 is used to calculate the charges
on these two device~ at the end o~ the PHIl cycle and also at
the end of the PHI2 cycle. At the end of PHI1, the charges
on the two devices Cl and C2 are given by
Q} = Cl(VCC - VT) ~Equation 8a~
Q2 = - ~Equationt8b)
At the end of PHI2, the charges on the two capacitors C1 :
and C2 are given by
Q1 = Cl(VDIV ~ VT) (Equation 9a)
Q2 ~ C2~VDIV ~ VT)- (Equation 9b)
Invoking charge conserva~ion on Equations 8a, 8b, 9a and
: 9b, and solving for VDIvr t~e ~ollowing is obtained
~:' -
,
~ 13
~'
3~
VCC T
V = ~ + __
DIV 1 + C /C l ~ C /C
2 1 1 2 ~Equation 10)
However9 by applying Equation 10, VDIv will result in a
large error caused by the threshold voltage VT of the two
devices. For example, if VT equals 0.7 volts and the ratio
C~/C1 equals 18/7, then VDIV from Equation 10 will equal 1.90
volts. That is, the threshold voltage has caused an error to
VDIV of 0.5 volts, which calculates to 0.5/1.4~ or
approximately 36%.
An attempt can be made to correct this error by
increasing the C2/Cl ratio, such that VDIV is again ~educed
to 1.4 ~olts. However, due to the fact that VT is a highly
variable parameter dependent on processing parameters,
temperature and VCC, an increase in the ratio would not
remove the variability caused by VT. In order to overcome
this variability caused by the threshold voltage, the circuit
of the preferred embodiment is implemented as a combination
of an n-type device and a p-type device.
Referring to Figure 4, a switched-capacitor divider
circuit of the preferred embodiment is shown utiliz~ng both
n-type and p-type devices. The circuit of Figure 4 is
equivalent to that of the circuit oP Figure 2, wherein C1 is
implemented as an n-type capacitor 31 and C2 is implemented
as a p type capacitor 32. Because capacitor 32 is a p-type
device it is coupled from the junction of switches 17 and 18
~o VCC tnstead to VSS as is shown in Flgure 2- COUT of
Figure 2 is lmplemented as a p-n capacltor pair comprised of
p-type device 33a and n-type devlce 33b. N-type device 33b
is coupled between the output line and VSS, whereas p-type
device 33a is coupled between the output line and ~CC. The
two device~ 33a ~nd 33b are equi~alent to capacitor COUT f
F~gure 2. Because the dlmensions of 33a and 33b are egual,
14
3L2~
the effects of power supply and ground nolse on VREF is
symmetrical and is removed from the output VREF-
Utilizing the implementation shown in Figure 4, thecharges on Cl and C2 at the end of PHI1 are given by
Q1 = C1(VCC - VTN) ~Equation lla)
Q2 = -C2(VCC ~ VTp~, (Equation llb)
where VTN is the threshold voltage of Cl, and VTp is the
threshold voltage of C2 (VTp is a negative quantity because
C2 is a p-type device).
At the end of PHI2, the charges on the two devices C
and C2 are given by
Q1 = C1(VDIV ~ VTN) (Equation 12a)
Q2 = -C2(VCC - VDIV ~ VTp). (Equation 12b)
Invoking charge conservation on Equati.ons lla, llb, 12a
and 12b and solving for VDIV~ the result obtained is that
~iven by Equation 4, just as if ideal linear capacitors were
used. That isl a divider implemented with an n-type device
for Cl and a p-type device for C2 will not be sensitive to
temperature or processing ~ariations.
An elaboration on the capacitors utilized in the present
invent~on is needed in order to achieve the desired results
of the present invention. On account of frin~ing field
effect , ~he capaci~ance of a capacitor is not only a
function of its area, but a}so of its circumference. Thus,
the capacitance ratio of t~o capacitoxs is ~ot generally
equal to their area ratio, unless both capacitors are
identical in area and circumference. For example, a C2/C1
ratio o~ 18/7, which is required in order to obtain ~ VREF f
1. 4 volt3, cannot be obtained 1mply by implementing two
~L 5
.. . .
~g~3~
capacitors with an area ratio of 18/7. In order to remove the
error caused by differi~ng circumferences, small capacitors of
fixed dimensions, called "unit" capacitors are used to
implement the desired capacitors of the present in~ention.
Instead of providing the requisite capacitance for a
capacitor by setting its dimensions, the capacitance is set
by coupling a selected number of unit capacitors in parallel.
Two capacitors implemented in this fashion have both an area
ratio and a circumference ratio equal to N2/N1, where N1 is
the number of unit capacitors used to implement the first
capacitor and N2 is the number of unit capacitors used to
implement the second capacitor. Because both the area
capacitance and the fringing field capacitance of the two
capacitors are related by N2/N1, the total capacitances of
the capacitors are each related by the ratio N2/N1. By using
this unit ~apacitor technique, the C2/C1 ratio of the above
example of 18/7 is implemented by utilizing eighteen unit
capacitors connected in parallel for C2 and seven unit
capacitors coupled in parallel for Cl.
The xeference voltage ~enerator 12 of the preferred
embodiment is designed as a finite-state machine having three
state variables. The machine states are represented in the
state diagram of Figure 5. Each state variable represents
one of the three phases, PHI1, PHI2 and PHI3, in that order. ~`
The machine can be in one o~ the following three states in
normal operation:
State 100 = PHIl*PHI2#*PHI3~ (Equation 13a)
State 010 = PHIl~*PHI2*PHI3# (Equation 13b)
State 011 = PHI17*PHI2*PHI3 ~Equation 13O)
The other five s~ates which can ~e derived from the three
state variables are ille~al states.
,
,
128~631
The state diagram of Figure 5 is also utilized in the
initialization of the reference voltage generator of the
present invention. In order for the input buffers to be in a
ready state by the time power-up reset is completed in the
device, the reference voltage generator 12 must provide a
stable reference voltage VREF even prior to the completion of -
the power-up reset sequence. The three-phase clock generator
must be operational prior to the completion of the reset
sequence initiated by a reset signal, such that by the time
the reset cycle is completed the three-phase clock generator
will have already been placed in one of the legal states of
the finite-state machine. In order to achieve this
requirement, the initialization of the three-phase clock
generator to generate VREF cannot rely on the system reset
signal.
Because no reset signal is available to force the
finlte-state machine of the present invention to enter one of
the legal states if it is started in an illegal state, the
finite-state machine is designed as is shown in Figure 5.
During power-up, if an illegal state occurs, the finite-state
machine is designed so that it will automatically recognize
~ that it is ln an illegal state and within one clock cycle,
; enter state 000. Once state 000 has been entered, any
further transitions will only occur within one of the three
legal sta~es (states 010, 011 and 100), due to the cycling
arrangement shown in Figure 5. It is to be noted that all
transitions between states are unqualified regardless of the
inputs.
Referring agaln to Figure 3, the waveform diagram shows
vari~us overlap timlngs incorporated into the clocking scheme
of the present invention. This overlap scheme is used to
ensure that a ~irst swltch has completely changed its state
prior to a second switch changing its s~ate. For example, lf
17
`:
~2Bg631
PHI2 transitions to a high state before PHI1 has completed
tran~itioning to its low state, Cl can be momentarily shorted
to ground, or, in the alternative, C2 could be momentarily
shorted to VCC, in which event the sum of the charges on the
two capacitors Cl and C2 will have a different value than
that which is desired. To prevent such an occurrence, PHI2
is logically forced off until PHIl has transitioned to its
low state, as is shown by arrow 25.
Similarly, if PHI1 transitions to a high state before
both PHI2 and PHI3 have completed their transition to their
. low states, CouT can be momentarily shorted, thereby, causing
an error in the vol~age value of CouT. In order to prevent
such an error, the presen~ invention causes PHIl to be
logically forced off until PHI2 and PHI3 have both
transitioned to their low states, as is shown by arrow 26.
The high-to-low transitions of PHI2 and PHI3 follow the
trailing edge of the cloc~ pulse as is shown by arrow 24.
It is also to be noted that after PHIl transitions to
its high state following a trailing edge of the clock pulse
as shown by arrow 24, the next subsequent trailing edge of
the clock pulse causes PHI1 to transition to its low state,
as is shown by arrow 27. Also, after PHI2 has transitioned
to a high state following the trailing edge of the clock
pulse shown by arrow 27, the subsequent trailing edge of the
clock pulse causes PHI3 to transit$on to a high state
following a predetermined timelag, as is shown by arrow 28.
Then tha sequence is repeated at the trailing edge of the
next clock pulse.
Referring ~o Figure 6, a circuit diagram of the
reference voltage generator 12 of Fi~ure 1, as implemented
; according to Figure 4, is shown as a circuit of the preferred
embod$ment. Seven uni~ capacitors formed from n-type devices
comprise capacitor Cl, while 18 unit capacitors ~ormed from
~8
~L289~3~
p-type devices comprise capacitor C2. A p-type device forms
switch 16 while n-type devices form switches 17, 18 and 19.
Switches 16-19 and capacitors C1 and C2 are coupled
electrically as is shown in the diagram of Figure 4. The
output capacitor CouT is split between a p-type de~ice
forming CoUT(a) and an n-type device forming C~UT(b) as is
also shown in Figure 4. The various transistor switches 16-
19 are controlled by clocking signals PHI1, PHI2 and PHI3,
which are coupled to the appropriate gates of transistors 16-
18.
The rest of the circuit of Figure 6 is comprised ofthree D-type flip-flops, two multiplexors and various
combinatorial logic gates to provide the finite-state machine
of Figure 5. A D-type flip-flop 40 has its outputs coupled
to multiplexor 43, which is then coupled to D-type flip-flop
41. The output of flip-flop 41 is coupled to D-type flip-
flop 42, which output is then coupled to multiplexor 44,
which then has its output coupled back as an input to flip-
flop 40. A number of NAND gates and inverters are included
in this flip-flop/multiplexor loop to provide the necessary
logic and time delays to implement the state diagram of
Figure 5.
The clock signal CLK of Fi~ure 3 is coupled to the three
flip-flops 90-42 to provide the necessary clocking of these
25 ~lip-flops 40-42. The output of flip-flop 40 is utilized to
provide the signal PHIl to drive the gates of transistors
represen~ing switches 16 and 19. Signal PHI2 is derived from
t~e output of the second flip-flop 41, which is then used to
: drive the gate of the transistor representlng switch 17.
PHI3 is derived from the output of the third flip-flop 42 and
is then used to control the gate o~ the transistor
representing switch 18. A number of N~ND gates and inverters
are utilized to provide the necessary. logi:: and delays for
: 19
~963~
~he generation of PHI1, PHI2 and PHI3. The necessary delays
shown in Figure 3 are derived ln th~ circuit of Figure 6.
PHI1 is coupled back as one of the inputs for providing PHI2,
such that the necessary delay for generating PHI2 from PHIl
is provided by this delay sequence. In order to provide the
delay of PHI1, both PHI2 and PHI3 are coupled as inputs for
generating PHI1. Therefore, in Figure 6 the finite-state
machine is represented by fl1p-flops 40-42, multiplexors 43-
44 and the associated combinatorial logie in the looping
circuit of the upper portion of the schematic. The necessary
time delays to prevent the overlap of the operation of the
various switches 16-19 are provided by the combinatorial
logic coupling the looping circuit to the switched capacitor ~-
circuit at the bottom portion of the drawing of Figure 6. It
is to be appreciated that although a particular embodiment is
shown as the preferred embodiment in Figure 6, various other
schemes can be implemented without departing from the spirit
and scope of the present invention.
The reference voltage VREF, which is providqd as an
output from reference voltage generator 12, is then coupled
to signal comparator ll as shown in Figure 1. The signal
comparator 11 can be any of a variety of comparators which
are used to toggle between two states depending on the value
of the input voltage~ Although a variety of prior art
comparators can be utilized, one prior art comparator circuit
50 is shown in Figure 7. A p-channel transistor 51 and a n-
channel transistor 53 are coupled in series between a voltage
supply source, such as VCC, and node 56. A second pair of
transistors formed by p-channel transistor 52 and an n-
channel transistor 54 are coupled in series between thevoltage source and node 56 also. VREF from the re~erence
voltage generator 12 is coupled to the gate of transistor 53.
The drains of transi ~ors 51 and 53 are coupled ~ogether to
ao
.
~2~39631
the gates of transistors 51 and 52. The VIN signal is
coupled to the gate of trans~stor 59, and the drains of
transistors 52 and 54, are coupled as an output VouT through
inverter 57. Transistor 55 is coupled between node 56 and
5. VSS, which in this case is ground, and the gate of transistor :
55 is coupled to VCC. The operation of this ~ircuit is
simply controlled by the value of VREF and VIN- Whenever VIN
is less than the value of VREF, VouT transitions to one CMOS
logic state, and when VIN is greater than VREF~ VOUT
transitions to the other CMOS logic state.
SELF-BIASED, HIGH~ IFFER~N~IAL ~PLIFI~R
; Although the above-described CMOS input buffer
circuitry, which includes the reference voltage generator of
the present invention, can operate with a prior art
comparator circuit, a high-speed comparator of the present
invention functions to provide an improvement over prior art
comparators. Referring to Figure 8, a high speed comparator
;20 circuit 60 of the present invention is shown. The purpose of
comparator 60 is to convert VIN, which typically has TTL
level signals, to a CMOS compatible VouT, wherein the
switching level is determined by the value of VREF. A CMOS
transis~or pair comprised of p-type transistor 61 ~nd n--type
25 transistor 6~ are coupled in series between nodes 71 and 72.
Node 71 is coupled to a voltage sourc~, such as VCC, through
a p-type transistor 64. Node 72 is coupled to VSS, which in :
this case is ground, through an n-type transistor 65. The
drains of transistors 61 and 62 are coupled together to the
30 gates of transistors 64 and 65. The gates of trans~stors 61
and 62 are driven by the signal VREF-
Also coupled in series between nodes 71 and 72 is
another pair of CNOS translstors formed by p-~ype transistor
66 and n-type.translstor 67. The gates of transistors 66 and
21 ~ .
~2~g63~L
67 are coupled together to receive VI~, and the drains of
these two transistors 66 and 67 are coupled to drive the
gates of a third set of CMOS transistors 68 and 69. A signal
VCoMp is obtained at the drain ~unction of transistors 66 and
67. VcoMp is coupled to drive the gates of a CMOS inverter
formed by transistors 68 and 69. P-type transistor 68 and n-
type transistor 69 are coupled in series between VCC and VSS,
and VouT is obtained from their drain ~unction.
The comparator 60 is actually a differential amplifier.
In operation, transistors 61 and 62 are identical in size and
structure to transistors 66 and 67, respectively~ This is
done so that both CMOS pairs have identical electrical
behavior. Transistors 64 and 65 are utilized to provide bias
for transistors 61, 62, 66 and 67. Because transistors 61
and 62 conduct together, the connection at their drains
provides a biasing voltage VBIAS~ which is then coupled to
the gates of transistors 64 and 65. This results in a self-
biasing technique, wherein transistors 61 and 62 operate in
their active regions in spite of variations attri~uted to
processing and temperature.
The size of transistors 61, 62, 64 and 65 are c~osen so
that under typical conditions for processing, temperature and
VCC, transistors ~1 and 62 are biased substantially in the
center of their active region. Under certain conditions, the
bias point of transistors 61 and 62 will shift away from the
center of the active region, either above or below the
center, depending on the nature of the conditlons. However,
due to the negative feedbac~ provided by transistors 64 and
65 at nodes 71 an~ 72, and through the negative feedback
inherent in the ~elf-biasing technique, the shift in ~he bias
~; point will be minim~zed, and the bias point ~ill remain
within the actlve region of transistors 61 and 62.
2~
~l39~ii3~L
Because transistors 66 and 67 are identical in all
respects to transistors 61 and 62, when VIN is equal to VREF~
transistors 66 and 67 will become biased identically to
transistors 61 and 62. That is, transistors 66 and 67 will
also be biased in the active region. Therefore, the VCOMP
voltage on the drain ~unction of transistors 66 and 67 will
be equal to the voltage VBIAS. VBIAS, along with VCoMp~ will
have a value somewhere between the high state and the low
state of VIN-
When VIN is made to transition from a low state to a
high state, then VCoMp will switch from a high level to a low
level, with the center of the switching region at or very
near to the point where VIN equals VREF. Furthermore, the
switching charasteristic of VCoMp will be sharp about the
point where VIN equals VREF, with VCoMp making a full
transition from a high state to a low statP for a small
change in VIN. Transistors 68 and 69 serve as an inverter
and amplify VCoMp further in order to obtain a full output
swing from VCC to VSS as VOUT-
An n-type device 73 has its gate coupled to node -71 and
its drain and source coupled to VSS. Device 73 is coupled to
function as a capacitor. When VIN switches from a high state
to a low state, VCoMp switches from a low state to a high
state, and device 73 provides some of the charglng current
necessary to charge the parasitic capacitance on VCoMp~
thereby speeding the rise time of the comparator. It is to
be appreciated that a p-type device 74 can be coupled to node
72 to improve the fall time of the comparator. However,
because the fall time of the comparator is much shorter than
the rise ~ime without the addition of device 74, the
addltional i~provement in performance i5 negligible~
Therefore as is implemented in the preferred embodiment,
device 74 ~s no~ u~ilized.
23
~2~39~33L
It is to be appreciated that the differential amplifier
60 can be implemented as the signal comparator 11 of Figure 1
to provide faster performance for the C~OS input buffer of
the present invention. It is to be further appreciated that
the self-biased, high-gain differential amplifier of Figure 8
can be utilized with other circuits other than the reference
voltage generator 12 of the present invention and is not
limited to the described application of the CMOS input
buffer, which is a self-biased high-gain differential
amplifier that provides a high-speed comparator.
Referring to Figure 9, the differential amplifier 60 of
Figure 8 is shown, but in a general differential amplifier
configuration. The suffix ~a" has been added to the
reference numerals of Figure 8 to designate equivalence.
lS Further the output inver~er has been deleted although such
in~erters can be used. One input VIN(a) is coupled to the
gates of transistors 61a and 62a. A second input VIN(b) is
coupled to the gates of transistors 66a and 67a. The two
inputs can be DC differential inputs or two AC differential
inputs.
The two capacitors 73a and 74a improve switching speeds
if one of the inputs is connected to a DC level. However, if
the inputs are AC, then the capacitors 73a and 74a are not
used because they degrade the switching speed.
It is to be appreciated that the self-biased high-gain
differential amplifier 60a can be used for various
applications, including general purpose differential
amplifier, sense amplifiers, front end for operational
amplifiers and hig,-speed comparators. These examples are
2~
.
~2~9~3~
for illustration only and are not provided to limit the
present invention.
Thus, an improved CMOS input buffer utilizing a switched
capacitor voltage reference source and a self-biased high-
gain differential amplifier circuit is described.
, ~
