Note: Descriptions are shown in the official language in which they were submitted.
IBM Docket No. BC9-86-010
COMPUTER SYSTEM HAVING PROGRAMMABLE DMA CONTROL
DESCRIPTION
Technical Field
The present invention relates to a DMA (Direct Memory
Access) controller for use in a microcomputer or
minicomputer system. More particularly, the invention
provides a DMA controller with which peripheral devices
in a number greater than the number of physical DMA
channels provided in the system can perform DMA data
transfers.
Prior Art
Many present-day computer systems employ DMA channels
to allow peripheral devices to transfer data, primarily
to and from the main memory, without going through the
CPU (Central Processing Unit~. Bypassing the CPU of
course has the advantage of increased data transfer
rates and improved overall system efficiency because
the CPU is free to perform other tasks during the data
transfer.
The most common practice to date has been to provide
one physical DMA channel for every peripheral unit that
is allowed DMA access. An example of a computer system
which employs such an arrangement is the IBM PC comput-
er.
.
However, the number of peripheral devices which a user
may attach to his or her computer system have been
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IBM Docket No. BC9-86-010
increasing and is expected to CGntinUe to do so. For
instance, lately there have become available optical
disk readers, additional communications devices, hard
files, tape backup devices, high speed printers, etc.,
all of which can make advantageous use of DMA access.
On the other hand, adding further physical DMA channels
is costly of system hardware, including IC count, board
space, and bus space. It has been considered to share
DMA channels among peripheral devices with the restric-
tion of mutually exclusive operation. Sharing of Dr~A
channels is employed in, for instance, the IBM XT and
AT computer systems. These schemes though require
extensive modifications to the operating system as
additional subroutines are required to prevent the
peripheral devices associated with each DMA channel
from operating simultaneously. A significant perfor-
mance burden is also created when file controllers are
not sufficiently "intelligent" to allow overlapped seek
operations. The problem is compounded in certain
situations, for example ~hen a LAN (Local Area Network)
feature and a file controller share the same DMA level
and a LAN file server routine must trade back and forth
between the two devices.
U.S. Pat. No. 3,925,766 to Bardotti et al. discloses a
computer system wherein peripheral devices are assigned
priori~y levels, and requests for access to communicate
with a memory are selected according to the priority
levels. The priority level assignments can be changed
according to the causes for which the reg~lest signals
are generated or the particular load conditions of the
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IBM Docket No. BC9-86-010
central processor. No DMA paths are provided, howe~-
er.
In U.S. Pat. No. 4,400,771 to Suzuki et al. there is
shown a multi-processor system in which each of the
multiple processors can access a single memory. A
programmable ~egister circuit stores priority informa-
tion designating a memory access grade priority for
each of the processors. The priority information can
be changed manually, by an external circuit, or by at
least one of the processors. The Suzuki et al. patent
does not though employ DMA access to a memory from
plural peripheral devices.
U.S. Pat. No. 4,257,095 to Nadir is of interes'c in its
teachings regarding bus arbitration techniques.
-
; 15 The following United States patents-are mentioned for
`generàl background teachings related to computer
~systems employing DMA controllers: 4,371,932 to
Dinwiddie, Jr., et al., 4,419,728 to Larson, 4,538,224
to Peterson, 4,556,962 to Brewer et al., and 4,584,703
to ~allberg.
Objects of the Invention
Accordingly, it is an object of the present invention
to provide a computer system employing a DMA controller
wherein peripheral devices in a number greater than the
number of physical DMA channels provided in the system
can share the DMA channels without encountering the
problems of the prior art approaches discussed above.
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IBM Docket No. BC9-86-010
,,
It is a further object of the invention to provide such
a computer system in which each peripheral device
allowed DMA access is assigned its own DMA access
arbitration lavel.
It is yet a further object o~ the invention to provide
such a-computer system in which the assignment of DM~.
channels to peripheral devices can readily be con-
trolled in software without making extensive modifica-
tions to the operating system.
Summary of the Invention
In accordance with the above and other objects of the
present invention there is provided a computer system
including a plurality of peripherals requiring DMA
access, the number of peripherals being greater than
the number of DMA channels provided in the system.
Some of the peripherals are allotted fixed, dedicated
ones of the DMA channels, while others of the peripher-
als share the remaining DMA channels. The shared
remaining channels are herein called "programmable" DMA
channels. These additional DMA channels are nonphysi-
cal, and hence may be term "virtual" DMA channels to
distinguish them from the physical or "real" DMA
channels.
.
Each of the peripherals is given a channel priority
assignment. An arbitration circuit stores DMA channel
assignment values, one for each of the DMA channels
provided in the system. For each peripheral having a
dedicated DMA channel, a fixed DMA channel assignment
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IBM Docket No. BC9-86-010
.
value is stored, while for the remaining peripherals,
which share the proyrammable DMA channels, a programma-
ble DMA channel assignment value is stored.
When a psripheral wants DMA access, it transmits its
channel priority value onto an arbitration bus. The
highest channel priority value "wins" on the arbitra-
tion bus. The winning channel priority value is
compared with the fixed and programmable DMA channel
assignment values. If the channel priority value
successfully compares with one of the stored fixed or
programmable DMA channel assignment values, it is
granted access to the corresponding DMA channel.
Brief Description of the Drawings
j FIG. 1 is a block diagram showing a computer system
employing the invention.
FIG. 2 is a conceptual diagram used to explain the
operation of the present invention.
FIG. 3 is a logic diagram depicting in detail an
- arbitration circuit provided in peripheral devices of
the computer system o FIG. 1.
FIG. 4 is a diagram showing details of one of the
buses in the computer system of FIG. 1.
FIG. 5 is a detailed logic diagram of a central arbi-
tration control circuit employed in the computer system
of the invention.
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IBM Docket No. BC9-86-010
FIG. 6 is a detailed logic diagram of a DMA control
circuit used in the invention.
,~
Detailed Description of the
Preferred Embodiment of the ~nvention
Referring first to FIG. 1 of the accompanying drawings,
there is shown a block diagram of a computer system in
which the present invention is used to advantage.
A CPU communicates with a main memory 15, bus control-
~ ler 16 and math co-processor 14 via a system bus 26.
Communication between the CPU and its associated
peripheral devices is through a bus controller 16, the
latter being coupled tb the peripheral devices through
a family bus 25. In the present example, the peripher-
al devices include an auxiliary memory 17, two communi-
cations devices 18 and 19, a hard file 20, an optical
disk 21, and two floppy disks 23. Other peripherals
can of course be used as well as system needs dictate.
The peripheral devices are represented generically by
DMA slave 24.
A ~MA controller 12 is provided to allow at least
- selected ones of the peripheral devices direct memory
access. For this purpose, as ~ill be explained in more
detail below, the family bus, or at least a portion
thereof, is branched to the DMA controller 12. Each
~5 peripheral allowed DMA access is provided with an
arbitration circuit 24, and each peripheral having an
arbitration circuit is assigned an arbitration (priori-
ty) level. Again as will be explained in more detail
IBM Docket No. BC9-86-010
later, a central arbitration control circuit 11 is
associated with the DMA controller to arbitrate among
peripheral devices concurrently requesting DMA access
and to inform the DMA controller of which peripheral is
to have access.
In the computer system embodying the invention, the
number of peripheral devices to be allowed DMA access
is greater than the number of physical DMA channels
provided in the system. In accordance with the present
invention, some of these devices are allotted their own
dedicated DMA channel, while others share the remaining
DMA channels. On the shared (programmable) channels,
access is in order of preassigned priority.
In the present example, it is assumed that there are
eiyht physical DMA channels, designated O through 7.
It is further assumed that channels O and 4 are shared,
and that remaining channels 1-3 and 5-7 are dedicated
to individual peripherals.
Referring now to FIG. 2, which is a conceptual drawing
used to explain the principles of the present inven-
tion, a comparator is provided with two sets of inputs.
One set is composed of four lines from a bus ARB~S
(ARbitration Bus). The value on the ARBUS is indica-
tive of the peripheral currentl~ requesting a DMA
channel having the highest arbitration (priority)
level. If that peripheral is one of those having one
of the dedicated channels 1-3 or ~-7, access is granted
directly to that channel. On the other hand, if the
peripheral is one of those having to share a
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IBM Docket No. BC9-86-010
programmable ~MA channel (channels O and 4), access is
- granted only if its priority level corresponds to one
of the values preset in registers 6 and 7. This
operation will be explained in more detail below with
reference to Figs. 3-6.
FIG. 3 is a logic diagram of one of the arbitration
circuits 28 used in each of the peripherals allowed D~A
access. I'he arbitration level assigned to the periph-
eral is set in a register 70, hereinafter referred to
as the channel priority assignment register. This may
be done using any of a number of well-known techniques.
Preferably, the CPU addresses the peripheral through a
preassigned port so that the arbitration level can be
set through software. This may be done through the
BIOS (Basic Input-Output Syste~l), POST (Power-On Self
Test) at reset, the operating system, or the applica-
tion program as desired. Other~ise, it is possible to
input the channel priority assignment value with
hardware switches.
The actual arbitration circuitry is implemented with of
an arbiter 72. This circuit, including the various
signals indicated in FIG. 3, is disclosed and discussed
in de~ail in American National Standard/IEEE Standard
No. ANSI/IEEE Std 696-1983, published by the Institute
of Electrical and Electronics Engineers, Inc., June 13,
1983. In general, each device incorporated in the
arbitration scheme is provided with such a circuit, and
the circuits are connected together via an ARBUS. The
ARBUS in the example shown has four data lines TMAO -
TMA3, allowing for 16 different arbitration levels.
IBM Docket No. BC9-86-010
Any desired number though can be used. During an
arbitration time period designated by the control
signals pHLDA and HOLD, all devices desiring to gain
control over the bus (those having the IWANT signal set
S to the high ("1") state) transmit their arbitration
(priority) levels onto the ARBUS. This occurs in the
example of FIG. 3 when the signal /APRIO ("/" indicat-
ing a "low-truth" signal) goes to the low ("O") state.
The value then held in the register 70 is gated through
the AND gates 71 to the arbiter 72 and thence onto the
ARBUS lines TMAO - TMA3. At the end of the arbitration
period, the value on the ARBUS lines TMAO - TMA3 will
be the value o~ the arbitration level of the device
having the highest level. The waveforms of the various
signals mentioned here are shown in detail in the
referenced ANSI/IEEE standard.
In the preferred embodiment under discussion, the ARBUS
forms a part of the family bus 25 coupling the periph-
erals to the bus controller 16 and thence to the CPU
10. The relationship of the ARBUS to the overall
family bus 25 is depicted in FIG. 4.
The details of the central arbitration control circuit
11 and the DMA controller 12 are shown in Figs. 5 and
6, respectively, to which reference is now made.
As indicated in FIG. 5, the signals HOLD and pHLDA from
the ARBUS are used to generate a signal ~ARBTIME.
/ARBTIME is in the "O" state during the time when
arbitration is to take place among the peripheral
devices competing for a DMA channel. It remains in the
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IBM Docket No. BCg-86-010
"O" state long enough for the signals on the ARBUS to
have reached steady-state conditions, that is, suffi-
ciently long for the arbitration to be completed. To
generate /ARBTIME, pHLDA is inverted by an inverter 61,
then applied together with HOLD to respective inputs of
an EXCLUSIVE-OR gate 62. A one-shot multivibrator 63,
having an output pulse period longer than the arbitra-
tion time on the ARBUS, is triggered by the leading
edge of the output pulse from the EXCLUSIVE-OR gate 62.
The output of the one-shot multivibrator is ORed with
the output of the EXCLUSIVE-OR gate 62 by an OR gate 64
to thu~ produce /ARBrIME. Other arrangements are of
course possible for generating /ARBTIME. In one
approach, DMA request signa~s from each device are ORed
together and the ORed output applied to generate a
pulse signal of appropriate length. The basic require-
ment in any case is to set /ARBTIME to the "O" state to
define the time periods when arbitration is taking
place on the ARBUS.
One compare logic 40 is provided for each ~f the
programmable physical DMA channels in the system, and
one compare logic 49 is provided for each of the fixed
channels. Each compare logic 40 for the programmable
DMA channels (channels O and 4 in the present example)
includes a register 41, referred to as a DMA channel
assignment register, which is loaded by the CPU with a
DMA channel assignment. The compare logics 49, namely,
those for the fixed channels, are identical to the
compare logics 40, except that the register ~0 is
replaced by a set of switches with which the channel
assignment is manually set. Only one each of the
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IBM Docket No. BC9-86-010
compare logics 40 and 49 are shown in detail since the
others ones of the compare logics 40 and 49 are identi-
cal and their input signals are the same.
The outputs from the registers 41 for the programmable
channels (compare logics 40) and the outputs of the
switches for the fixed channels (compare logics 49) are
compared with the signals TMAO - TMA3 by a set of
exclusive-OR gates 42, the outputs o which are applied
to inputs of a NOR gate 43. If a match is present
between the channel assignment and the value represent-
ed by TMAO - TMA3 at the end of the arbitration period,
that is, if the corresponding signals are then in the
identical states, the output from the NOR gate 43
(COMPARE O - COMPARE 7) will be-in the "1" state. Of
course, only one NOR gate 43 at a time can have an
active output.
With reference now to FIG. 6, at the end of the arbi-
tration time when /ARBTIME goes back to the "1" level,
a "1" from the one of the signals COMPARE O - COMPARE 7
in the "l" state will be set in one of the two latches
51 of the DMA contro]ler 12. The other ones of COMPARE
O - COMPARE 7 will be in the "O" state, and hence a "O"
will be set in the corresponding positions in the
latches 51.
The outputs of the latches 51 are applied to corre-
sponding DMA request inputs (DREQO - DREQ3) of two
cascade-connected DMA controller IC s 52. In the
embodiment under discussion, the IC s 52 are each a
type 8237 programmable DMA controller manufactured by
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1~9~6~3
~C9-86-010 12
Intel~ Corporation. The DMA controller IC's 52 are
cascade connected using NOR gates 53. The CPU may be any
of the Intel iAPX 86 series of microprocessors, such as
the 8088, 8086 or 80286. For details of the connections
between the two DMA controller IC's and the CPU,
reference may be made to the 1985 Intel Micro-system
Components Handbook, pages ~-57 to 2-71.
Accordingly, for a peripheral having a dedicated DMA
channel assignment, once the peripheral wins on the
ARBUS, it is guaranteed immediate use of a DMA channel.
For peripheral sharing one of the DMA channels, when it
wins on the ARBUS, it will gain the immediate use of a
DMA channel only if its channel priority assignment
value, as held in its channel priority assignment
register 70, matches one of the DMA channel assignment
values set in one of the two registers 41. Of course,
the BIOS, operating system, or applications program can
continually reprogram the channel assignment values held
in the DMA channel assignment registers 41 of the two
programmable channel compare logics 40 to assure that all
peripherals needing access eventually are given the use
of a DMA channel. Many different programming schemes can
be implemented to control the values stored in the DMA
channel assignment registers 41 and the channel priority
assignment registers 70 of the arbitration circuits
depending upon the application at hand. In a simple
example, the values set in the priority assignment
registers 70 are fixed and the values set in the DMA
channel assignment registers 41 are rotated among at
least some of the values in the priority assignment
registers 70 to thus give each
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IBM Docket No. BC9-86-010
peripheral associated with one of the programmable DMA
channels a chance to gain the use of a DMA channel. If
"intelligent" peripherals are employed having their own
controller, more complex schemes may be implemented.
For example, when a peripheral assigned to a program-
mable DMA channel wishes access, the peripheral can
query the operating system or BIOS as to the availabil-
ity of one of the programmable channels. If a channel
is available, its number can then be set in the regis-
ters 70 and 41 to guarantee access. However, since the
selection of the programming scheme is beyond the scope
of the present invention and in the province of the
user, further examples will not be discussed here.
.
Other applications of the invention are also contem-
plated. For example, programmable DMA channels provid-
ed by the use of the invention can be used as redundant
back-up channels for ones of the dedicated channels,
thereby providing improved system reliability.
It is to be understood that while modifications can be
made to the structures and teachings of the present
invention as described above, such modifications fall
within the spirit and scope of the present invention as
specified in the claims appended hereto.
