Note: Descriptions are shown in the official language in which they were submitted.
~ 130~07 20104-8505
The present invention relates to a system for management
of the priorities of access to a memory, comprising at least one
request generator module provided with means for emitting requests
for access, an arbitration module to arbitrate between the said
requests for access and thus to elect a request for access to be
executed with priority.
Such a system is well known in the data processing
industry, where it frequently occurs that the resources of a
memory are apportioned between a plurality of request generators;
the request generators formulate requests for access which may be
simultaneous, while their execution cannot be so.
Such a system lS used, in particular, in a graphics
system, comprising a dynamic random access memory DRAM storing
pixels.
A known priority logic system is described in French
patent application no. 2,593,304, laid open to public inspection
on July 24, 1987; in such a system, each request generator module
successively emits requests for access, each request for access
having a priority which is unique but variable in time, especially
as a function of the duration of the request as detected by the
said arbitration module.
The arbitration module thus described is complex, both
with regard .o its production, and thus to its cost, and also with
regard to its implementation, since a same request is therein
provided with a variable priority, of which it is not a simple
matter to know the impact on the performance levels of the system.
7~
~ 13 0 9 ~ 07 20104-8505
The object of the present invention is to eliminate this
disadvantage.
To this end, a system for the management of the
priorities is particularly noteworthy ln that each request
generator module is provided with means for separately
- la -
Pl~r ~7.hO9 ~ 1 3 ~ 9 5 7 09 l2-l98~
emitting, on the one hand, the requests for access to a
single ~ord of the said memory and, on the other hand, the
requests for access to a plurality of consecutive words
of the said memory, and that the arbitration module is pro-
vided with means for receiving and arbitrating the said
requests for access ~ith d;stinct prior;ties, even if
they emanate from the same request generator module.
Thus, each type of request is formulated separately
and a priority can be allocated to each type, depending
upon whether what is involved is the type concerned ~ith
a single word or the type csncerned with a plurality of
words. The arbitration module is simpler to construct,
since it no longer includes a block detector as described
in the patent application ~hich has already been mentioned.
The present invention may be implemented advant-
ageously either with priorities which are programmed,
that is to say modifiable during the operation of the
system, or ~ith priorities ~hich are pre-programmed, or
w;red, that is to say non-modifiable during the operation
of the system.
ln the case ~here the priorities are ~ired, it is
thus possible to cause an external clock signal to part-
icipate in arder to automatize the ~anagement of the
priorities~
In a preferred mode, the arbitration module comp-
rises, on the one hand, a first module to arbitrate the
requests for access to a single ~ord and thus to preselect
such a request and, on the other hand, a second module
to arbitrate bet~een the said preselected request and
requests for access to a plurality of ~ords and thus to
elect a request for access to be executed.
Thus, a prearbitration is executed and the second
arbitration module can operate all the faster; this is
favourable in ~he case of the reading in bursts of pixels
to be displayed.
In the case of a DRAM as mentioned above, the
refresh reques~s can advantageously be arbitrated by the
said second module.
~ 1309507
Pl~ 87-609 - 3 - 09-12-1988
The present invention will be better understood
~ith the description of various embodiments which are set
forth ~ith reference to the accompanying drawings.
Figures 1a and 1b represent two modes of implem-
entation.
Figure 2 represents the breakdown of the arbitration
module.
Figure 3 represents the application of the invent-
ion to a graphics system.
Figure 1a represents a priority logic system
similar to that of the patent application already mentioned
and included herein by reference in order to avoid over-
loading the present description.
The essential difference resides in the fact that
each request generator module comprises t~o re~uest con-
nections to formulate, on the one hand, the re~uests for
access to a single word (DP.REQ1, GP.REQ-1, etc...) and,
on the other hand, the requests for access to a plurality
of words, or by blocks (DP.REQ-N,GP.REQN, etc...). If a
module emits only a single type of request, a single
connection is sufficient (CPU-REQ-1~. The priority logic
circuit (CLP) comprises as many reg;sters (REGA, REGB,...
REGI) as there are request inputs; these registers operate
as in the patent application already mentioned but they
are clearly not dissociated and a single priority value
is alLocated to each connection at the input; as previously,
this value can be modified by a command (VAL-REG) even
during the operation of the syste0; depen~ing upon the
priorities, a request to be executed (REQ.EX) is selected
by the system.
In Figure 1b, a similar management system is rep-
resented; the request generator modules csmprise t~o
further connections to formulate seParately each type of
request; on the other hand, the priority logic system
(SL) consists of a system of logic gates which is not
modifiable on account of the fact that it ;s ~ired; the
priorities are therefore fixed once and for all, but it
is possible to act on the gates ~ith a time signal, for
~ i309507
PHF 87.609 _ 4 _ 09-i2-19~8
example the clock tCLK) or, in a preferred mode, ~ith a
time slice s;gnal (TS) ~hich is appropriately chosen;
the TS s;gnal may, for example, represent the display
period and/or the line return period of the screen of a
graphics system; in this case, it is clear to a person
skilled in the art that, following the period in progress,
the various access request generator modules may advant-
ageously be equipped with differing priorities; it is then
a matter for a person skilled in the art to arrange the
logic gates in consequence of his choices of design and
of operation of the system; the TS signal may also rep-
resent, or be combined with, the frame return signal;
these examples of time slicing (TS) arP clearly not lim-
iting.
In Figure 2 the arbitration module has been divided
into two parts.
A first module (SL-PRE) receives and arb;trates
exclusively the requests for access to a s;ngle ~ord to
preselect one of them (REQ-S), which is transm;tted to the
second arb;tration module; the second module (SL.EX) re-
ceives and arbitrates the said preselected re~uest and the
request(s) for access to a plurality of words to elect a
request to be executed; each of the t~o arbitration
modules may independently be either programmable or wired
as mentioned above.
This particular arrangement gives an especially
good performance level in a graph;cs system as shown ;n
Figure 3.
The graphics system comprises, connected to one
another by data, controL and address buses which have been
succinctly represented, a control microcomputer consist-
ing ot a microproce~sor (P) ~ith its programme memory
(~P) for controlling the system, a graphics visual display
screen (CRT), a dynamic random access memory (DRAM) to
store the display information ~ords for the ~indows of
the lines of the screen, ~he said DRAM having to be re-
freshed periodically, and a graphics controller (CT-GRAPH)
comprising a microcomputer interface (INT), a graphics
~ ~30~07
PHF 87.609 ~ 5 ~ 09-12-19B8
processor (MCLP) and screen processor ~DCLP).
The abovementioned first arbitration moduLe is
in this case referred to as bus arbitrator (aUSAR); it
arbitrates the re~uests for a single ~ord (REQ1, REa2,
REQ3) originating from the microcomputer (P), from the
graphics processor (MCLP) and from the screen processor
(DCLP), and it preselects a request (REQ.S).
The abovementioned second arbitration module is,
in this case, integrated in the DRAM controLler (CT.DRAM);
it arbitrates the said request (REQ.S) and the requests
for access in bursts tRAF) to a plurality of words, as
~ell as the refresh requests (REQ-FR) originating from
the screen processor (DCLP), and it elects a request to
be executed (REQ.EX).
The device arranged in this ~ay is ~ell suited to
the process of displaying the p;xels which is dr;ven by
the DCLP; in fact, the said process comprises, on the one
hand, a preparatory reading of a descriptor ~ord (REQ.3)
in ~hich information items which are necessary for the
reading per se of the pixels (RAF) are situated; it is
therefore of imPortance to g;ve a high pr;or;ty to REQ3
during the d;splay per;od, and th;s is possible with the
described device by arranging the bus arbitrator (~USAR)
in accordance ~ith the dPscription of Figure 1b.
The graphics system ;s thus optimized; th;s em-
bodiment ;s not limiting, and a person skilled in the
art may envisage other modes of implementation of the
present invention depending upon the particular cases of
access priority managemene ~hich are presented to him.
