Note: Descriptions are shown in the official language in which they were submitted.
A SWITCHABLE DC POWER SUPPLY WITH INCREASED EFFICIENCY
~OR VSE I~ LARGE WATTAG~ AMPLIFIERS
Back~round of the Invention
..... ~
This invention will rela~e to a means for
increasin~ the e~ficiency of high wattage amplifiers
and will have speclfic applica~tion to a means for
switching power supplies in large wattage amplifiers
between a ~eries and parallel arrangement for increased
efficiency.
In industry, it i5 very often desirable to have
an amplifier oapakle o~ producing a large amount of
output power, generally in the range of several
kilowatts. A good example of a ~ituation where this
power output ls required would be in the field of AM
radio where large amplifiers are used for transmitter
modulators. Another common u~e of such large
amplifiers is as an exoitor ~or vibr~tion or ~hake
tables used to test products against vibration. A
problem associated with such large amplifiers is the
generally poor efficiency of the amplifier wllich
increases the operating and construction cost. A
generally accepted definition of e~ficiency is the
ratio of useful power delivered by a dynamic system to
the power supplied to it. Industry has made several
attempts ~to increase the efficiency of ~n amplifier.
The mo~t popular, however, is the pulse width
modulation technique. In pu18e width modulation, the
amplltude o~ the si~nal to the ampll~ier remain~
2 ~ A~^~
constant with the pulse width varying. The advantage
of pulse width modulation i~ that ~ince the si~nal is
of a con~tant amplitude the transistor~ used can
function between cut off and saturation, thereby,
increasing the efficiency of the amplifier by reducing
the power dissipated in the system. To lncrease the
efficiency of the amplifier further by reduein~ the
amount of power that must be dissipated in the form of
heat, it is typical to use a center tapped DC power
supply with a complementary pair of pul~e width
modulated ~witches connected between the positive and
negative voltacJe supplie5 and a load which is connectecl
to the center tap. A problem associated with this i5
that in order to insure the maximum sharing an~
efficiency between the set of pulse width modulated
switches, the components within the switches must be
care~ully and accurately selected and matched. If one
sw~tch is not speed matched to its complementary switch
then a current will be generated which will pass
through both switches and the efficiency of the sy~tem
wlll drop.
Summary o~ the In~ention
In this invention, ~he problems associated with
previous attempts to increase a~plifier efficiency are
eliminated by u~ing a power supply whlch has multiple
DC outputs that may be switched from parallel to serie~
in response to the output o~ the amplifl~r ~ecoming too
large a~ compared with volta~e of one o~ the ~C outputs
of the power supply. Upon the amplifier voltage
falling below the predetermined maximum, the DC output~
are switched back to parallel to improve cooling and
heat dis~ipation of the ampliPier power supply thereby
making the amplifier and power 9upply more cost and
energy efficient. An ancillary be~e~Fit of this
invention is that since the power 5Upply iS more
efficient a smaller wattage power supply may be used to
power the amplifier thus reducing cost fu;rther.
Accordingly, it is an object of this invention to
provide for an increased efficiency amplifier power
5upply design.
Another object of this invention i5 to provide a
means ~or switching voltage sources be-tween a series
and parallel condition.
Other objects of this invention will become
ohvious upo~ a reading of the following description.
Description of the Drawin~s
Fig. 1 i5 a schematic representation of the
switchable power supp1y of this invention.
Fig. 2 is a schematic representation of a second
embodiment of a switchable power supply.
Fig. 3 is a schematic representa-tion of the
switchable power supply connected to an amplifier
circuit.
Fig. 4 is a schematic repre~entation of a further
embodiment o~ the switchable power ~upply having a
comparator and tr~g~ering circuits.
Brie~ Descrl~tion_o~ the Invention
The preferred embodiment herein described is not
intended to be exhaustive or to li~lit the invention to
the preci~e ~orm disclosed. I-t :i5 cho3en anc1 described
to explain the principles o~ the in~vention and its
application and practical use to enable others skilled
in ~he art to utilize the invention.
Fig. l depict~ a switchable DC power supply
circuit l which has DC voltage source~ 4 and 5 and
diodes 6 and 7 interconnected between output terminals
2 and 3. DC voltage source 4 is connected at its
negative voltage terminal to negative output terminal 3
of DC power supply circuit l. Diode 7 has its anode
connected to the positive terminal of voltage source ~
and its cathode to the positive terminal of volt~ge
source ~ and to positive output terminal 2 of DC power
supply circuit l. Diode 6 is connected at its cathode
to the negative terminal o voltaga source 5 and at its
anode to the ne~ative terminal of voltage source 4. An
electrlcal or mechanical switch 8 is connected between
the anode of diode 7 and the cathode of diode 6.
In use with switch 8 open DC voltaye sources ~
and 5 are connected in parallel and the volta~e at
~erminals 2 and 3 i~ equal to the volta~e o one source
4 or 5 (as~uming both are equal), When switch 8 is
closed, voltage sources 4 and 5 are placed in series
between ter~inals 2 and 3 with the positive terminal of
voltage source 4 connected throu~h 5Wi tch 8 to the
~ A.
negative voltage terminal of voltage source 5.
As can be seen in Fig. 2 any multiple of voltage
sources can be switched by addirlg two diodes and a
switch for each additional voltage ~ource, The
circuit~ of Fi~. 1 and Fi~. 2 u~e a common numbering
scheme with numbers primed in Fig. 2 to denote common
function or purpose. In addition to co~lponents
mentioned in the desoription of Fig. 1, the switchable
power source 1' ~hown in Fig. ~ inoludes DC voltage
source 9 connected in parallel with DC voltage source
5'. Diode 10 is connected between the positive voltage
terminals of voltage sources 5' and 9 with its cathode
connected to voltage source 9 and positive voltage
output terminal 2'. Diode 11 i6 connec~ed between the
~: negative voltage ter~inals of voltage source 5' and 9
with its cathode connected to voltage source 9. A
second electrical or mechanical switch 12 i5 connected
between the anode of diode 10 ~nd the cathode of diode
11 .
In use, if switches 8' and 12 a~e open the
voltage available at terminals 2' and 3' i5 equal tv
the parallel value of voltage sources 4', 5' and g. If
switch 8' is closed and 12 remains open then the
voltage available at ter~inals 2' and 3' is e~ual to
the parallel voltage of sources 5' and 9 in series with
the voltage of source 4'. I~ switch 8' is open and
switch 12 î~ clo,~ed, source 9 will be in serie~ with
the parallel combination o~ source~ 4' ancl 5'. When
6 ~ 3 ~
both switches 8' and 12 are closed source~ ~', 5' and
g are in series and the voltaye at terminals 2' and 3'
is equal to the sources collective value.
An amplifier shown in block form in Fig, 3
includes two amplifiers A1 and A2 driviny four
transis-tors T1-T4 which are connected in a `oridge
confi.guration having output terminal6 40 and 34
connected to a load. The amplifier circuit depicted is
known in industry and is included merely to illustrate
the interconnection of the switching circuit 18
(described below) and amplifier circuitry. As such the
amplifier does not constitute a point of novelty of
this invention.
Fig. 4 illustrate an application of the
previous switchable power supply 1 where switch 8 of
Fig. 1 is replaced by switchiny circuit 18.
Transformer 39 having pri.mary windings 31 connected to
a three phase external power source not shown also
includes secondary windings which have filtering and
rectifying devices to form DC power supplies 14 and 16.
DC supply 16 is connected to a switching circuit 18 to
provide supply and reference voltayes to the components
o~ circuit 18. ~witching circuit 18 includes as main
components comparators 20 and 22. Zener diodes 2~ and
26 are connected in series along with current limiting
resistor 29 between the positi.ve voltage terminal 17
and negative voltage terminal 15 of DC supply 1~ to
provide a set point for comparators 20 anfl 22. A
_~ !
7 ~ ~ q /~
vol~age divider i5 provided by connecting resistor~ 2B
and 30 in series between positive terminal 17 and
junction 25 of zener diodes 24 and 26. The junction of
resistQrs 28 and 30 is connected to non-invertin~ inpu'c
terminal 19 of comparator 20 to provide a reference
voltaye at termlnal 19. ~e~istor 32 is connected
between terminal 19 of comparator 20 and the ground 34
of an amplifier circuit (shown in Fig. 3). Resistor 35
and 36 are connected in series between junction 25 and
negative voltage terminal 15 to Porm a voltage divider
with the junction of resistor~ 35 and 36 being
connected to inverting input terminal 21 of comparator
20. Resi~tor 37 is connected be~ween ~he output
terminal 4~ of an amplifier circuit (Fig. 3) and
inverting input terminal 21 of comparator 20. 0utput
terminal 42 of comparator 20 i5 connected to trig~er
input 46 of timer 44. A resistor network is connected
to ~omparator 22 which ~ubstantiall~ mirrors the
network connected to comparator 20. Resistors 48 and
50 are connected in series between junction 25 of zener
diodes 24 and 26 and the negative voltage terminal 15
of DC supply 16. The junction of resistors 48 and 50
i9 connected to the inverting input terminal 2~ of
comparator 22.
Re~istor 52 i5 connected between inverting input
2~ of comparator 22 and ground 34 of the amplifier
circuit shown in Fig. 2. Resistors 54 and 56 are
connected in serie~ to form a voltage divider between
junc~ion 25 and positive voltage terminal 17 of DC
supply 16, with the ~unction oP resistor 54 and 56
being tied to non-inverting input 23 of comparator 22.
A resistor 58 is connected between pos,itive output 40
of an amplifier circuit and non-inverting input 23 of
comparator 22. Output 60 of comparator 22 i~ connected
to trigger input 46 of Monostable o~ one shot timer 44.
The resistor networks that in'cerconnect
comparators 20 and 22 to amplifier output 40 and
positive and negative voltage terminals 17 and 15 of DC
supply 16 have been chosen ~o as to make each
comparator di~ferentially receive the output voltage of
the amplifier and the DC supply voltage. Resistors
connected in a like fashion to each comparator will
have an approximately e~ual value. Therefore,
referring to Fig. 3 resistors 28, 35, 48 and 54 will
have an equal or approximately equal value as will
resistors 30, 36, 50 and 56 as will 32, 37, 52 and 5~.
Implementing equi~alent resistance values allows
comparat~r~ 20 and 22 to change output states at the
same voltage ratio on alternative half cycles.
It should be noted that comparators 20 and 22 are
paired components in a single integrated circuit chip
and, therePore, share a common voltage su~ply between
terminal 62 connected through resistor 29 to the
positiv~ voltage terminal 17 and input terminal 64 to
negative voltage terminal 15 of ~C supply 16.
The circuitry which provides support and proper
~ s~ 3
biasing for monostable or one-shot timer 44 includes
resistor 66 and capacitor 68 connected in ~eries
between junction 70 and negative voltage terminal 15 of
DC supply 16. The junctlon oi componen~ 66 and 68 is
connected to the threshold input terminal 72 and
trigger input 46 of timer 44. A positive voltage is
supplied to timer 4~ by connectin~ pin 74 to positive
voltage terminal 17 via resistor 29. Ground pin 76 is
connected to the negative voltage terminal 15.
Capacitor 7a l~ connected between input 80 of timer 44
and negative voltage terminal 15. Resistor 84 i5
connec~ed between junction 70 ~nd reset pin 82 of ti~er
44 with capacitor 86 and resistor 88 connected between
reset pin 82 and negative terminal 15 to force a low
volta~e on output pin 92 upon initial power being
supplied to the circuit until capacitor 86 fully
charges. Supply by-pa~.s capacitor 90 i9 connected
between junction 70 and negative voltage terminal 15.
Output pin g2 of timer 44 i5 connected by current
limiting resistor 94 to gate 96 of field effect
transistor 100 (hereinafter referred to as FET lOQ~.
Drain 104 of FET 100 is connected to positive voltage
terminal 11 of DC supply 14 and to the anode of diode
110. The source lead 106 oP FET 100 is connected to
the cathQde of diode 108 and to negative voltage
terminal 15 of DC supply 16. The cathode o~ diode 110
i8 connected to po~itive volta~e terminal 17 of DC
supply 16. Th~ anode of diode 108 is connected to
1 0 ~ 3 ~ r
negative ~oltage terminal 13 of DC 5upply 14 .
The switching circuitry o~ this invention
improves the efficiency of arl amplifier power supply by
switching DC supplie~ 14 and 16 ~rom parallel to serie~
arrangement in response to the amplifier exceeding a
predetermined maximum output voltage. The
predetermined ma~imum i5 a ratio of the ampllfier
voltage relative to the volta~e across DC 5upplV 16 and
i5 determined by the supportin~ resiQtor networks
connected to comparator~ 20 and 22 previou~ly
described. Initially, DC supplies 14 and 16 are
connected in parallel, outputs 42 and 60 of comparators
20 and 22 are at a high voltage level and, therefore,
do not trigger timer 44. Further, upon initialization
capacitor 86 begins to charge thus placing ~ low
voltage on output pin 92 and, thereby, maintaining FET
100 off and DC supplies 14 and 16 in parallel. Vpon
the output signal from the amplifier at terminal 4~
exceeding the predetermined ratio even moment~rily
dur~ng the positive half cycle, comparator 20 will
produce a la~ vol-tage level at output 42 thus
triggering timer 44 to to~gle its output at pin 92 from
a low voltage to a high volta~e level. In a like
fashion, if t~e output o the amplifier monitored at
pin 40 1~ greater than the predetermined ratio during
the negative half cycle, comparator 22 produce~ a low
output at pin 60 which also tri~ger~ timer 44 into
toggling it~ output at pin 92 ~rom a low voltaye to a
A ~
high voltage level. In this manner, if the amplifier
output at pin 40 exceeds the predeterlnined ratio either
in the positive or negative half cycle, timer 44 will
be triggered.
When timer 44 triggers, a logical level high
occurs at output pin 92 o~ timer ~4 which causes FET
100 to turn on and create a current path which
electrically places DC supply 14 and DC supply 16 in
series. If the amplifier output signal at pin 40 is
within normal limits i.e. lower than the predetermined
ratio comparators 20 and 22 will not trigger timer 44
and, therefore, the output at pin 92 will be low which
maintains FET 100 in the off condition. ~hen FET 100
i5 off DC supplies 14 and 16 are connected in parallel
thro~lgh diodes 108 and 110 thus reducing the amou~t of
power required to be dissipated hy any one sin~le
supply. The stable state for timer 44 is to produce a
low at output pin 92 and, therefore, FET 100 is
normally off or non-corlduct;ve an~ ~C supplies 14 and
16 are normally in parallel. Monostable or one-shot
timer 44 functions in switching circuit 18 to provide
hysterisis to the s~itching of DC supplies 14 and 15.
Timer 44 also set~ the maximum fre~uency at which
switchin~ circuit 18 will switch DC supplies 14 and 16.
Upon being initially triggered by either col~parator 20
or 22, timer 44 will produce a high at pin 92 for a
predetermined period of time.
12
If a second or multiple trigger signal~ are rcceived
during the predetermined period of time that timer ~4
i5 producing a high at output pin 92, timer 44 will
retrigger and FET .lO0 will remain on. There~ore, the
maximum frequency switchable is inversely proportionate
to the predetermined period of time that timer 44
produces a high output at pin 92 in response to being
triggered. If hysterisis or a maximum switching
frequency is not desired, timer 44 could be omitted and
lo comparators 20 and 22 could be configured in a Schmid~
trigger arrangement to adequately drive the switch
transistor.
It is ~o be under~tood that the invention i5 not
limited to the details above described but may be
modified within the scope of the appended claims.
