Note: Descriptions are shown in the official language in which they were submitted.
1327991
HIGH FREQUEl`lCY BALLAST FO~ GASEOUS DISCHPE~GE~ L.Z~MPS
Background and Summary of the Invention
The present invention relates to circuits for
energizing gaseous discharge lamps such as fluorescent lamps
or high intensity discharge lamps. More particularly, it
re]ates to a ballast using solid state switches and adapted
to energize the lamps with high frequency current. ~allast
circuits of this type are normally designed to receive energy
- from a conventional 60 Hz, cycle as is commonly available,
and by means of frequency inversion, generate a hiyher
frequency signal (in the range of 25-100 KHz.) to energize
I the lamps. I
The advantages of high-frequency lamp excitation
such as more efficient conversion of electrical energy to
light output are well-known. However, in the past, and
despite the generally accepted principle that high frequency
;j excitation is more efficient, there have been many attempts
at high frequency ballasts, but few have met with co~Mercial
success. Even those high frequency ballasts which have been
commercially produced have one or more disadvantages to them.
, Another important factor in evaluating high
frequency ballast circuits is the effect that the excitation
I current has on lamp life. With the rise in energy costs,
¦ both ballast manufacturers and lamp manufacturers have, in
the last few years, given increased attention to high
~ frequency excitation. Lamp manufacturers haYe concluded
l that lamp life may seriously be diminished if the crest
i factor of the excitation current is not maintained within
certain limits.
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1327991
When, for example, fluorescent lamps were energized
by magnetic ballasts at 60 Hz., the crest factor for lamp -
current (which is defined as the ratio of peak current to
RMS current1 was approximately l.41 because 60 Hz. voltage
is sinusoidal.
As lamp manufacturers designed lamps for operation
at high frequencies, it became clear that the crest factor
of lamp current must be maintained within a desired range.
It is believed that the heating effect of lamp current is
sufficient to heat the cathode of the lamp (in fluorescent
lamps) to the point where it is capable of emitting l.7 times
the RMS current. Circuits which exceed a crest factor of
1.7 necessarily exceed the thermionic emission capability
of the cathode, and this results in sputtering of the cathode
; material and shortening lamp life.
Thus, the requirement for achieving a desirable
crest factor in high frequency excitation of fluorescent
lamps has become an important criteria if a ballast is to
~; receive commercial acceptance~ A desired crest factor can
be obtained simply by using large inductors and capacitors
; to filter the line voltage, but the power requirements of
I these components make them expensive and somewhat bulky,
;I despite operation at higher frequencies.
The preferred embodiment of the present invention,
thus, is d~rected to a high frequency inverter ballast for
gaseous discharge lamps which achieves a desired crest factor
for lamp current with a relatively simple and inexpensive
circuit which does not require magnetic components for
sensing the lamp current, yet which has many of the desirable
characteristics of other solid state ballast circuits.
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~ 1327991
Summar~ of the Invention
The present invention uses first and second power
switches which are operated sequentially and mutually exclu-
sively to cause current to flow in the primary winding of
a power transformer when conducting. The lamp circuit is
connected in the secondary of the power transformer.
Current is regulated in the primary by sensing
the current through the power switches and turning off the
conducting switch when the sensed current reaches a pre-
10 determined value, thereafter turning on the complementary
` power switch, causing current to flow in the opposite
` polarity in the secondary of the power transformer. We refer
to this as "current mode" operation or regulation. As will
be shown, current mode regulation may be employed in various
circuit configurations, but the principal advantage is that
it maintains the peak amplitude of transformer primary
current (and consequently secondary current as well) -
substantially constant.
The B+ voltage for the inverter circuit is ~erived
20 from a conventional 60 Hz. source which is full-wave
rectified and from a make-up source which supplies a minimum
;, voltage during periods when the full-wave rectified voltage
~ would otherwise reduce to zero. Make-up power is supplied
¦ from a capacitor which is charged during voltage peaks.
;l In a preferred embodiment, the power switches are
connected in a push-pull circuit arrangement and operated
3 in current mode regulation. As the B+ voltage increases,
the frequency of operation of the power switches (and thus,
the frequency of the lamp current) is also increased. Corre-
30 spondingly, when the Bf voltage goes lower, the frequency
;J 3
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1327991
,,
of operation decreases. However, the maximum current flowing
in the switches remains constant.
The load circuit is designed such that its
impedance increases with frequency. When the B+ voltage
is at a higher value, the frequency of operation is also
higher, and the impedance of the load is greater at the
higher frequency. Conversely, when the source voltage is
at a lower value the inverter operating frequency is lower
and the load impedance is lower. This has the effect of
10 equalizing lamp current and maintaining the peak value of
: load current at a substantially constant value even though
the B+ voltage varies considerably from its peak value to
the value of the make-up voltage (which is one-half the peak
voltage). A desirable crest factor for lamp current is
thereby achieved.
; Another feature of the present invention is a
circuit provision wherein as power is drawn from the B~
source to be stored in the make-up voltage supply, a signal
is generated which increases the current flowing in the po~er
20 switches so as not to diminish the actual lamp current during
periods when energy is being tapped from the primary source
and stored in the make-up voltage source.
I A minimum fre~uency oscillator is also incorporated
; in the circuit so that in the case normal operation is
interrupted for any reason, the minimum frequency oscillator
becomes actuated and drives the power switches at a minimum
frequency (which, advantageously, is a function of the
magnitude of the B~ voltage also). The minimum frequency
, oscillator is reset and re-synchronized with the operation
of the inverter s~itches during each half cycle of normal
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1327991
operation so it does not drive the inverter switches during
- normal operation.
An alternate embodiment is disclosed in which the
power switches are connected in a half-bridge circuit con-
figuration with the primary of the power transformer con-
nected in the diagonal of the bridge. This configuration
permits the use of power switches with lower voltage ratings
and may, therefore, reduce overall cost.
Other features and advantages of the present
invention will be apparent to persons skilled in the art
' from the following detailed description of a preferred
embodiment accompanied by the drawing wherein identical
reference numerals will refer to like parts in the various
views.
J' 8rief Description of the Drawing
FIG. 1 is a circuit schematic diagram of a ballast
, circuit incorporating the present invention with portions
i in functional block form;
FIG. 2 is an idealized voltage timing diagram
illustrating operation of the system of FIG. l;
FIGS. 3 and-4 also illustrate voltage waveforms
which assist in understanding the oPeration of the circuit
of FIG. l; and
FIG. 5 is a functional block schematic diagram
of an alternate circuit incorporating the present invention.
Detailed Description
Referring first to FIG. 1, and before describing
the individual circuit components in detail, an overall
description of the principal components and their operation
, .
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13279~1
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"
will be given. Input electrical power is received from a
conventional source, such as a 60 Hz, 115 v. or 220 v. power
line and coupled to input terminals 10. The input power
is fed to a full-wave rectifier bridge circuit generally
designated 12, the output of which is fed to an input
terminal 13 of a power transformer generally designated 15.
` Terminal 13 may be a center tap of first and second primary
~, ~7indings designated 16, 17 respectively, as illustrated.
If the only voltage fed to the terminal 13 (called
the B+ or source voltage) were a full-wave rectified sinu-
soidal voltage, then the voltage at the terminal 13 would
vary from a maximum or peak down to zero and then back to
the peak with the same polarity. In order to prevent the
voltage from going to zero ~which would mean that the lamps
would not be energized during the period when the input
voltage is less than a minimum operating threshold value),
a make-up voltage supply generally designated by reference
numeral 20 stores power during peaks of the B+ voltage and
couples it along a line 21 to the terminal 13 of the power
transformer 15 during periods when the voltage falls below
a predetermined value of the B+ source. These periods are
sometimes referred to as inter-cusp periods.
Thus, the a+ voltage at terminal 13 is a full-wave
rectified sinusoidal voltage which does not diminish below
a predetermined, fixed minimum level. That minimum level
preferably is approximately one-half the peak voltage, is
seen in idealized form in FIG. 2, line Ll and generally
dèsignated by reference numeral 25.
Returning to FIG. 1, a power inverter circuit
generally designated 28 includes first and second semi-
` 1327991
:
- conductor switches 30, 31 which, as illustrated, may be
N-channel, enhancement mode MOSFET's such as are commercially
available under the designation IRF 730 from General Electric
Co. or RCA, Inc. The power switches 30, 31 are turned "on"
(i.e., switched to a conducting state) when a positive level-
voltage is fed to the gate input lead. When that level is
removed, the associated power switch is turned "off" (i.e.,
non-conducting).
Power switches 30, 31 (sometimes referred to as
"inverter switches") are connected in series with series-
connected primary windings 16, 17. The junction between
power switches 30, 31 is designated 32 and connected to
ground through a current-sensing resistor 33.
The power transformer includes a secondary winding
generally designated 34 which is coupled to a lamp circuit
generally designated 35 and including at least one gaseous
discharge lamp such as a fluorescent lamp, seen at 36. In
this case, a second lamp 37 is included in the lamp circuit.
Persons slcilled in the art will readily appreciate that the
: 20 illustrated circuit, once it is understood, may be employed
to energize and operate other lamp circuit configurations
or d i f f erent gaseous discharge lamps, such as so-called High
Intensity Discharge ~HID) lamps.
Also included in the lamp circuit 35 is a passive
reactance element, in this case an inductor 38 (which may
be the leakage inductance of the power transformer) is
illustrated schematically as connected in series with the
lamps and transformer secondary so that any current flowing
in the lamps 36, 37 also flows in the inductor 38. Logic
circuitry generally designated by reference numeral 40
~ " , . . , . ~. , : ,
13279~1
; controls the state of power switches 30, 31 in current mode
control, and it also provides a suitable turn-off voltage
` and timing sequence for applying the control voltages for
the power switches.
3 A first comparator circuit 42 senses the voltage
at junction 32 which is a signal representative of the
current flowing in whichever of the power switches 30, 31
is conducting at any given time. Comparator 42 senses the
signal on its negative or inverting input lead and compares
it with a fixed reference voltage VsT PT (standing for a
"set point" voltage) and generates an output signal when
the sensed "current" signal (actually a voltage representa-
tion of current) reaches a predetermined value determined
by the set point voltage.
The logic circuit 40 includes a flip-flop circuit
43 which changes its output state each time a positive-going
signal appears at its clock input, C. The output signals
of the flip-flop 43 are coupled through gating circuitry
I to be described for turning the inverter power switches 30,
1 20 31 on and off in mutually exclusive time periods so that
they operate in "push-pull" fashion with only one semi-
I conductor switch conducting at any given time.
~i A brief description of the operation of the
circuitry described above will now be given with the object
of explaining a principal feature of the system, namely,
achieving high frequency, uninterrupted excitation of the
lamps using a 60 Hz. line source while regulating lamp
current. If the lamp current were a pure sinusoid of constant
peak amplitude, a crest factor of approximately 1.41 would
be obtained.
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1327931
The low frequency supply voltage is derived from
the input line voltage connected to the source lines 10 and
rectified by bridge circuit 12. It is fed to the input
terminal 13 of the primary winding 15 of the power trans-
former. As mentioned, the voltage appearing at the junction
13 from output of the bridge rectifier circuit 12 would be
a full-wave rectified voltage, but it is modified by power
fed from the make-up power source 20 coupled from the winding
19 of the transformer 15 and storing energy in a capacitor
to be described which is then coupled back to the junction
13 of the power transformer during periods when the output
voltage of the bridge circuit 12 is reduced below a pre-
determined level. Referring to line L-l of FIG. 2, the solid
line generally designated 25 represents the B+ voltage
appearing at the junction 13. Each cycle of the B+ voltage
includes a portion of a sinusoidal wave form such as is
designated 44a which increases to a peak and then reduces,
and a fixed DC minimum level represented by the horizontal
.
' line 44b. During those intercusp periods when the sinusoidal
j 20 voltage would ordinarily reduce to zero volts as indicated
by the dashed line between the peaks ~or cusps) of the sinu-
soidal input voltage, the make-up voltage source 20 supplies
' a DC level to sustain inverter operation.
Assuming operation during steady state, and, for
, a moment, ignoring the effect of the amplitude variation
of the input voltage just discussed, it will be assumed that
power switch 30 has just been turned on. A current will
flow in the direction of arrow Il through the primary winding
17 of the transformer 15, the power switch 30, and the
current-sensing resistor 33 to ground.
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1327931
; At this time, power switch 31 is non-conducting,
and a voltage will appear at the secondary winding 34 of
the power transformer to energize the lamp load circuit.
The current Il builds up generally linearly because of the
inductive reactance in the circuit, so the voltage at the
junction 32 increases in accordance with, and is represen-
- tative of, the current flowing in the power switch 30. It
is also representative of the current flowing in the lamp
circuit, as persons s~illed in the art will appreciate.
The voltage at junction 32 is coupled to the
negative (or inverting) input of comparator 42. When that
signal exceeds the set point voltage VST PT which is fed
to the positive (or non-inverting) input of comparator 42,
` the comparator 42 will switch states. The output signal,
in turn, is fed to the logic circuitry 40 and causes the
` flip-flop circuit 43 to change its output state, thereby
turning off the power switch 30, and very shortly thereafter,
turning on power switch 31, causing a similar current to
flow in the primary winding 16 of the power transformer as
indicated by the arrow I2 in FIG. 1.
In order to explain the effect of the variation
in amplitude of the B~ voltage, reference is made to FIG. 3.
~¦ Since the current increases in the sensing resistor 33 at
! the initial portion of an exponential increase, it can be
considered to be substantially linear. If the voltage (or
current) is rising to one level (for example, the level V
in FIG. 3), the voltage will be a line as seen at 46 in
FIG. 3. If, however, the voltage is rising toward a second,
higher level, such as that designated at V2 in FIG. 3, then
the voltage will increase as representated by line 47.
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1327391
Assuming that each of the voltages 46, 47 is then terminated
at a fixed level V0 which is lower than the levels Vl and
V2, voltage 46 will reach the level V0 in time t5, whereas
voltage 47 will reach level V0 at time t4, which is shorter
than time t5. Thus, as the instantaneous voltage at input
junction 13 gets greater, the resulting current slope (either
Ilor I2) will increase, and the voltage at junction 32 will
rise faster. Correspondingly, as the magnitude of the B+
voltage at junction 13 decreases, the voltage at junction
32 will have a correspondingly slower rise time, and will
reach a fixed voltage in a slightly longer time. Thus, as
the B+ voltage increases, the frequency of the inverter
current will increase and as the B+ voltage decreases, the
frequency of the inverter current will decrease. However,
because the inverter switches are operated in current mode
control, the peak value of inverter current will be constant
and thus regulated, even though its frequency varies
monotonically with the magnitude of the B+ voltage.
In terms of the operation of the circuitry thus
far described, when the voltage at the input junction 13
is relatively high, such as at time tl in line L-l of FIG. 2
(corresponding to a peak of the sinusoidal input voltage),
the voltage at junction 32 will rise toward the level VsT PT
more rapidly, and the comparator 42 will switch states more
rapi~ly than when the input voltage is lower, such as at
time t2 on line L-l of FIG. 2. Similarly, the time taken
for the voltage 32 to rise to the level Vs,r PT will be even
longer when the voltage at the input junction 13 is derived
solely from the make-up supply 20, such as at t3 in line
L-l of FIG. 2. In all cases, however, the power switches
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1327991
:
reverse states when the current following in the switch then
conducting reaches a predetermined value as represented by
., .
Referring now to line L-3 of FIG. 2, there are
shown three sets of ramp waveforms designated respectively
48, 49 and 50 and depicting, in idealized form, the voltage
at junction 32 at times tl, t2 and t3 on line L-l of FIG. 2.
The first ramp of each of the sets of ramps 48, 49 and 50
represents the voltage at junction 32 during the time when
power switch 30 is conducting, and the subsequent ramp of
each set indicates the corresponding voltage at the time
. when power switch 31 is conducting. The resulting
voltage waveform on the secondary of the p~wer transformer
is seen on line L-2 of FIG. 2. This waveform has also been
drawn in idealized form to illustrate the principle involved
rather than to try to depict accurately the exact frequencies
or voltages, as is customary.
In summary, when the source voltage is relatively
high, the frequency of the current in the primary winding
(and thus the secondary winding), of the power transformer
15 is at a relative high frequency; and when the input source
, voltage is relatively low, the frequency of the load current
`~ is relatively low. On the other hand, when the frequency
af the load current is high, the impedance of inductoc 38
is proportionately greater; and when the frequency of the
lamp current is relatively low, the impedance offered by
the inductor 38 is correspondingly low. Thus, the overall
effect is to maintain the peak value of lamp current
substantially constant.
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1327991
The resulting load current, as seen in line L-4
of FIG. 2, has a peak amplitude which is substantially
constant, although the frequency of the load current varies
from a minimum frequency during time t3, to approximately
twice the minimum frequency at time tl, when the B+ voltage ~-
is at a maximum. In both cases, however, the excitation
frequency of the lamp is in the range of 30 KHz-75 KHz,
thereby achieving the benefits of high frequency excitation,
but the crest factor of the lamp current is maintained in
a desired range, as discussed more fully below. Further,
current regulation and improved crest factor are achieved
without sensing lamp current in the secondary of the
transformer 15 ~which requires inductive sensors such as
` current transformers) thereby minimizing bulk, cost and
quality assurance restrictions. These features are achieved
with an uncomplicated current mode push-pull inverter circuit
with a reliable yet inexpensive circuit arrangement requiring
no special magnetic circuit elements, such as might be
required if the cur~ent ~ere sensed in the secondary of the
power transformer.
The circuit shown in FIG. 1 will now be described
in more detail. The input section includes a fuse 52 in
one of the lines 10 for system protection, a metal oxide
varistor (MOV) over-voltage protection device 53 for protec-
tion against transient excursions of the input voltage, an
electromagnetic interference filter circuit generally
designated 54 and including series inductors L1 and L2 and
shunt capacitors Cl and C2 in each input line, and the pre-
viously identified bridge rectifier circuit 12. The filter
circuit not only prevents electromagnetic interference
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1327991
. .
; generated in the circuit from being coupled to the power
lines, but it isolates the inverter switches from any high
frequency transients on the input power lines. A high
frequency bypass capacitor 55 is also coupled between the
output of the bridge circuit 12 and ground.
Low voltage for the logic circuitry is derived
~'~ from the output of the bridge circuit 12 through a resistor
56 to a zener diode 57. A filter capacitor 58 and a high
frequency bypass capacitor 59 are connected across the diode
57, the low voltage source being designated Vcc. The voltage
1 Vcc for the logic supply is less than the output voltage
- of the bridge circuit 12. This voltage difference can be
achieved economically by a voltage drop across a series
~; resistor (i.e., resistor 56) in the illustrated embodiment
~ without substantially reducing operating efficiency and
¦ without more costly components because arranging the power
i~ switches in a current mode control, push-pull configuration
requires less logic circuit~y and, therefore, less power
than many alternative designs.
Turning now to the power inverter circuit 28, for
the most part it has already been described. However, each
of the power switches 30, 31 has a "snubber" circuit 60 con-
nected across its power terminals for protecting the devices
against high frequency transient signals.
Turning now to the make-up voltage source, winding
19 of transformer 15 couples power fed from the source lines
10 to a second bridge rectifier circuit 61, the output of
which is connected to a storage capacitor 62. The other
output terminal of the bridge c1rcuit 61 is connected through
a resistor 63 to ground; and a high frequency by-pass
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1327991
capacitor 64 is connected across the storage capacitor 62.
A diode 65 couples the make-up voltage source to the input -
terminal 13 of the power transformer.
The previously described input signai to comparator
42 from the junction 32 is coupled through a resistor 67; and
a capacitor 68 is connected between the negative input
terminal of comparator 42 and ground and serves as a high
frequency shunt. Additional signals are coupled to the nega-
tive input terminal of comparator 42 from the source voltage
at junction 13 through resistor 69 and from the signal
developed across resistor 63 through a resistor 70. The
functions of these two signals will be described below.
Turning now to the logic circuitry 40, the
flip-flop 43 is a "D" type flip-flop, having a data input
designated D and a clock input designated C. The Q output
of flip-flop 43 is coupled through a NAND gate 72 and an
1 inverter 73 to the gate lead of power switch 30. The Q
' output of flip-flop 43 is coupled through a NAN~ gate 74
and an inverter 75 to the gate input of power switch 31.
The Q output of flip-flop 43 is also connected to the data
input D. The output of comparator 42 is connected through
an inverter 76 to the clock input C of the flip-flop 43.
Turning now to the upper left-hand portion of FIG.
1, an initialization (or start-up) circuit generally desig-
nated 80 senses input voltage and inhibits operation of the
logic circuit 40 until the input voltage level has rèached
a predetermined threshold, as during start up. The circuit
includes a comparator 81 having its positive (non-inverting)
input connected to a voltage divider circuit comprising
30 resistors 82, 83 connected between the low voltage source
~j
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: 1327~1
Vcc and ground. The output of comparator 81 is connected
through a diode 84 to a junction designated 85 which is the
input to the inverter 76 described above. A resistor 86
is connected between the source Vcc and the junction 85.
A resistor 87 is connected between the low voltage source
and the output of comparator 81, and a resistor 88 is
connected between the positive input and the output of the
comparator 81. The resistors 87, 88 provide positive feed-
back to the input of comparator 81 so that once it is
switched it will remain switched unless the input voltage
diminlshes appreciably as will be understood. This
hysteresis effect of the start-up circuit prevents undesired
switching of the logic enable circuit when the source voltage
is passing through the threshold for operation.
A resistor 90 is connected between the low voltage
source and a zener diode 91. The voltage developed across
the diode 91 is coupled directly to the negative input of
comparator 81.
The function of the initialization circuit 80 is
to inhibit operation of the power switches until the low
voltage source has stabilized when the circuit is initially
energized. Resistors 82 and 83 form a voltage divider
network which is designed such that the voltage fed to the
non-inverting input of comparator 81 is less than the refer-
ence voltage across diode 91 until the diode conducts and
clamps the voltage at the non-inverting input of comparator
81 which by design does not occur until Vcc has nearly
reached its desired value. During this initialization
period, the output of the comparator 81 is clamped to ground,
thereby holding the voltage at junction 85 at a low level
.
13279~1
through diode 84. The junction 85 is also connected to
inputs of the NAND gates 72, 74, and serves as an "enable"
signal. When the output of the comparator 81 is relatively
low, the gates 72, 74 are disabled, so that the power
switches cannot conduct. A positive or relatively high
signal is required on the gate lead of a power switch to
4 cause it to conduct.
A minimum frequency oscillator generally desi~nated
95 is set at a frequency below the normal operating range
10 and does not affect the operation of the circuit unless the
operating frequency of the push-pull inverter falls below
the design range or stops operating altogether. In such
a case, the minimum frequency oscillator serves to operate
the inverter at a minimum frequency which preferrably varies
with the magnitude of the input supply voltage B+.
The minimum frequency oscillator 95 includes a
~ capacitor 96 having one terminal grounded and the other
j terminal connected to the low voltage power source through
1 a diode deslgnated 99 of a reverse polarity, and it is also
connected to the B+ voltage through a resistor 100. The
positive terminal of capacitor 96 is also connected through
a resistor 101 to the output of a comparator circuit 102.
A comparator circuit 103 has its positive input connected
to the previously described reference voltage generated
across the diode 91 (as is the negative input of the
comparator 102). The negative input of comparator 103 is
, connected to the positive terminal of the capacitor 96.
7 The positive input of the comparator 102 is
connected through an inverter 105 to the output of the
30 previously described inverter 76.
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1327391
The set point voltage, VST PT ~ is generated across
a capacitor 108, the positive terminal of which is connected
to the movable arm of a potentiometer generally designated
109. A fixed resistor 110 is connected in series with the
fixed resistor of the potentiometer 109 to the reference
voltage developed across zener diode 91. As previously men-
tioned, the set point voltage is fed to the positive input
of the comparator 42.
As mentioned, the minimum frequency oscillator
95 serves to estab]ish a minimum switching frequency for
the inverter (i.e., the power switches 30, 31) so that in
the event comparator 42 does not trigger the flip-flop 43,
the minimum frequency oscillator 45 will perform that
function. Otherwise, it would be possible to have one of
the power switches 30, 31 be left on indefinitely, thereby
saturating the power transformer and preventing normal
l operation of the circuit.
I Once the low voltage source has stabilized after
the initial build-up period follo~ing turn on, so that the
gates 72, 74 are enabled by the output of comparator 81,
j the normal operation of the circuit proceeds as follows.
1 Assuming the power switch 30 has just been switched to a
conducting state, the voltage at the junction 32 increases
as current flows through resistor 33. That voltage signal
is fed through resistor 67 to the negative input of com~
parator 42, the positive input of which is at the fixed set
' point voltage. When the increasing voltage appearing on
the negative input of comparator 42 exceeds the set point
voltage, the output of comparator 42 switches to a relatively
low voltage which is fed directly to the gates 72, 74 to
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~327991
. , .
disable them for a short period of time to permit the flip-
flop 43 to switch its state and to permit current flowing
through power switch 30 to return to zero (which does not
happen intantaneously).
When the current flowing through the power switch
30 (which had just been turned off) returns to a zero level,
and after the output state of flip-flop 43 has changed, the
output of comparator 42 again goes positive because current
stops flowing through switch 30 so the voltage at terminal
32 diminishes beneath the set point voltage. This causes
gates 72, 74 once more to be enabled, but the signal inputs
from the flip-flop 43 have now assumed their complementary
states so that whereas in the previous half cycle, power
switch 30 had been conducting, when the gates 72, 74 are
once more enabled, power switch 31 is turned on.
As illustrated in idealized form in FIG. 4, the
voltage on the negative (inverting) input of comparator 42
is represented by the ramp voltage 107. When that voltage
exceeds the set point voltage, the output of comparator 42
goes relatively low, thereby disabling the switches 72, 74
and turning off the power switch 30 at time t6 in FIG. 4.
The current flowing through the switch takes some finite
time to reduce to zero as indicated by the portion 108,
although the lines 107 and 108 are not necessarily drawn
to the same time scale. The same output signal of comparator
42 which disables the gates 72, 74 is inverted by inverter
76 and fed to the clock input C of the flip-flop 43 to cause
its outputs to change state because the Q output is connected
to the data input D of the flip-flop. The gates 72, 74 are
j 30 disabled before flip-flop 43 changes its state so that the
. :
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132799
switching signals on the output leads of the flip-flop are
` not fed directly to the power switches.
At the same time, the output signal of the inverter
76 is coupled through inverter 105, the output signal of
- which is a negative pulse which causes comparator 102 to
switch to a low output level and thereby create a low
impedance path for quickly discharging capacitor g6. This
resets the timing of the minimum freauency oscillator and
synchronizes it with the switching of the inverter switches
under normal operating conditions.
If the voltage at junction 32 does not rise to
the set point voltage within the design period of the minimum
frequency oscillator 95, the minimum frequency oscillator
will nevertheless sustain operating at a minimum frequency
as follows. When comparator 102 changes state from a
relatively low voltage output to a relatively high voltage
! output, the output of the comparator is floating so that
. it becomes a comparatively high impedance and is not a
substantial factor in charging capacitor 96. Rather,
capacitor 96 is charged as a function of the magnitude of
voltage of the B~ supply (through resistor 100). Thus, when
the voltage on capacitor 96 exceeds the reference voltage
across zener diode 91, comparator 103 will switch its output
from a relatively high voltage level to a low voltage level,
thereby disabling gates 72, 74, triggering the clock input
of the flip-flop 43 via inverter 76, and causing the output
of comparator 102 to go low. ~his discharges capacitor 96
which, in turn, causes comparator 103 to chanqe states once
more so that its output goe8 to a relatively high voltage
! 30 level. As described above, when the signal at junction 85
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goes positive, gates 72, 74 are enabled once more, but since
the state of flip-flop 43 has changed, the complementary
power switch (30, 31) will conduct this half cycle.
The timing of the charging of capacitor 96 depends
primarily on the value of the capacitor and the value of
` resistor 100, and the magnitude of the B+ voltage. The
minimum operating frequency of the minimum frequency
oscillator ~which is not a fixed frequency oscillator, it
- will be observed, because of the influence on the charging
timer capacitor 96 caused by the value of the B~ voltage),
is designed to be lower than the minimum operating frequency
, of the inverter during normal operation. This insures that
;l the inverter will be operating as designed for normal opera-
tion and not under the minimum frequency oscillator. ~en,
during normal operation, the output of the comparator 42
goes low (representative of the current in the then-
conducting switch reaching a predetermined peak value), the
gates 72, 74 are disabled, as described, and the flip-flop
43 is clocked, but also, the same signal is fed through
inverter 105 to cause the comparator 102 to change states
and have its output grounded, thereby discharging capacitor
96 and resetting the time base for the minimum frequency
, oscillator. Thus, the minimum frequency oscillator is syn-
chronlzed automatically each half cycle, with the switching
on of the power switches. ~he minimum frequency oscillator
comes into play only after the current in current sensing
¦ resistor 33 and the voltage at junction 32 do not exceed
j the set point voltage during a period of time longer than
the time it takes capacitor 96 to charge to the reference
voltage on the positive input of comparator 103.
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: 1327991
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If the B+ voltage is relatively high, then the
time for the voltage at junction 32 to reach the set point
voltage will be correspondingly less. Similarly, the period
of the minimum frequency oscillator 95 will be correspond-
; ingly less and the operating frequency will be higher
because, with the B+ voltage comparatively high, charging
current through resistor 100 to charge the timing capacitor
96 will be correspondingly greater, thereby reducing the
time for the capacitor to charge to the reference voltage
on the positive input of comparator 103.
Thus, the base or set frequency of the minimumfrequency oscillator increases and decreases as the B+
voltage increases and decreases. Persons skilled in the
art will appreciate that having the base frequency of the
minimum requency oscillator 95 vary with the value of B+
,,
voltage reduces the requirements and thus the size of the
power transformer. Reduced size, in turn, reduces its cost.
There is a short delay time in turning the power
switches off--that is, between the time the volt~ge input
to the switching level and the time the signal is propagated
through the comparator and goes to cause the current through
the switch to stop flowing. This causes a slight overshoot
in the current flowing through the switches after the switch-
ing level at 32 is reached so that the current flowing at
~ the time of shut-off may be above the desired current level.
I Since the rate of rise of current flowing in the switches
is a function of the applied voltage ~that is, the B+
voltage), this overshoot will also be a function of applied
voltage. In other words, the overshoot will be greater when
j 30 the B+ voltage is at its peak than when it is at the make-up
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13279~1
voltage level. In order at least partially to compensate
this effect, resistor 69 is connected between the B+ voltage
terminal 13 and the inverting input of comparator 42. As
the B~ voltage becomes greater, more current is fed through
resistor 69, causing comparator 42 to change states earlier
than otherwise would occur, and thereby compensating for
the overshooting current mentioned above.
Resistor iO and its associated circuitry compen-
sates for yet another effect. The storage capacitor 62 which
stores power for the make-up voltage during the inter-cusp
period is charged by the bridge circuit 61 only when the
' B+ voltage is near a peak, and during that time, energy drawn
from the source reduces the energy available to the lamp
circuit. Since a constant load current is desired, and some
input power is diverted to the make-up power source as just
indicated, a signal is generated across resistor 63 during
the time when capacitor 62 is being charged. This signal
, is a negative signal which draws a slight current through
resistor 70 and causes the current thro~gh resistor 33 to
rise to a slightly higher-value before the input signal to
the inverting input of comparator 42 will switch. The
additional power is coupled to store energy in storage
capacitor 62 for use during the inter-cusp period of source
voltage and thereby partly compensate for the effect of
draining power during voltage peaks of the primary source
voltage to charge the make-up capacitor 62 by extending the
"on" time of the power switches as a function of the
magnitude of the B+ voltage.
Inductor 38 is illustrated in FIG. 1 as a separate
component. Preferrably, however, it is incorporated into
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the magnetic design of the power transformer 15. In either
case, whether a separate component is included or the trans-
former 15 is designed to have the desired higher impedance
at higher frequency, the overall effect is that as the
inverter operating frequency increases, the impedance seen
by the power switches also increases and the lamp load
current remains substantially constant. By way of example,
for the range of operating frequency indicated below, if
the inductor 38 is designed as the leakage inductance of
the power transformer 15, it may be approximately 4 mhy.
By way of further illustration, with the components
indicated in Table A below, and with two 34-watt lamps in
the lamp circuit, the operating frequency of the power
inverter under normal conditions (i.e., without the minimum
frequency oscillator being actuated) varies from 30 R~z to
75 KHz; and a crest factor of approximately 1.6 has been
obtained. With the components indicated in Table B below,
the minimum frequency oscillator operates in a frequency
range from approximately 23 K~z to 40 XHz.
TABLE A
Component Value
resistor 33 0.5 ohm
diode 91 4.7 volts (break-down)
resistor 63 1.0 ohm
resistor 70 3.3 K ohm
resi.stor 32 1.0 X ohm
resistor 69 330 K ohm
.
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- 1327991
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~- TABLE B
Component Value
diode 91 4.7 volts (break-down)
diode 57 12 volts (Vcc)
resistor 100 330 X ohm
capacitor 96 .001 ufd.
. . .
In addition to the features and advantages
mentioned above in connection with particular aspects of
the embodiment illustrated in FIG. 1, persons skilled in
the art will appreciate that measuring inverter current in
the circuit connected to the primary winding of the power
transformer, as distinguished from the load circuit in the
secondary of the transformer further reduces cost because
it eliminates any need for a current transformer in the
secondary or load circuit.
Referring now to FIG. 5, there is shown an alter-
native embodiment of t~e invention which uses current mode
regulation as described above, but which includes the
switches and power transformer in a half-bridge circuit con-
figuration, as distinguished from the push-pull arrangement
shown in FIG. 1 and described above. The half-bridge circuit
has isolating transformers for sensing current in, and for
driving the power switches and these components will increase
cost. The half-bridge configuration also requires increased
capacity in the low voltage (i.e., logic) power supply.
On the other hand, the half-bridge circuit arrangement per-
mits the use of power MOSFET switches with lower voltage
and higher current ratings which currently are less
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:
expensive. Thus, the half-bridge circuit may be used, for
example, with a 277 v. line voltage.
In the half-bridge circuit of FIG. 5, the B+
voltage is derived with a full-wave rectifier and a make-up
source as described in connection with the embodiment of
FIG. 1 Corresponding elements in FIG. 5 are given the same
reference numeral as in FIG. 1 followed by an "A". Thus,
the MOSFET power switches are designated 30A and 31A and
are connected in series across the B+ supply. Capacitors
220 and 221 are also connected in series across the B~ supply
voltage; and the primary winding 222 of power transformer
223 forms the diagonal branch of the bridge circuit. The
lamp load circuit 35A is connected to the secondary winding
224 of the power transformer. Although not illustrated in
the dra~7ing of FIG. 5, power transformer 223 has a leakage
:1
inductance similar to that designated 38 in FIG. 1 and per-
forms a similar function.
In the embodiment of FIG. 5, current flowing in
the conducting power switch is sensed by a current trans-
former 226 having its primary coil connected in series withprimary winding 222. Alternatively, the current transformer
could be in the secondary of the power transformer. The
~ output signal of current transformer 226 is coupled to the
i input of logic circuit 140 which may be substantially the
, same as the previously descrihed logic circuit 40, except
', that it is responsive to the absolute value of the output
of current transformer 226 ~i.e., not polarity sensitive).
In particular, the output of the current transformer 226
may be coupled through a diode bridge (which gives a signal
representative of the absolute value of the input signal
26
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1327991
and is not sensitive to the polarity of the input siqnal)
to the junction of resistor 70 and capacitor 58 of FIG. l
(which is the same as the non-inverting input of comparator
42). The inverter drive signals of inverter circuits 73,
75 are, in this case, coupled to the primary winding 228
of a drive transformer 229 having two secondary windings
- 230 and 231 ~hich are connected in the gate circuits res-
pectively of the power switches 30A, 30B. Resistor 67 of
the FIG; l embodiment is eliminated. The drive transformer
10 229 has its secondary windings arranged in a polarity to
cause only one of the switches to conduct at any given time.
When switch 30A condùcts, for example, current flows from
the positive terminal of the B+ voltage through MOSFET 30A,
the primary of current transformer, the primary winding 222
of the power transformer (from the plus to the minus
terminal) and capacitor 221 to the negative terminal of the
B+ supply. ~hen the value of current sensed by the current
transformer reaches the preset value, the bistable circuit
i~ of the logic circuit switches states; and after switch 30A
l 20 becomes non-conducting, switch 30B is turned on and current
1 flows through capacitor 220, primary winding 222 (this time
7 in the opposite direction), the current transformer and
switch 30B. Thus, an alternating current is generated in
the power transformer to energize the lamp load circuit 35A.
As in the first embodiment, the frequency of
operation of the inverter increases and decreases, but the
peak value of current flowing in the primary ~and secondary)
of the power transformer 223 is substantially constant.
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As the inverter frequency increases, the leakage reactance
of the power transformer is such as to present an increased
impedance so that the peak value of load current also remains
substantially constant and the crest factor of load current
. remains below a desired value.
Persons skilled in the art will appreciate that
certain of the above elements may be changed, or equivalents
may be substituted for those circuits or components dis-
closed, while continuing to practice the principle of the
10 invention; and it is, therefore, intended that all such
:~ modifications and substitutions be covered as they are
embraced within the spirit and scope of the appended claims.
''.
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