Note: Descriptions are shown in the official language in which they were submitted.
1 3 )~63 1
¦The present invention relates to a digital signal
exchange equipment for connecting a plurality of digital
¦signal input circuit lines to an arbitory circuit line
of a plurality of output clrcuit lines and to a circuit
line selection control apparatus for selectively
controlling a circuit line connection and for preventing
a connection error at an exchange time.
In general, a digital signal exchange equipment for
performing an exchange of a fast and continuous digital
signal, such as an image PCM signal used, for example,
at a broadcasting station comprises a matrix array of
switching elements each provided at a crosspoint of each
input line with a corresponding output line, or at a
crosspoint of each output line with a corresponding
input line, with the input and output lines connected
to input and output circuit lines, respectively, as a
lattice-like structure. In this matrix array, any input
circuit line can be connected to any output circuit line
by making a selective, switching connection to a prede-
termined switching element.
A matrix type unit for controlling a crosspointconnection by the switching element requires a very
large number of switching elements with an increase in
the circuit lines and, furthermore, the switching of the
switching elements is very complex to control. Since,
in this case, an input digital signal has to be passed
through a great many of switching elements until it is
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1 33263 '
output from the exchange equipment, it is not possible
to, due to a high-speed requlrement for a digital signal
to be transferred, disregard a delay of that signal when
it passes through the switching elements. AS the
switching elements, use may be made of electronic
switches (semiconductor switches) in which case the
signal passage characteristics of this type of switches
are generally not equal in terms of the delay of a
signal at a time of a rise and a fall. For this reason,
the input digital signal suffers a deformation with
respect to time, each time it passes through the
switching element, so that it has a very great defor-
mation. This causes a difficulty in a signal iden~
tification.
As a general countermeasure against this situation,
a met~od may be adopted which achieves the synchroniza-
tion and waveform-shaping of such digital signal by a
flip-flop each time that signal passes through the
switching element at the crosspoint. If, however, this
method is applied to an exchange equipment having a
simple matrix array as set forth above, a great number
of flip-flops are required in the case where many cir-
cuit llnes are involved. This system disslpates more
electrlc power and is difficult to implement because of
many flip-flops involved, failing to offer any practical
countermeasure.
on the other hand, a circuit line selection
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control apparatus used in the conventional exchange
equipment performs a selective switching among the
many circuit lines in a time-division fashion and
dynamically monitors the switching elements so that
a connection error may be prevented. In the time-
division exchange system, however, the select signal is
multiplexed in a time-division fashion to conform to
the characteristic of the digital signal transmitted
and then input to the exchange equipment. In the
lo treatment of a fast, continuous digital signal, such
as an image PCM signal, the bit rate of the select
signal after being multiplexed becomes an extremely
high level. It is, therefore, not easy to implement
such a system. The error connection preventing means
works under dynamical control of the switching element,
only after a switch connection has been achieved, and
it is not preferable that it be employed for such a
purpose.
As set forth above, the conventional digital
signal exchange equipment involves a high-speed re-
quirement for transmitted digital signals as well
as an increase in a signal delay among the circuit
lines resulting from a large increase in the number
of circuit lines. It is thus difficult to meet the
hlgh-speed requirement for digital signals as well as
an increase in the number of circuit lines. Since
the conventional circuit selection switching apparatus
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1 3s263 1
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? performs a selective switching among circuit lines, it is not
easy to achieve it as a practical apparatus due to an
extremely high bi~ rate of the select signal. Indeed in
spite of the dynamic monitoring of the switches, the
apparatus works only after a switch connection is achieved,
failing to be manufactured as a fully practical apparatus.
A first object of the present invention is to provide a
digital signal exchange equipment which is simple in
arrangement, easy in the control of a switching among circuit
lines, uniform in a signal delay ti~,e among the circuit lines
and can fully suppress deformation caused during a signal
¦ transmission whereby it is readily possible to achieve a
high-speed requirement for transmitted digital signals as
well as an increase in the number of the circuit lines.
A second object of the present invention is to provide a
I circuit line selection control apparatus which can readily
i and positively provide a protection against a circuit line
connection error when the digital signal exchange equipment
is implemented according to the first object of the present
invention.
According to a first aspect of the present invention
there is provided a selector module for a digital signal
I exchange equipment comprising: an m number (m: a natural
¦ number) of basic selection circuits each comprising a first
selection section for selecting, by a tournament system, a
line designated by a first selection signal from an n number
~n: a natural number) of first input lines, and a second
selection section for selecting a line designated by a second
selection signal from the line selected by said first
selection section and a second input line and connecting the
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1 3 3263 1
selected line t~ an output line; an internal input bus for
supplying a digital signal of n channels to all of said n
number of first input lines of said m number of basic
selection circuits; and selection signal distributing means S for inputting said first and second selection signals for
designating the selection states of said first and second
selection sections of each of said basic selection circuits.
According to a second aspect of the present invention,
there is provided a digital signal exchange equipment
comprising: a kx Q (k, Q a natural number) number of
selector modules arranged as a k-columns/ ~ -rows array, each
of said selector modules comprising; m number (m: a natural
number) of basic selection circuits each comprising a first
selection section for selecting, by a tournament system, a
line designated by a first selection signal from an n number
(n: natural number) of first input lines, and a second
selection section for selecting a line designated by a second
selection signal from the line selected by said first
selection section and a second input line and connecting the
selected line to an output line; an internal input bus for
supplying a di~ital signal of n channels to said n number of
first input lines all of said n number of basic selection
circuits; and selection signal distributing means for
inputting said first and second selection signals for
designating the selection states of said first and second
selection sections of said basic selection circuit; a k
number of input buses each constituted by n number of lines,
said input buses respectively provided for the columns of
said selector modules, for supplying a digital signal of n
channels to all of said internal input buses of the selector
modules in a column; a kx ~ number of extended buses, each of
which is constituted by m number of lines and connects m
number of output lines of the selector modules in a column to
the second input line of the selector module of the next
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1 33263 1
column in the same row, m number of output lines of the
selector modules in the final column to the second input line
of the selector module in the ~irst column of the next row,
and m number of output lines of the selector module in the
final column of the final row to the second input line of the
selector module in the first column of the first row;
selection signal generating section for designating a basic
selection circuit of a selector module and generating the
first and second selection signals for the first and second
selecting section: and selection signal transmitting means
for transmitting the selection signal to the designated
selector module.
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¦ This invention can be more fully understood from the
following detailed description when taken in conjunction with
the accompanying drawings, in which:
Figs. 1 to 6 are views showing a digital signal exchange
equipment according to one embodiment of the present
invention;
Fig. 1 is a block circuit diagram showing a whole
circuit arrangement of the digital signal exchange equipment,
excluding a control system;
Fig. 2 is a view showing a selector module of Fig. 1 and
input/output signals for the selector module;
Fig. 3 is a block circuit diagram showing a detailed
circuit of a gate array in the selector module shown in Fig.
2;
Fig. 4 is a block circuit diagram showing an inner
circuit of the selector module of Fig. 2;
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1 33~h31
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Fig. 5 is a logic circuit diagram showing
a d~tailed arrangement of the gate array shown in
Fig. 3;
Fig. 6 is a logic clrcult diagram showlng a 2xll
gate which ls used for a gate array shown in Fig. 3;
Figs. 7 to 9 are views showing a selectlon
switching control apparatus according to another
embodiment of the present invention;
Fig. 7 is a block circuit diagram showing a circuit
lo arrangement of a control system of the selector module
shown in Fig. 3;
Fig. 8 is a block circuit diagram showlng a circuit
arrangement of a checking clrcuit arrangement suitable
for a control system of Flg. 7; and
Fig. 9 is a logic clrcult dlagram showing an
arrangement of a parlty checking circuit arrangement of
~ Fig. 8.
;~ An embodiment of the present invention will be
explained below with reference to the accompanying
drawings.
First, a digital signal exchange equipment
according to one embodiment of the present invention
wlll be explained below with reference to Figs. 1 to 6.
Fig. 1 shows a whole arrangement of a 16xl6-input/
16x16-output type dlgital signal exchange equipment
according to the present invention, noting that, here,
a control system is omltted.
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g
In the arrangement shown in Fig. 1, Sl to S2s6
¦ denote selector modules which constitute a 32-input/
¦ 16-output (hereinafter referred as 32X16) type IC
device having 16 inputs in a column direction and 16
outputs in a row direction. The IC device is formed,
as a 16-columnxl6-row array, on a substrate a. IB1 to
IB16 show internal input buses which are provided to
correspond to respective 16 circuit lines of 16x16
circuit lines of external lnput terminals, not shown.
Digital signals which are input to external input ter-
minals of respective 16 circuit lines are transmitted,
respectively through bus drivers BDl to DB16, to 16
selector modules S1 to S16, S17 ~o S32, ..., S241 to
S256 on respective columns.
CB1 to CB240 denote internal common buses and
transmit 16 outputs of selector modules S~ to Sl6~ on a
~-th column to 16 inputs of selector modules S~+1 to
Sl6(~+l) on an(~+l)th column, noting that ~ denotes a
natural number of 1 to 15~ CB241 to CB256 are internal
common buses and transmits 16 outputs of the selector
modules S241 to S256 on the 16-th column to 16 inputs
of selector modules S2 to S16 on the next column, noting
that CB256 denotes an initial row. OBl to OB16 are
internal output buses and transmit 16 outputs of selec-
tor modules S24l to S2s6 on the column to correspondingexternal output terminals, not shown, of 16x16 circuit
lines.
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An interface for control signal inputting/outputting, as
well as a control bus for making a connection between the
interface and the respective selector modules Sl to S256, is
provided on the substrate a, though not shown in Fig. 1. The
interface is connected to a host computer, not shown, and the
respective selector modules Sl to S256 are selectively
controlled by the host computer.
~hat is, in the digital signal exchange equipment so
arranged, the digital signal inputs I1 to I2s6 16x16 circuit
lines are divided into 16 sections and are connected
respectively through buffer drivers BD1 to BD16 to the
internal input buses IBl to IB16. The input digital signals
of the internal input buses IBl to IB16 are transmitted to
the selector modules S1 to S16, S17 to S32, --, S241 to
S256-
The host computer HC generates a select control signal
SS (A0 to A4, CK, WRITE, LOAD, AD) for designating a select
execution operation in a chip select signal CS for assigning
the select control signal to the selector modules Sl to S256.
These signals are supplied to the interface I/O for
controlling the device of this invention. The interface I/0
transmits the select control signals SS from the host
computer HC to the modules S1 to S256 via a control bus, and
6electively raises the chip select signals CSl to CS256 for
the modules Sl to S256 on the basis of the chip select signal
CS supplied from the host computer HC (not shown for
clarity).
The respective selector modules Sl, ..., S256 are
arranged such that the input lines on the respective column
are connected, in an normal state, to the corresponding
output lines on the same column. When the input and output
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lines on the column are designated by a control signal which
is input via the control bus, the corresponding designated
lines are selected for connection. A digital signal on the
output line of a column is output to an outside via the
internal output bus line of the same column, unless the
first-mentioned line is selected by the other selector.
Fig. 2 shows a detail of the 32x16 selector modules S
where I1 to I16, Cl to C16, l to 16l and Ao to A4 denote
internal input bus lines, internal common bus lines, internal
output bus lines, and control bus lines, respectively. The
selector modules S is of such a type that gate arrays Gm (m =
1 to 16) as shown in Fig. 3 are constructed of a parallel
array of 1~ gates on the column as shown in Fig. 4 where the
input terminals of the respective gate arrays are connected
to the internal input bus lines I, to I16 via input bus lines
IIl to II16 in the selector module S. The synchronizing
clock signal CK, a write instruction signal WRITE, a load
instruction signal LOAD, a 4-bit address data AD and a chip
select signal CS are supplied to the selector signals A0 to
A4.
In Figure 3, the internal structure of the selector
module S including the control system is shown in the Figure
4, and a detailed structure of the gate array Gm is shown in
Figure 3. For example, in Figure 4 the internal bus line ITl
to IT16, for the transmitting line inputs I1 to I16 of the
gate arrays G1 to G16, and a transmission line for
synchronizing clock signal CK are found. Further, the
internal bus lines for select signals A0 to A4 are identified
as AA0 to AA4.
In Figure 3, a synchronizing clock signal CK is supplied
to the flip-flop F/F. However, if the device is small and a
delay of the transmission signal does not influence the
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1 33~631
operation of the device, the flip-flop F/F may not be
required. Accordingly, if the device is small and the flip-
flop F/F is not present, the synchronizing clock signal is
not required.
~he detailed arrangement of the gate array Gm will be
explained bèlow with reference to Fig. 5. The first 16xl
gate gl constitutes a tree-like array of 2xl gates gO1 to gl5
with eight 2xl gates gO1 to gO8 at a first stage, four 2xl
gO9 to gl2 at a second stage, two 2xl gates gl3 and gl4 at a
third stage and one 2xl gate gl5 at a fourth stage. The
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to gO8, gos to gl2, gl3 to gl4 and gls are selectively
controlled by select signals Ao, Al, A2 and A4, respec-
tively.
Of the input bus lines IIl to II16 connected to
the first gate gl, eight lines are selected by the gates
gOl to gO8 at the first gate, four lines are selected by
the gates gO9 to gl2 at the second gate, two lines are
selected at the third gates gl3 and gl4 and one line is
selected by the gate gl5 at the fourth gate. In this
way, the output of the first gate gl is connected to the
input of the second 2xl gate g2.
Here, the respective gates gO1 to gl5 are so
constructed that, for example, the upper lines are
selected when a select signal is "O" and the lower lines
1 15 in Fig. 5 are selected when the select signal is "1".
In order to select an input bus line IIn, it is only
necessary that a value of (n-l)2 in binary notation be
applied to the select signal of the control bus lines A
to A3. If~ for example, IIo7 is to be selected, it is
only necessary to put a select signal (A3A2AlAO)2 as
(0110)2 (= (7-1)1o). It is thus easy to set any select
signal by establishing the aforementioned relation.
The second gate g2 is controlled by a select signal
coming from the control bus lines A4 and selects an
output line of the first gate gl when A4 = "1" and an
internal common bus line Cn when A4 = "O".
The 2xl gates gOl to gl5 and g2 can be implemented
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by a logic circuit as shown in Fig. 6. In an arrange-
ment shown in Fig. 6, A, B denote a digital signal input
line; C, a control signal input llne; and X, a digital
signal output line. The aforementioned logic circuit
implements
X = (A*C) + (B*C~.
That is, A is selected at an AND gate ANDl when
C = o an B is selected at an AND gate AND2 when C = 1
in which case the selected signal is taken out as x via
an OR gate OR.
If, as set forth above, the gate array Gm is
constructed with the 2xl gate as a fundamental element,
the input signal can pass through the gates with an
equal number of gate passages to obtain ready synchro-
nization and ready selection control can be achievedwith 5-bit select signals (Ao to A4).
Fig. 7 shows an arrangement of a control system for
the aforementioned selector modules S. A control bus
which is connected to the module S is constituted by
the aforementioned five-bit select signal (Ao to A4),
4-bit address data AD, chip select signal cs, write
instruction signal WRITE and load instruction signal
LOAD.
on the other hand, a control system comprises, for
the respective gate array Gm, first and second latch
circuits Lln and L2n and AND gates gan and address
decoder ADD.
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`~ A bus line of a 4-bit address data AD and chip
select signal cs is connected to the address decoder
ADD, and a bus line of an n channel output ADn o the
address decoder ADD and write instructlon slgnal WRITE
is connected to the AND gate gan. The 5-blt bus llne of
the select signals Ao to A4 and output line of the AND
gate gan are connected to the first latch circuit Lln;
the 5-bit output line of the flrst latch circuit Lln and
a bus line of a load instruction signal LOAD are con-
nected to a second latch circuit L2n; and a 5-bit output
terminal of tha second latch circuit L2n is connected to
a control bus of the respective gate array Gm.
That is, the aforementioned address decoder ADD is
inltiated upon receipt of a chip select signal cs and
receives the 4-bit address data AD to identify which
gate array Gm is designated, and transmits a designation
signal ADn to the AND gate gan of the designated gate
array Gm.
Upon receipt of the designated signal ADn, the AND
gate gan supplies a write instruction signal WRITE to
the first latch circuit Lln. The first latch circuit
Lln receives the select signals Ao to A4. when it
receives a write instruction signal WRITE, and holds
them until it receives the next write instruction signal
WRITE. Upon receipt of a load instruction signal LOAD,
the second latch circuit L2n receives a latch output of
the f1rst latch clrcult Llr and transmlts lt to the gate
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- 15 - 13)26,1
array Gm until the next instruction signal LOAD is
received. By so doing, it is possible to make the
first latch circuit Lln in a ~freely writable" state
and hold the next select signal for the respective gate
array Gm.
The digital signal exchange equipment thus arranged
includes a combination of IC selector modules and can
readily cope with an increase in their circuit lines.
Furthermore, the exchange equipment allows the use of a
simpler control system since it is possible to perform
control per module. At the same time, since the respec-
tive modules are switchingly controlled by the output
of the latch circuit and since the synchronization, as
well as the shaping of a waveform, is achieved by the
flip-flop circuit in the respective module, a circuit-
to-circuit delay time becomes uniform and any possible
deformation as generated during a signal transmission
can be reduced to a satisfactory extent. As a result,
adequate preparation can readily be made for the use of
a high-speed digital signal as well as an increase in
the circuit lines.
In the digital signal exchange equipment, there is
a possibility that if an error signal is latched to the
first and second latch circu~t Lln and L2n due to some
cause, such as a noise, a connection error will arise
relative to the input and output circuit lines in the
selector modules S. As a general way of monitoring
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- 16 - 13~2631
such a connection error~ use may be made of a scanning
system which sequentially reads ~held data~ out of the
control register (latch circults Lln, L2n) in the
respective module and ascertains whether or not normal
control data is stored. Since, in this scanning system,
the number of control registers for storing control
information is increased with an increase in the size of
the signal exchange equipment, a lot of time is taken to
read the information out of all the control registers in
lo a sequence. It also takes a lot of time to respond to
any abnormality, if any. A checking mechanism is,
therefore, required to ascertain whether or not a
correct select signal is latched to the latch circuit
(Lln~ L2n), that is the control register.
Fig. 8 shows an arrangement of a checking circuit
arrangement for the circuit line selection control
apparatus of the present invention which is provided to
meet the aforementloned need. The checking circuit
arrangement is provided for the respective gate array
Gm. In the arrangement shown in Fig. 8, identical
reference numerals are employed to designate parts or
elements corresponding to those shown in Fig. 7 and
different parts or sections will be explained below.
To the aforementioned control bus are connected
bus lines of a parlty signal P, even/odd designation
signal EVEN/ODD, read instruction signal READ and read
switching signal RR, 6-line read output bus RB and
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- 17 -
write output bus WB (Ao to A4, P control bus lines) and
bus lines for parity error slgnals PEl, PE2. The read
output bus RB, write output bus WB and respective buses
of the parity error signals PEl, PE2 are connected via
their interface to an external host computer. In this
connection, it is to be noted that the read output bus
RB and write output bus WB may be provided as a single
shared bus because a write and a read operation are not
performed simultaneously.
A 6-bit register is employed for the first and
second latch circuits Lln and L2n. The first latch
circuit Lln receives a write instruction signal from an
AND gate gn and holds not only select signals Ao to A4
but also a parity signal P. The held signals Ao to A4
and P are output to a second latch L2n, first parity
check circuit PCl and switch circuit SWl. Upon receipt
of a load instruction signal LOAD, the second latch
circuit L2n supplies the output signals Ao to A4, P to
the first latch circuit Lln to the second parity check
circuit PC2 and second read switch circuit SW2, and
only select slgnals Ao to A4 are fed to a gate array
Gm.
The first and second parity circuits PCl to PC2
are of the same type and are constructed as shown, for
example, in Fig. 9. In the arrangement shown in Fig. 9,
gOl to gO3 denote exclusive OR gates (hereinafter
referred to as EX-OR gates) in which case signals Ao to
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- 18 _ 1 3 32h 3 1
A2 are supplied to the gate gOl, signals A3, A4, P and
EVEN/ODD are supplied to the gate gO2 and the outputs of
the gates gOl and gO2 are supplled to the gate 03. In
Fig. 9, the EX-OR gates gO1 and gO2 are indicated as
having three and four inputs, respectively, showing that
the 2-input EX-OR gates are multi-connected to obtain
the gates gO1 and gO2.
The even/odd designation signal EVEN/ODD determines
whether a parity signal is set as an even parity or an
odd parityO The parity signal P is determined based on
the even/odd designation signal EVEN/ODD. For example,
at Ao to A4 ="00101" and EVEN/ODD = 1, a parity signal
P becomes "O". If the output PEl (or PE2) of the ~:
EX-OR gate gO3 becomes ~'1", an error is detected and a
detected output is supplied to a host computer via the
bus line (PEl, PE2)-
The read instruction signal READ and read switchingsignal RR select the first and second read switch
circuits SWl and SW2 via the gates gln to g3n, and the
outputs of the switch circuits SWl and SW2 are fed to
the read output bus RB. For example, at READ = "1" and
RR = "O", the outputs of the gates gln, g2n and g3n
become "1", "1" and "O", respectively, turning the first
read switch clrcuit SWl ON and the second read swltch
SW2 OFF. The outputs Ao to A4, P of the first latch
circuit Lln are read onto the output bus RB. When
RR = 1, the outputs of the gates gln, g2n and g3n become
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13~2631
-- 19 --
"0", "01l and ~ , respectively, turning the first read
¦ switch circuit Swl OFF and the second read switch cir-
cuit SW2 ON. The outputs Ao to A4, P of the second
latch circuit L2n are read onto the output bus RB.
That is, in the aforementioned control system, the
select signals Ao to A4 and parity signal are sent to
the latch circuit Lln and L2n. The respective outputs
of the latch circuits Lln and L2n are parity-checked
and, if an error occurs, error signals PEl, PE2 are sent
to the host computer. It is thus possible to immedi-
ately ascertains whether or not right select signals
are held in the respective latch circuits Lln and L2n
and to, if an error occurs, implement an interrupt
processing for data preservation to be made by the
host computer. ~pon receipt of the read instruction
signal READ and read switching signal RR, the first
and second latch circuits Lln and L2n send the respec-
tive outputs ~0 to A4, P to the read output bus RB as
set forth above and from there onto the host computer.
By so doing, the host computer can sequentially monitor
¦ the memory contents in all of the latch circuits,
thereby largely reducing a response time from the
generation of an error to a corresponding action to be
taken.
Thus the circuit line selection switching control
apparatus having the aforementioned checking circuit
arrangement can readily and positively provide
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a protection against a connection error between the
circuit lines.
