Note: Descriptions are shown in the official language in which they were submitted.
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IMPROVED ~NSU~ATOR STRUCTURE FOR A~ORP~OUS
SI~ICON T~IN-FI~M TRANSISTORS
S ~a~k~s~ . Qf--~ ~Y-eJltion
The present invention relates to thin-film field-
effect transistors and, more particularly, to an improved
gate insulato~ structure for amorphous silicon (a-Si) thin-
film field-effect transistors (FETs), such as may be employed
in matrix addressed liquid crystal displays (LCD) and the
like.
Thin-film FETs have a variety of applications; for
example, one use of thin-film FETs is in LCD devices. A LCD
device typically includes a pair of flat panels sealed at
their outer edges and containing a quantity of liquid crystal
material. Transparent electrode material, such as indium tin
oxide (ITO) or the like, is typically disposed on the inner
surfaces of the panels in predetermined patterns. One panel
is often covered completely by a single transparent "ground
plane" or "back plane" electrode and the opposite panel is
configured with an array of transparent electrodes, referred
to herein as "pixel" (picture element) electrodes; the pixel
electrodes are usually arranged in uniform columns and rows
to form an X-Y matrix structure. Thus, a typical cell in a
LCD devic~ includes liquid crystal material disposed between
a pixel electrode and a ground electrode, and forming, in
effect, a capacitor-like structure diqposed between adjacent
front and back panels.
If the LCD device is to operate by reflected light,
then only one of the two panels and the electrodes disposed
thereon need be light transmissive with the other panel and
electrodes disposed thereon being formed from a light reflec-
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tive material. If the LCD device is to operate by
txansmission of a backlight through the LCD, then both panels
and the electrodes disposed thereon must be light
transmissive.
In operation, the orientation of the liquid crystal
material is affected by voltages applied between the pixel
electrodes and the ground plane electrode, disposed on
opposite sides of the liquid crystal material to cause an
electric field to be formed therethrough responsive to the
voltage. Typically, voltages applied to the pixel electrode
effect a change in the optical properties of the liquid crys-
tal material. This optical change facilitates the display of
information on the screen of the liquid crystal display
device.
While many forms of electrical mechanisms can be ~-
employed to turn on and off individual pixeL elements of an
LCD device, the utilization of thin-film field-effect
transistors (TFTs), and especially those FETs employing a
layer of amorphous silicon (a-Si), are preferred because of
their potentially small size, low power consumption, high
switching speed, ease of fabrication and compatibility with
conventional LCD structures.
Electrical communication with the individual pixel
FETs is accomplished by use of coincident addressing
techniques using a plurality of X-address lines or scan
lines, typically one for each row (or column) of pixels, and
a plurality of Y-address lines or data lines, one for each
column (or row) of pixels. The scan lines are usually con-
nected to the gate electrodes of the pixel FETs and the data
lines are usually connected to the source electrodes. The
drain electrode of each FET is connected to the associated
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pi.xel electrode. An individual pixel may be addressed by
applying a voltage of sufficient magnitude to one of the scan
li.nes to cause the FETs in the row corresponding to that scan
line to ~switch-on~ to a conducting state. If a data voltage
is applied to a data line while an FET in the column
corresponding to the data line is in an "on" state, the pixel
capacitor will charge and store the data voltage, which will
remain present even after the scan line voltage has decreased
to a level sufficient to turn off the FET. Each pixel in the
display may be individually addressed in this manner.
Depending upon the magnitude of the data voltage applied to
the pixel electrode, the optical propertie~ of the liquid
crystal material may be altered. The data voltage magnitude
may be such as to: allow no light transmission through the
pixel (off); allow maximum light transmission throu~h the
pixel (on); or provide an intermediate gray scale level of
light transmission.
A-Si TFTs, for use in LCD devices, are typically
fabricated in an inverted staggered configuration by
depositing and patterning a first layer of metallization to
form the gate of each TFT, simultaneously with the scan lines
which address the FE~s in the LCD. A layer of gate insula-
tion material, such as silicon nitride (SiN), silicon oxide
(SiO) or the like, is deposited over the gate metallization;
a first layer of a-Si is deposited over the gate
insulation/dielectric layer and a second layer of doped a-Si
is deposited over the first a-Si layer. The doped a-Si layer
is patterned to form the source and drain regions of the FET.
One particularly useful form of a field-effect transistor,
having a two-layer gate insulator structure to improve the
FET's structure and electrical characteristics, is disclosed
and claimed in pending application serial no. 07/303,091,
filed January 26, 1989, assigned to the assignee of the
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RD-19,360
present invention,
In any TFT, the gate insulation/dielectric layer(s)
must perform the dual functions of: (1) providing good
electrical performance characteristics when the FET is
operational, such as good mobility of charge carriers and
threshold voltage stability; and (2) providing structural
integrity manifested as high breakdown voltage and low etch
rates during device fabrication. No single material has yet
been found which exhibits all of these desired qualities;
therefore, a tradeoff is typically made between electrical
performance and structural integrity.
The charge mobility in the conduction channel of a
FET determines the switching speed of a FET; therefore, FETs
having high mobilities are required in applications where
fast switching is desired. Also, threshold voltage stability
must be maintained if the device is to operate reliably. The
conduction channel ln a FET is formed in an interface region
between the gate insulation/dielectric layer and the semi-
conductor material layer when the FET is operational; thisinterface region is typically a few hundred angstroms thick
and it is the composition of this region that determines the
electrical performance characteristics of the FET. An a-Si
FET with an insulation/dielectric layer of silicon nitride,
which is deposited by plasma enhanced chemical vapor
deposition ~PECVD) and which is rich in nitrogen ~relative to
the stoichiometric compound of Si3N4), will produce a device
with acceptable electron mobility and threshold voltage
stability. However, a silicon nitride layer which is rich in
nitrogen will typically have poor structural integrity, which
is an important concern in all applications and is
particularly so in the fabrication of complex structures,
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such as LCD de~ices and the like. A nitride layer with poor
structural integrity (rich in nitrogen) will be susceptible
to the formation of structural defects, such as pinholes and
the like which can lower the breakdown voltage and cause
short-circuits between the a-Si layers and underlying
conductive layers. Addi~ionally, a nitride layer rich in
nitrogen will exhibit a high etch rate in etchants such as
buffered hydrofloric acid (BHF) and gaseous mixtures of
carbon tetrafluoride (CF4) and oxygen, relative to the
overlying a-Si layers. High etch rates are undesirable
because the a-Si and SiN layers are sometimes etched in the
same masking step. If the SiN layer etches faster than the
a-Si, the SiN layer will be undercut beneath the a-Si layer;
this undercutting can cause step coverage problems when
subsequent layers of material, such as the source and drain
metallization layer and a passivation layer, are deposited.
A faster SiN etch rate relative to silicon is also
undesirable where design constraints and fabrication
processes require only the silicon to be etched and for the
etch to stop at the underlying nitride layer.
It is accordingly a primary object of the present
invention to provide a thin-film transistor with a novel gate
insulator structure which is not subject to the foregoing
disadvantages.
It is another object of the present invention to
provide a thin-film transistor with a novel gate insulator
structure which has optimum electrical properties and
structural properties.
It is a further object of the present invention
invention to provide a thin-film transistor with a novel gate
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insulator structure which has process compatible etch
properties and a high dielectric strength.
It is yet another object of the present invention
to provide a thin-film transistor that has high charge mobil-
ity and threshold voltage stability.
These and other objects of the invention, together
with the features and advantages thereof, will become
apparent from the following detailed specification when read
with the accompanying drawings in which like reference
numerals refer to like elements.
Summary of the Invention
In accordance with the present invention, a thin-
film field-effect-~ransistor ~TFT) includes a gate metalliza-
tion layer, deposited on a substrate of an insulative
material (such as glass or the like) and patterned to form a
gate electrode. A first layer of silicon nitride ~SiN),
having a thickness between about 1000-3000 angstroms, is
deposited over the gate metallization layer. The first SiN
layer has a silicon-to-nitrogen ~Si:N) concentration ratio ~;
selected to provide a minimum etch rate and a high dielectric
strength. The first SiN layer is preferably deposited by
plasma enhanced chemical vapor deposition (PECVD) and
preferably has a silicon density to provide an optical (or
refractive) index above about 1.87. A second layer of SiN,
having a thickness of about 200 angstroms or less, is
deposited ~as by PECVD) over the first S~N layer; the second
SiN layer has a Sl:N concentration ratio selected to provide
optimum TFT performance, i.e., stability, charge mobility,
threshold voltage stability and the like, and preferably has
a silicon density to provide an optical index of about 1.87
and, therefore, has a lower Si:N ratio and is less dense and
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softer than the first SiN layer. The Si :N concentration
ratios of the first and second SiN la~ers may be controlled
primarily by the gas phase ratio of ammonia-to-silane used
during deposition; the concentration ratio is also a function
of the deposition pressure, the plasma power and substrate
temperature. A first layer of amorphous silicon (a-Si) is
deposited over the second SiN layer and a second layer of a-
Si is deposited over the first a-Si layer and is doped to
preferably have N+ type conductivity. At least the first and
second a-Si layers and possibly the soft second SiN layer are
patterned to form an island structure. The hard first SiN
layer preferably acts as an "etch stop" to prevent any
significant undercutting beneath the a-Si layer, which
undercutting can cause step coverage problems when subsequent
layers of material are deposited over the island structure.
A source/drain metallization layer is deposited over the
island structure and in electrical contact with the second
doped a-Si layer. The source/drain metallization layer is
patterned to form separate source and drain electrodes and to
form an opening in the metallization layer which is aligned
with the underlying gate electrode. The patterned
source/drain metallization layer forms a mask through which
the doped a-Si layer is patterned to form separate source and
drain regions which each partially overlie the gate elec-
trode. In operation, a voltage of proper polarity and magni-
tude applied to the gate electrode will enhance a conductive
channel between the source and drain regions through the
first a-Si layer.
In accordance with the present invention, a liquid
crystal display (LCD) device includes a plurality of pixel
cells each including a TFT structure having a first SiN l~yer
overlying the gate metallization layer and a second SiN layer
disposed between the first SiN layer and a subsequently de-
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posited a-Si layer. The second SiN layer has a silicon
density selected to provide optimum transistor performance
and may have a thickness that is thin relative to the first
SiN layer. The first SiN layer has a silicon d~nsity
selected to provide a high dielectric strength and a minimum
etch rate when etchants such as BHF, CF4 plasmas and the like
are used. A pixel electrode of light transmissive material,
such as indium tin oxide or the like, is deposited and
patterned on the first SiN layer and a source/drain
metallization layer is deposited and patterned to provide a
source electrode and a drain electrode in electrical contact
with a portion of the pixel electrode. A layer of light
transmissive passivation material, such as SiN, silicon oxide
or the like, may be deposited over the pixel cell.
~ e~criDtion o~ he Dra~in~
Figure 1 is a schematic plan view of a portion of a
thin-film transistor driven liquid crystal display device.
Figure 2 is a detailed plan view of a portion of
the LCD device of Figure 1.
Figure 3 is a cross-sectional view of a portion of
a conventional liquid crystal cell of Figure 2 taken along
lines 3-3.
Figure 4 is a schematic diagram of the equivalent
circuit of a liquid crystal cell.
Figures 5-8 are cross-sectional views of a portlon
of a LCD pixel cell showing the various steps of the fabrica-
tion process in accordance with the present invention.
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RD-19,360
Figure 9 is a graph showing the threshold voltage
shift versus optical index for various Si:N concentration
ratios.
Detailed Dercrip~ion of the
Preferred Embodimen~s
The use of thin-film field-effect-transistors
(FETs) as electronic switching means for controlling the
application of voltages to other components is known in the
art. One particular application is to controllably turn on
and off individual picture cells (picture elements or pixels)
of a liquid crystal display (LCD). Figure 1 is a schematic
plan view of a portion of a LCD device 10 which is formed
from an array of a multiplicity of pixels 12. The pixels 12
~are usually arranged in uniform columns and rows to form an
X-Y matrix-type structure. A FET 14 is typically formed with
each pixel 12 to control operation of the light transmissive
(or reflective) characteristics of the pixel. Electrical
signals are communicated by a plurality of X-address lines
16, commonly referred to as gate lines or scan lines, and a
plurality of Y-address lines 18, commonly referred to as
source or data lines, to FETs 14 and pixels 12 for conversion
to a visual signal. Typically, there is one scan line 16 for
each row of pixels and one data line 18 for each column of
pixels. Scan lines 16 usually run in one direction across
the display and data lines 18 typically run in a direction
substantially perpendicular to the scan lines; however, the
~can and data lineq may jog or snake back and forth if the
pixel elements are staggered. Scan lines 16 and data lines
18 traverse each other at locations 20, known as crossovers
and are spaced from each other at crossovers 20 by a layer of
insulation.
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RD-19,360
Referring also to Figure 2, which is a detailed
plan view of a single liquid crystal cell 22 of Figure 1, a
gate electrode 24 and a source electrode 26 of each FET 14
are respectively connected to a scan line 16 and a data line
18 for transferring electrical signals from the scan and data
lines to pixel 12 for conversion to an optical signal. A
drain electrode 28 of each FET 14 is connected to a pixel
electrode 30 fabricated from a light transmissive material,
such as indium tin oxide ~ITO~ and the like.
A cross-sectional view of a conventional FET 14 and
a portion of a pixel 12 are shown in Figure 3. While the
pixel cell portion shown in Figure 3 does not correspond to
structures or processes embodied by the present invention, it
is nonetheless instructive to consider it for the differences
which will become apparent. A layer 32 of light
transmissive, insulative material, such as silicon dioxide
and the like, may be formed on a glass substrate 34. A FET
gate electrode 29, and pixel electrode 30 are formed on
insulati~n layer 32 by known photolithographic techniques. A
layer 36 of silicon nitride (SiXNy) is deposited over gate 24
and a layer 38 of hydrogenated amorphous silicon (a-Si:H) is
deposited over silicon nitride layer 36. Layers 36 and 38
are then patterned by known photolithographic techniques as
shown in ~igure 3. If SiN layer 36 has a low Si to N
concentration ratio selected to provide good electrical
characteristics, i.e., good mobility and threshold voltage
stability, then SiN layer 36 may be undercut by the etchants
used which can cause step coverage problems when subsequent
layers of m3terial are deposited Additionally, a low Si:N
ratio causes an increased probability of structural defects
such as pinholes wh~ch can crea~e short-circuits and reduce
yield. A heavily doped layer 40 of hydrogenated amorphous
silicon is formed and patterned on layer 38 to form source
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region 40a and drain region 4Qb. Regions 40a and 40b
preferably have N+ conductivity. Silicon nitride layer 36
and silicon layers 38 and 40 are preferably deposited by
plasma enhanced chemical vapor deposition (PECVD) which per-
S mits deposition of high quality films, at much lower sub-
strate temperatures than conventional CVD. This low-tempera-
ture process ~urther permits the use of a glass substrate 34.
Metallization for data line 18, source electrode 26
and drain electrode 28 are preferably deposited and patterned
at the same time; source electrode 26 is formed in contact
with both data line 18 and source region 40a, and drain elec-
trode 28 is deposited and patterned in contact with both
drain region 40b and pixel electrode 30. A layer ~2 of
passivation material, such as silicon nitride or the like, is
formed over the FET preferably by plasma deposition. A layer
46 of glass covers the liquid crystal display 10 and is
spaced from the FET structure by a mechanical spacer 47 such
as glass fibers, glass beads or the like. Thus, the FET and
pixel are sandwiched between glass substrate 34 and cover
glass 46. A ground plane electrode 48, which is common to
all pixels in liquid crystal display 10, is formed on cover
glass 46 at a spacing from pixel electrode 30. The volume 50
between electrodes 30 and 48 is filled with liquid crystal
material and cover glass 46 is bonded to glass substrate 34
by a seal (not shown) at the perimeter of liquid crystal dis-
play 10. ~s shown in the cell equivalent circuit of Figure
4, pixel electrode 30 and ground electrode 48 effectively
form a pixel capacitor 52 connected between FE~ 14 and ground
potential.
IA operation, an individual pixel 12 (Figure 4) may
be addressed by applying a scan line voltage of proper polar-
ity and magnitude to scan line 16 to enha~ce a conductive
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RD-19,360
channel 44 (Figure 3) across a-Si:H layer 38, between source
region 40a and drain region 40b. If a data voltage is
applied to data line 18 while the scan line voltage is pre-
sent, then pixel capacitor 52 will charge while the data
voltage is also present and pixel capacitor 52 will store the
charge after the scan line voltage has decreased to a level
sufficient to deplete conductive channel 44 and switch FET 14
to a non-conductive state. This procedure is usually period-
ically repeated to refresh the charge on pixel capacitor 52;
the LCD image is refreshed or updated at video rates, prefer-
ably about every 10-2 seconds or less, to maintain the image
on the LCD and prevent flickering of the display. The quan-
tity of light transmitted through pixel 12 is a function of
the magnitude of the data line voltage applied to pixel elec-
trode 30 and the charge on pixel capacitor 52.
In accordance with the present invention, a FEThaving an improved multiple-layer gate insulation/dielectric
structure is formed by depositing a gate metallization layer
24' (Figure 5) on substrate 34', preferably by chemical vapor
deposition (CVD). This substrate preferably includes a glass
panel 34'a upon which a layer 34'b of light-transmissive
insulation material, such as silicon oxide or the like, has
been deposited. Gate metallization layer 24' is patterned
and etched to produce gate electrode structures, scan lines
and redundant gate metallization material (if desired).
Redundant gate metallization is preferably provided so as to
be eventually disposed beneath data lines 18. Redundant gate
metallization patterns actually comprise individual
electrically isolated island patterns, with gaps therebetween
to permit passage of gate lines 16 (Figure 2), which may be
used to provide electrical circuit redundancy and increased
yield~ In the present invention, gate metal may comprise
aluminum, gold, chromium, titanium and the li~e. In the case
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of titanium, gate metallization layer 24' may ~e plasma
etched in a mixture of carbon tetrafluoride (CF4) and 4
percent oxygen (by weight). Alumlnum gate metallization
material may be etched through the use of solutions such as
PAWN (phosphoric, acetic and wea~ nitric acid solutions).
Figure 5 illustrates a portion of gate metallization layer
24', in the vicinity of an FET island, which corresponds to
the FET gate electrode.
A first layer 54 of SiN having a thickness of about
1000-3000 angstroms is deposited over gate metalliza~ion
layer 24', preferably by PECVD. First SiN layer 54 should
have a silicon-to-nitrogen concentration ratio which is
sufficiently high (rich in silicon) to provide a minimum etch
rate and a high dielectric strength. The density and
hardness of layer 54 will increase with an increase in the
silicon to nitrogen concentration, which will reduce the
probability of structural defects (such as pinholes and the
like) occurring. A second, thin layer 56 of SiN, having a
thickness of about 200 angstroms or less, is deposited
~preferably by PECV~) over the first SiN layer. Second SiN
layer 56 has a silicon-to-nitrogen concentration ratio (Si:N)
which is typically lower than the first SiN layer; the second
layer Si:N concentration ratio is selected to provide a layer
which is rich in nitrogen and therefore exhibits optimum FET
performance, i.e., stability, charge mobility, threshold
voltage stability and the like, when second layer 56
interfaces an amorphous silicon layer to be subsequently
deposited. Since second SiN layer 56 is nitrogen rich
relative to first layer 54 and has a lower Si:N concentration
ratio than first layer 54, second SiN layer 56 also has a
lower density and is softer than first SiN layer 54, which
can result in structural defects; however, this possibility
is of little concern because first SiN layer 54 is optimized
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RD-19,360
to provide the desired structural integrity. The selected
density or Si:N concentration of second SiN layer 56, which
provides optimum electrical characteristics, can be
determined by measuring the optical (or refractive) index of
the layer, i.e., measuring the speed of light in the material
relative to the speed of light in a vacuum. An optical index
of about 1.87 corresponds to a Si:N concentration which
provides optimum electrical performance. To illustrate the
optimum electrical performance of second SiN layer 56 (which
has an optical index of about 1.87), the threshold voltage
(VT) shift was measured for different optical indices (which
correspond to different Si:N concentration ratios). A curve
58 ~shown in Figure 9) was fit to the various points. The
lowest VT shift is seen to be between an optical index of
about 1.86 and 1.88. A higher Si:N concentration will have a
correspondingly higher optical index and a higher VT shift,
but will exhibit slower etch rates either during wet etching
in BHF or during plasma etching in an atmosphere of CF4 and 2
in a plasma barrel etcher. Additionally, the higher optical
index also corresponds to a higher breakdown strength and
fewer pinholes. Thus, first SiN layer 54 should have an
optical index higher than 1.87, preferably about 1.90 or
higher, to provide optimum structural integrity.
Nitride layers 54 and 56 are preferably deposited
by PECVD using ammonia and silane as source gases, although
other gases such as disilane and nitrogen may be used as
well. The Si:N concentration ratios of first SiN layer 54
and second SiN layer 56 may be controlled primarily by the
ammonia-to-silane gas phase ratio used during deposition of
each layer; the concentration ratios may also be affected by
the temperature at which the substrate is maintained during
deposition, the processing pressure and the plasma power but
these later three variables preferably remain constant for
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the deposition of each layer and only the gas phase ratio of
ammonia to silane is changed. The settings for each of the
variables may be different from one deposition apparatus or
system to another, but the optical indices for each layer can
be checked and the deposition equipment can be calibrated
accordingly to provide the desired Si:N concentration ratio
for each layer. The gas phase ratio may vary between about 4
and about 10 to provide the desired Si:N concentration ratio
for each layer; the temperature is preferably about 300 C and
the pressure is preferably about 0.5 torr for a gas phase
ratio between about 4 and about 10.
Referring back to Figure 5, a layer 38' of semicon-
ductor material, preferably amorphous silicon ~a-Si~, is de-
posited by PECVD on SiN layer ~6 and a second layer 40' of
semiconductor material, preferably also a-Si doped to have N+
conductivity, is deposited on first a-Si layer 38'. Semicon-
ductor layers 38' and 40' preferably have a thickness of
about 2000 and 500 angstroms, respectively.
Since the two nitride layers and the two a-Si
layers are deposited by PECVD, the use of a plasma stimulates
gas phase reactions and surface reactions to occur at lower
processing temperatures than would be possible with
traditional CVD methods. The lower processing temperatures
permit the use of glass substrates which are cheaper and are
~5 available in arbitrary areas as compared to single
crystalline silicon substrates. PE~VD also permits the
deposition of the multiple layers sequentially without
breaking vacuum to provide interfaces between the layers
which are substantially free of contaminants, such as oxygen,
carbon and the like.
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At least semiconductor layers 38' and 40' are then
patterned and plasma etched, preferably in HCl gas; although
other plasma etches such as SiCl4, SF6 and CF4 + 2 may also
be used. Second SiN layer 56 may also be plasma etched in
HCl. First SiN layer 54 is not substantially etched because
of its high density and hardness and remains over
substantially the entire surface of the wafer. SiN layer 54
is particularly visible in Figure 6 which also particularly
indicates the early stage of the FET island formation.
Transparent pixel electrodes 30' (Figure 7),
preferably comprising indium tin oxide (ITO), are deposited
and patterned either by etching or by lift off (if an LCD
device is being fabricated). Note that in particular, wet
etching of indium tin oxide is possible at this stage of
fabrication since any gate level metallization is protected
from the indium tin oxide etchant by SiN layer 54.
At this stage of processing, source/drain metal-
lization, such as molybdenum, aluminum or the like, is
deposited over the surface of the substrate, preferably by
sputtering, and etched to form the source/drain and data line
18 patterns. A PAWN solution may be used to etch the
molybdenum or aluminum source/drain metallization. The
resultant structure is shown in Figure 7 in which the
source/drain metallization layer has been etched to produce
source contact elec~rode 26' and drain contact electrode 28',
both in electrical contact with N+ doped a-Si layer 40', as
shown in Figure 7. Subsequently, a portlon of N+ a-Si 40' is
removed from the channel region of the island structure,
using electrodes 26' and 28' as a mask, to form an FET device
with source region 40'a and drain region 40'b. Those skilled
in the art will note that many FET structures are symmetric
with respect to source and drain propertiPs and that in many
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situations, the source and drain connections can be reversed;
such is the case with the present invention as the source and
drain designations are merely for purposes of convenience in
describing the device. The substrate is capped with a layer
60 of passivating material, such as silicon nitride or the
like, preferably deposited by plasma deposition. The
resulting structure is shown in Figure 8. It is noted that
this process eliminates shorts between the gate or scan lines
and the pixel electrodes or data lines due to excess metal or
excess indium tin oxide because they are insulated from one
another by SiN layer 54.
It will be readily understood by those skilled in
the art that the present invention is not limited to the spe-
cific embodiments described and illustrated herein. Differ-
ent embodiments and adaptations besides those shown hereinand described, as well as many variations, modifications and
equivalent arrangements will now be apparent or will be
reasonably suggested by the foregoing specification and draw-
ings, without departing from the substance or scope of the
?0 invention. While the present invention has been described
herein in detail in relation to its preferred embodiments, it
is to be understood that this disclosure is only illustrative
and exemplary of the present invention and is made merely for
purposes of providing a full and enabling disclosure of the
invention. The thin-film transistor structure described
herein is generally applicable and may be useful in other
devices. The structure was merely described with respect to
its application in an LCD device which is only one of many
TFT uses. Accordingly, it is intended that the invention be
limited only by the spirit and scope of the claims appended
hereto.
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