METHOD TO MANUFACTURE DOUBLE-POLY CAPACITORS

METHODE DE FABRICATION DE CONDENSATEURS A DEUX POLYMERES

English Abstract

ABSTRACT
A method a manufacturing integrated circuits including
transistors, capacitors, and resistors, comprises the steps
of forming a first poly layer, which is heavily doped;
forming a dielectric layer over the first poly layer; forming
a second poly layer over the dielectric layer, the second
poly layer being lightly doped; and subsequently further
doping the second poly layer at least in capacitor regions
while masking the second poly layer in resistor regions so as
to heavily dope the second poly layer in the capacitor
regions and thereby improve capacitor linearity while
substantially maintaining the resistivity of the lightly
doped second poly layer in the resistor regions. In this way
capacitors having good linearity can be fabricated at the
same time as small area resistors with good contact
resistance.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A method of manufacturing integrated circuits including
transistors, capacitors, and resistors, comprising the steps
of forming a first poly layer, which is heavily doped;
forming a dielectric layer over said first poly layer;
forming a second poly layer over said dielectric layer, said
second poly layer being lightly doped: and subsequently
further doping said second poly layer at least in capacitor
regions while masking said second poly layer in resistor
regions so as to heavily dope said second poly layer in said
capacitor regions and thereby improve capacitor linearity
while substantially maintaining the resistivity of said
lightly doped second poly layer in said resistor regions.
2. A method of manufacturing integrated circuits as claimed
in claim 1, wherein said subsequent doping takes place
through a mask with windows opened in said capacitor regions
and said regions where metal contacts are to be made.
3. A method of manufacturing integrated circuits as claimed
in claim 2, wherein said mask is also used to apply the
source and drain regions of the transistors.
4. A method of manufacturing integrated circuits as claimed
in claim 3, wherein said subsequent doping is applied by
means of diffusion or ion implantation.
5. A method of manufacturing integrated circuits as claimed
in claim 4, wherein the subsequently doped poly layer is
further activated by rapid thermal processing.
6. A method a manufacturing integrated circuits as claimed
in any of claims 1 to 5, wherein said subsequent further
doping also takes place in said second poly layer in regions

adjacent said resistors to which contacts are to be made to
reduce contact resistance therewith.
7. A method a manufacturing integrated circuits as claimed
in claim 1, wherein a layer of refractory metal silicide is
formed on top of said first poly layer prior to formation of
the dielectric layer.
8. An integrated circuit including transistors, capacitors,
and resistors, comprising a first poly layer, which is
heavily doped; a dielectric layer on said first poly layer; a
second poly layer on said dielectric layer, said second poly
layer being lightly doped in resistor regions and heavily
doped in capacitor regions; whereby capacitor linearity is
improved while the resistivity of said lightly doped second
poly layer in said resistor regions is substantially
maintained.
9. An integrated circuit as claimed in claim 8, wherein said
second poly layer is also heavily doped regions where
contacts are made.
10. An integrated circuit as claimed in claim 8, wherein the
lightly doped portions of said second poly layer have a sheet
resistance of at least 50 ohms/square.

Description

This invention relates to integrated a method of
manufacturing double poly capacitors in integrated circuits,
and integrated circuits manufactured thereby.
Double poly capacitors, i.e. capacitors consisting a pair of
opposed electrodes made of polycrystalline silicon, are
widely used in integrated circuit manufacturing, especially
in analog applications and for switched capacitor circuits.
The use of two poly layers to fabricate capacitors is well
known and has been used since the first 5 micron process
became known about ten years ago.
In a known process, the first poly layer is heavily doped,
either with POC13, ion implantation, or during deposition
(In-Situ Doped). An oxide is then thermally grown on top of
the first poly layer (Poly I) to form the capacitor
dielectric. A second poly layer is deposited to form the top
electrode of the capacitor. If a resistive film is required
to fabricate small resistors, this second layer is lightly
doped .
The use of lightly doped poly II is advantageous in providing
very linear resistors that are small, compared to other
materials. However, the voltage coefficient of the double-
poly capacitor produced by this method is large because of
the difference in doping levels between the two poly layers.
When a voltage is applied across the capacitor, a depletion
layer develops in the second poly film, which affects the
capacitance. Lightly doped poly II also results in high
contact resistance that can affect circuit performance.
The solution to the problem of high voltage coefficlent has
been to use a heavily doped second poly layer. This results
in a low resistance film, which does not permit fabrication
of small area resistors and results in larger die sizes.

An object of the invention is to alleviate the aforementioned
problem.
Accordingly the present invention provides a method of
manufacturing integrated circuits including transistors,
capacitors, and resistors, comprising the steps of forming a
first poly layer, which is heavily doped; forming a
dielectric layer over said first poly layer; forming a second
poly layer over said dielectric layer, said second poly layer
being lightly doped; and subsequently further doping said
second poly layer at least in capacitor regions while masking
said second poly layer in resistor regions so as to heavily
dope said second poly layer in said capacitor regions and
thereby improve capacitor linearity while substantially
maintaining the resistivity of said lightly doped second poly
layer in said resistor regions.
Typically the heavily doped Poly I layer has a sheet
resistance Rs between 15 and 30 ohms/square for a thickness
of 330 nm., and the lightly doped Poly II layer has a sheet
resistance Rs at least 50 and up to 500 or more ohms/square
for a thickness of 250 nm.
A layer of refractory metal silicide can be formed on top of
the first poly layer. The dielectric is then grown and/or
deposited on the refractory layer depending on the type of
material used on top of the first poly layer.
Preferably, the subsequent doping takes place through a mask
with windows opened in the capacitor regions, the mask being
the same mask that is used to fabricate the source and drain
regions of the integrated circuit.
The contact regions for the small area resistors can also be
heavily doped in the same step to improve contact resistance

r~
The invention allows the use of a second lightly doped poly
layer, which gives a much improved voltage coefficient of the
double poly capacitor and a much lower contact resistance for
the resistors.
In another aspect the invention provides an integrated
circuit including transistors, capacitors, and resistors,
comprising a first poly layer, which is heavily doped; a
dielectric layer on said first poly layer; a second poly
layer on said dielectric layer, said second poly layer being
lightly doped in resistor regions and heavily doped in
capacitor regions; whereby capacitor linearity is improved
while the resistivity of said lightly doped second poly layer
in said resistor regions is substantially maintained.
The invention will now be described in more detail, by way of
example only, with reference to the accompanying drawings, in
which:-
Figures la to le show the various stages in the fabricationof in integrated circuit in accordance with one embodiment of
the invention;
Figure 2 shows a portion of an integrated circuit forming a
double poly capacitor; and
Figure 3 shows a portion of an integrated circuit forming a
poly resistor.
Referring to Figure la, a first poly layer 1 is deposited on
an insulator (thick field oxide) 5 which has been previously
grown or deposited on a silicon substrate (Filed oxide 5 is
omitted in Figures lb to le). The layer 1 is normally
heavily doped during deposition, or can be doped
subsequently.

2~23~ ~'2
After patterning with a resist (not shown) and etching, an
oxide layer 2 is thermally grown on the first poly layer 1,
as shown in Figure lb. The oxide layer serves a dielectric
in the finished double poly capacitor.
As shown in Figure lc, a second poly layer 3 is then
deposited undoped on the oxide layer 2. After deposition,
the second poly layer is lightly doped by diffusion, ion
implantation, or during deposition (in-situ doped) to yield a
high final sheet resistance of about 100 ohms per square, or
even greater.
The second poly layer 3 is then patterned, as shown in Figure
ld, and resist ~ spun onto the wafer in preparation for N~
active area implantation to heavily dope the second poly
layer 3.
The heavily doped N+ implantation is normally carried out to
form the source and drain regions of the transistors.
However, in addition to the usual openings, windows are
opened up on top of the second poly layer 3 at locations
where it is desired to increase locally the doping level,
that is over capacitor areas and where resistor contacts to
the second poly layer 3 are to be made (Figure le). The
resist is retained over the sma].l area resistors in order to
mask them during the implantation process.
The N+ implantation can then be performed selectively to dope
simultaneously the N+ active area and the upper plate of the
double poly capacitors and the regions where metal contacts
to the poly II layer are to be made.
Figure 2 shows a poly-poly capacitor fabricated in accordance
with the method of the present invention.
In Figure 2, the second poly layer 3, forming one plate of
the capacitor, lies above the first poly layer 1 and is

~ ~ ~ 3 Iq ~ 2
separated therefrom by the dielectric (not shown in Fig. 2).
During fabrication the second poly layer 3 is surrounded by
window 3a in the source/drain mask (not shown) through which
N+ ion implantation is carried out during formation of the
source/drain of the integrated circuit. The doping of the
second poly layer is enhanced, resulting in increased
conductivity and therefore linearity.
In Figure 3 the second poly layer 3 forms serpentine resistor
3b. A window 3al is formed in the source/drain mask (not
shown) through which N+ ion implantation is carried out
during formation of the source/drain of the integrated
circuit to increase the doping of end regions 3b', where
metal contacts are to be made.
The invention allows double poly capacitors to be fabricated
with good linearity without the need to employ an extra mask.
The additional benefits in terms of contact resistance can
also be obtained without added cost.
The second poly layer 3 can be doped with, for example,
phosphorous and/or arsenic to provide the light level of
doping, and then an N+ diffusion implant, using phosphorus
and/or arsenic, employed to locally increase the doping
level. Alternatively, the second poly layer 3 can be doped
with boron, and P+ diffusion implant, using boron, BF or BF2.
The dielectric layer can be a deposited layer (oxide, or
nitrite), or a combination of thermally grown and deposited
layers (thermal oxide/nitrite/oxide).
Rapid thermal processing treatment can be carried out on the
thus fabricated wafer to further activate the implanted
heavily doped regions in the second poly layer 3.
The invention has general application in the doping of poly
films and integrated circuits, including MOS and bipolar
transistors. It allows a lightly doped second poly layer
c;

with high sheet resistance per square to be employed, while
giving a low voltage coefficient of the double poly
capacitor, a low metal to poly 2 contact resistance without
the need for additional processing.

Representative Drawing