Note: Descriptions are shown in the official language in which they were submitted.
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TITLE OF THE INVENTION
VIDEO SIGNAL DECODER
BACKGROUND OF THE INVENTION
1. Field of the Tnvention
The present invention relates to a video signal
decoder based on the MUSE (Multiple Sub-nyquist Sampling
Encoding) system where the capacity of each frame memory
employed therein can be reduced.
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2. Description of the Prior Art 4~~- ~'~'
Referring first to Fig. 4, a description will be
given on a conventional example (1) of a MUSE-format
video signal decoder which employs two frame memories
each having a delay time of 1-frame period. A parallel
8-bat digital video signal (digital luminance signal)
(A) obtained from an input terminal 1 by three-
dimensional subsampling is supplied via a noise reducer
2 to a first frame memory 3, and a digital video signal
(B) outputted therefrom is supplied to a second frame
memory 4.
As shown in Fig. 5, each of the first and second
frame memories 3 and 4 is cornpased of field memories vMl
and vM2 which are cascade-connected between input and
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output terminals Tl and T2. Each frame memory as a
whole has a capacity of 1125 x 480 x 8 = 4,320,000 bits
(i.e., approx. 4M bits) and a delay time of 2-Field
period (i.e., 1-frame period).
Subsequently, in a subtracter 5. 'the digital video
signal (C) outputted from the frame memory 4 is
subtracted from the digital video signal (A) obtained
from the input terminal 1, and the resultant difference
digital video signal (A - C) is supplied via a bit
compressor 6 to an absolute value converter 7. (The
pixel data arrangement thereof is shown in Fig. g.)
Thus, an absolute-value 2-frame difference signal is
obtained at an output terminal 8 of a 2-frame difference
detector 2FMDK.
The bit compressor 5 is a circuit where an 8-bit
difference digital video signal of -128 - 0 - +127
levels is compressed to a 6-bit difference digital video
signal of -32 - 0 - +31 levels, as shown in Fig. G.
The digital video signals (A), (~) and (C)
represent the pixel data of the present frame, the
preceding frame and the ante-preceding frame,
respectively. The arrangement relationship of the pixel
data on mutually corresponding scanning lines in the
same odd or even field is such that, as shown in Fig. 9,
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the pixel data B is positioned between the pixel data A,
and the pixel data C is positioned between the pixel
data B.
The difference digital video signal (A - C)
outputted from the subtracter 5 is supplied to 'the noise
reducer 2.
The digital video signal (A) obtained from the
noise reducer 2 and the digital video signal (B) from
the first frame memory 3 are supplied to an interframe
interpolator 9, whose output is then~supplied via an
output terminal 10 to an unshown still picture processor
in the MUSE-format video signal decoder.
Now a 1-frame difference detector 1FMDK will be
described below.
The digital video signal (A) from the noise reducer
2 is supplied to a first interpolation filter 11, while
the digital video signal (B) from the first frame memory
3 is supplied to a second interpolation filter 12. In a
first subtracter 13, the digital video signal (B) from
the first frame memory 3 is subtracted from the
interpolated digital signal (A'} obtained from the first
interpolation filter 11, thereby producing a first
difference digital video signal (A' - B). (The pixel
data arrangement thereof is shown in Fig. 9.) Tn a
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second subtracter 14, the interpolated digital video
signal obtained from the interpolation filter 12 is
subtracted from the digital video signal (A) to produce
a second difference digital video signal (A - B'). (The
pixel data arrangement thereof is shown in Fig. 9.) The
first and second difference digital video signals (A' -
B) and (A ° B') are supplied to a multiplexer 15, where
the input signals are combined with each other. And the
output therefrom is supplied via a low-pass filter 16 of
a cutoff frequency 4 MRz to an absolute value converter
17 so as to be converted into an absolute value, whereby
an absolute-value 1-frame difference signal is obtained
from an output terminal 18.
Referring next to Fig. 7, a description will be
given with regard to another conventional MUSE-format
video signal decoder (2) which employs two frame
memories each having a delay time of 1-field period. In
Fig. 7, the same reference numerals and symbols as those
used in Fig. 4 denote the same or corresponding
components, and a repeated explanation thereof is
omitted here. A parallel 8-bit digital video signal (A)
obtained from an input terminal 1 by three-dimensional
subsampling is supplied via a noise redur_er 2 to a
multiplexex 25. The digital video signal (A, B)
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outputted from the multiplexes 25 is supplied to a first
frame memory 3, whose output is then saipplied to a
second frame memory 4. (The pixel data arrangement
thereof is shown in Fig. 9.) The digital video signal
(C, B) outputted from the second frame memory 4 is
supplied to a demultiplexer 29, where the input signal
is separated into the digital video signals (B) and (C).
(The pixel data arrangement of the signal (C, H) is
shown in Fig. 9.)
As shown in Fig. 8, each of the first and second
frame memories 3 and 4 comprises a demultiplexer DMP
connected to an input terminal Tl, field memories VM1,
VM2 supplied with two outputs of the demultiplexer DMP,
and a multiplexes MPX supplied with outputs of the field
memories and connected to an output terminal T2. Each
of the frame memories has a total capacity of 1125 x 480
x 8 = 4,320,000 bits (~i.e., approx. 4M bits) and a delay
time of 1--field period.
Now the constitution of a 2-frame difference
detector 2FMDK will be described below. The digital
video signal (B) obtained from the demultiplexer 29 is
supplied to the multiplexes 25 and then is combined with
the digital video signal (A) outputted from the noise
reducer 2. In a subtracter 30, the digital video signal
_
(C) outputted from the demultiplexer 29 is subtracted
from the digital video signal (A), and a difference
digital video signal (A - C) thus obtained is supplied
to the noise reducer 2 while being supplied also to a
bit compressor 6 which is similar to the aforementioned
bit compressor 6 shown in Fig. 4, whereby bit
compression is executed. The bit-compressed signal is
then supplied to an absolute value converter 7r so that
an absolute value 2-frame difference signal is obtained
from an output terminal 8.
Next the constitution of a 1-frame difference
detector 1FMDK will be described below. The output
digital video signal (A, B) of the multiplexer 25 is
supplied via the output terminal 10 to the still picture
processor while being supplied also to a demultiplexer
26 so as to be separated into the digital video signals
(A) and (B). Subsequently the digital video signal (A)
and the digital video signal (-B) obtained through phase
inversion by a code inverter 27 are supplied to a
multiplexer 28 so as to be combined with each other.
The combined digital video signal (A, -B) is then
supplied via a low-pass filter I6 to an absolute value
converter 17. so that an absolute-value 1-frame
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difference signal is obtained from an output terminal
18.
In each of the conventional examples (1) and (2),
there are needed two frame memories 3 .and 4 each having
a capacity of ~ bits ar so.
OBJECT AND SUMNAR~ OF THE INVENTION
Tt is therefore an obaect of the present invention
to provide an improved MUSE-format video signal decoder
where the capacity of each frame memory employed therein
can be reduced as compared with any known example.
According to one aspect of the present invention,
there is provided a MUSE-format video signal decoder
comprising a first frame memory supplied with an input
digital video signal and having a delay time of 1-.frame
period; a 1-frame difference detector including a first
interpolation filter supplied with the input digital
video signal, a second interpolation filter supplied
with the digital video signal from the first frame
memory, a first subtracter for obtaining the difference
between the output of the first interpolation filter and
the digital video signal outputted from the first grame
memory, and a second subtracter for obtaining the
difference between the input digital video signal and
the output of the second interpolation filter, wherein a
1-frame difference signal is produced in accordance with
the outputs of the first and second subtracters; and a
2-frame difference detector including first and second
bit compressors supplied with the outputs of the first
and second subtracters respectively, a second frame
memory having a delay time of 1-frame period and
supplied with one output of the first bit compressor and
that of the second bit compressor, and an adder for
obtaining the sum of the other outputs of the first and
second bit compressors and the output of the second
frame memory, wherein a 2.-frame difference signal is
produced in accordance with the output of the adder.
According to another objeet of the present
invention, there is provided a MUSE-format video signal
decoder comprising a 1-frame difference detector
including a first interpolation filter supplied with a
first digital video signal, a second interpolation
filter supplied with a second digital video signal as an
input digital video signal, a first subtracter for
obtaining the difference between the output of the first
interpolation filter and the second digital video
signal, a second subtracter far obtaining the difference
between the first digital video signal and the output of
the second interpolation filter, and first and second
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bit compressors supplied with the outputs of the first
and second subtracters respectively, wherein a 1-frame
difference signal is produced in accordance with the
outputs of the first and second bit compressors; and a
2-frame difference detector including a ~-frame memory
having a delay time of 2-frame period and supplied with
one output of the first bit compressor and that of the
second bit compressor, and an adder for obtaining the
sum of the second digital video signal outputted from
the 2-frame memory and the other outputs of the first
and second bit compressors, wherein a 2-frame difference
signal is produced in accordance with the output of the
adder.
The above and other features and advantages of the
present invention will become apparent from the
following description which will be given with reference
to the illustrative accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Figs. l, 2 and 3 are block diagrams showing
exemplary embodiments (1), (2) and (3) of the present
invention, respectively;
Fig. 4 is a block diagram of a conventional example
(1) ;
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Fig. 5 is a block diagram showing the structure of
a frame memory employed in the example of Fig. 4;
Fig. 6 graphically shows the characteristic of bit
compression;
Fig. ? is a block diagram of another conventional
example (2);
Fig. 8 is a block diagram showing the structure of
a frame memory employed in the example of Fig. 7; and
Fig. 9 illustrates arrangements of pixel data.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Hereinafter an exemplary embodiment (1) of the
present invention will be described in detail with
reference to Fig. 1. In the embodiment (1) which is an
improvement of the conventional example (1) shown in
Fig. 4, each of first and second frame memories 3, ~ has
the aforementioned structure of Fig. 5. Tn Fig. l, the
same reference numerals and symbols as those used in
Fig. 4 denote the same or corresponding components, and
a repeated explanation thereof is omitted hexe.
First a description will be given on a ~-frame
difference detector 2FMDK which is different in
constitution from the one employed in the conventional
example. More specifically, difference digital video
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a
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signals (A' -B) and (A - B;) outputted from first and
second subtracters 13, 14 are supplied to bit
compressors 21, 22 which are similar to the known ones
described with reference to Fig. 6, so that such
signals are compressed to parallel 6-bit difference
digital signals (A' - B) and (A - B'), which are then
supplied respectively to a second frame memory 4 and an
adder 23. In the meantime, a difference digital video
signal (B' - C) from the frame memory 4 is supplied also
to the adder 23. In the adder 23, the compressed
difference digital video signal (B' - C) outputted from
the frame memory 4 is added to the compressed difference
digital video signal (A - B') outputted from the bit
compressor 22, to thereby obtain a compressed difference
digital video signal (A - C): this signal is supplied
to a noise reducer 2 while being also supplied to an
absolute value converter 7 so as to be converted into an
absolute value, whereby an absolute-value 2-frame
difference signal is obtained at an output terminal 8.
Since the 2-frame difference detector 2FMDK is so
constituted as mentioned, it becomes possible to reduce
the capacity of the second frame memory 4 to 1125 x 480
x 6 = 3,240,000 bits (i.e., approx. 3M bits). Meanwhile
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the capacity of the first frame memory ~ is equal to
that of the conventional example.
Referring next to Fig. 2, an exemplary embodiment
(2) of the present invention will be described below.
In the embodiment (2) which is an improvement of the
conventional example (2) shown in Fig. 7, each of first
and second frame memories ~, 4 have the aforementioned
structure of Fig. ~. In Fig. 2, the same reference
numerals and symbols as those used in Fig> 7 denote the
same or corresponding components, and a repeated
explanation thereof is omitted here.
A digital video signal (B) outputted from a
demultiplexer 29 serves as a first digital video signal,
and an input digital video signal (A) from a noise
reducer 2 serves as a second digital video signal. The
first digital video signal (B) is supplied to a first
interpolation filter 11, while the second digital video
signal (A) is supplied to a second interpolation filter
12. In a first subtracter 13, the output of the first
interpolation filter 11 is subtracted from the second
digital video signal (A). And in a second subtracter
14, the first digital video signal is subtracted from
the output of the second interpolation filter 12.
Subsequently the first and second difference digital
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2~D~~3~~~
video signals (A - B') and (A' - B) outputted from the
first and second subtracters 13, 14 are supplied
respectively to first and second bit compressors 21, 22
which are similar to those mentioned with reference to
F'ig. 4, whereby bit compression is executed.
The 1-frame difference detector 1FMDFC is so
constituted as follows. The outputs of the bit
compressors 2l, 22 are supplied to a multiplexes 15 so
as to be combined with each other, and then the combined
output therefrom is supplied via a low-pass filter 16 to
an absolute value converter 17, so that an absolute-
value 1-frame difference signal is obtained from an
output terminal 18.
Next the constitution~of the 2-frame difference
detector 2FMDK will be described below. The second
digital video signal (input digital video signal}
obtained from the noise reducer 2 and the output of the
second bit compressor 22 are supplied to a multiplexes
33 so as to be combined with each other, and the
combined digital video signal (A, A' - B) outputted
therefrom is supplied to a cascade-connected circuit of
the first and second frame memories 3, 4 to thereby
obtain a digital video signal (B' - C, B), which is then
supplied to a demultiplexer 29 so as to be separated
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~~~~~~
into the digital video signals (B) and (H' - C). The
digital video signal (B) thus separated is the
aforementioned first digital video signal. zn an adder
30, the compressed difference digital video signal (A -
B') from the first bit compressor 21 is added to the
difference digital video signal (B' - C) separated by
the demultiplexer 29, so that a difference digital video
signal (A - C) is obtained. This signal is supplied to
the noise reducer 2 while being supplied also to the
absolute value converter ? so as to be converted into an
absolute value, whereby an absolute-value 2-frame
difference signal is obtained at an output terminal 8.
Due to such constitution of the 2-frame difference
detector 2FMDK, it becomes possible to reduce the
capacity of each of the first and second frame memories
3 , 4 to ( 2 x 1125 x 480 x 8 - 1125 x 480 x 2 ) : 2 =
(1125 x 480) (2 x 8 - 2) - 2 = 3,?80,000 bits (i.e.,
approx. 3.5M bits).
Now a description will be given on another
embodiment (3) of the present invention with reference
to Fig. 3. Since the embodiment (3) of Fig. 3 is mostly
similar to the aforementioned embodiment (1) of Fig. 1,
any components corresponding to those used in the
embodiment (1) of Fig. 1 are denoted by the same
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reference numerals or symbols, and a repeated
explanation thereof is omitted here.
The aforementioned embodiment (1) of Fig. 1
represents an exemplary case where the frame memory 4
employed therein has a capacity of approximately 3M
bits. However. in the embodiment (3) of Fig. 3, the
frame memory 4 has a capacity of approximately 4M bits,
and the entire capacity is used in a freeze mode or a
still-picture broadcast receiving mode.
In the example of Fig. 3, three selector switches
SWI, SW2 and SW3 are provided. The selector switch SW1
has a movable contact m and stationary contacts ~, b, c;
and each of the selector switches SW2 and SW3 has a
movable contact a and stationary contacts a, b. The
movable contact m is selectively chargeable to the
stationary contacts a, b, c or the stationary contacts
a, b in a manner described below.
Switch SWl
Stationary contact a: In freeze mode; after
complete storage of 4 fields
of digital video signal in
first and second frame
memories 3, ~
Stationary contact b: In normal mode
__1~_..
Stationary contact c: Upon occurrence of dropout
Switch SW2
Stationary contact a: In freeze made
Stationary contact b: In normal mode
Switch SW3
Stationary contact a: In freeze mode
Stationary contact b: In normal mode
In the switch SW1: the movable contact m is
connected to one input of the noise reducer 2; the
stationary contact a is connected to the output of the
second frame memory 4; the stationary contact b to the
input terminal 1; and the stationary contact c to the
output of the second interpolation filter 12.
In the switch SW2: the movable contact a is
connected to the other input of the noise reducer 2; the
stationary contact a to the input terminal 3Q to which
"0" is inputted continuously; and the stationary contact
b to the output of the adder 23.
end in the switch SW3: the movable contact m is
connected to the input of the second frame memory 4; the
stationary contact a to the output of the first frame
memory 3; and the stationary contact b to the output of
the first bit compressor 21.
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A 2-bit signal from an input terminal 35 is
additionally fed to the stationary contact b of the
switch SW3 and, after a delay of 1-frame period, the 2-
bit signal is supplied from the second memory 4 to an
output terminal 36. Such input terminal 35 and output
terminal 36 are used for the signal processing by a
motion detector.
Now a description will be given on the operation of
the decoder in the embodiment (3) of Fig. 3. In a
normal mode, the respective movable contacts m of the
three switches SW1, SW2 and SW3 are connected to the
stationary contacts b to thereby form the circuit
configuration shown in the embodiment (1) of Fig. 1.
In a freeze mode, first the movable contacts m of
the switches SW2 and SW3 are changed from the stationary
contacts b to the stationary contacts a. However, the
movable contact m of the switch SW1 is still left
connected to the stationary contact b. And upon
complete storage of a 4-field or 2-frame digital video
signal in the first and second frame memories 3 and 4,
the movable contact m of the switch SW1 is changed from
the stationary contact b to the stationary contact a.
In this stage of the operation, the absolute-value 2-
frame difference signal obtained from the output
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terminal 8 is not utilized or detected since it is
insignificant.
Tn response to occurrence of a dropout (during
reproduction of MUSE-format signal from a recording
medium), the movable contact m of the switch SW1 is
changed from the stationary contact b to the stationary
contact c, so that the interpolated digital video signal
of the preceding frame is inputted to the noise reducer
2. In such a case, it has been customary heretofore to
use the digital video signal of the ante-preceding frame
upon occurrence of a dropout.
According to the present invention, as described
above, it becomes possible to reduce the capacity of
each frame memory employed in a MUSE-format video signal
decoder where a 1-frame difference signal and a 2-frame
difference signal are obtained.
s
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