Note: Descriptions are shown in the official language in which they were submitted.
- 1 - RD-18,938
~_~
c
This application is related to application Serial
No. (RD-20,382~, entitled "A High Density
Interconnect Structure Including a Spacer Structure and a
Gap~, by H.S. Cole et al., application Serial No.
(RD-20,055), entitled "High Temperature Polyether Imide
Compositions and Method of Making" by J.H. Lupins~i et al.,
and application Serial No. (RD-20,487), filed
, entitled, "Multiple Lamination High Density
Interconnect Process and Structure Employing a Variable
Crosslinking Adhesive", by T.B.Gorczyca et al. t each of which
is incorporated herein by reference in its entirety.
~a~k~round Qf th~ InyentiQn
~L;iQ~
The present invention relates to the field of high
density interconnect structures for interconnecting ~ `
electronic components, and more part:icularly, to such
structures employing more than one layer of conductors.
~k9~9u~d lnfo~ iQn
A high density interconnect (HDI~ structure or
system which has been developed by General Electric Company
offers many advantages in the compact assembly of electronic
systems. For example, an electronic sy~tem such as a micro
computer which incorporatçs 30-50 chips can be fully
assembled and interconnected on a single substrate which is 2
inch lon~ by 2 inch wide by .050 inch thick. Even more
important, this interconnect structure can be disassembled
for repair or replacement of a faulty component and then
... . . . . . . ..
: : . :, . . :
: ; . .,, . ~ ,. :
" .:, . .` ` ,
., .. '
- 2 - RD-18,938
reassembled without slgnificant risk to the good components
lncorporated within the system. This is particularly
important where as many as 50 chips having a cost of as much
as $2,000.00, each, may be incorporated in a single system on
S one substrate. This repairability is a substantial advance
over prior connection systems in which reworking the system
to replace damaged components was either impossible or
involved substantial risk to the good components.
Briefly, in tnis high density interconnect
structure, a ceramic substrate such ~s alumina which may be
100 mils thick and of appropriate size and strength for the
overall system, is provided. This size is typically less
than 2 inches square, but may be made larger or smaller.
Once the position of the various chips has been specified,
individual cavities or one large cavity having appropriate
depth at the intended locations of differing chips, is
prepared. This may be done by starting with a bare substrate
having a uniform thickness and the desired size.
Conventional, ultrasonic or laser milling may be used to form
the cavities in which the various chips and other components
will be positioned. For many systems where it is desired to
place chips nearly edge-to-edge, a c;ingle large cavity is
satisfactory. That large cavity may typically have a uniform
depth where the semiconductor chips have a substantially
uniform thicknes~. Where a particularly thick or a
particularly thin component will be placed, the cavity bottom
may be made respectively deeper or shallower to place the
upper surface of ~he corresponding component in subs~antially
the same plane a~ the upper surface of the rest of the
components and the portion of the substrate which surrounds
the cavity. The bottom of the cavity is then provided with a
thermoplastic adhesive layer which may preferably be
polyetherimide resin available under the trade name ULTEM~
6000 from the General Electric Company. The various
components are then placed in their desired locations within
:
,. : :~
,. ~: . :
3 . 3 ~ ~
- 3 - RD-18,338
the cavity, the entire structure is heated to about 300C
which is above the softening point of the ULTEM~
polyetherimide (which is in the vicinity of 235 C) and then
cooled to thermoplastically bond the individual components to
the substrate. Thereafter, a polyimide film which may be
Kapton~ polyimide, available from E.I. du Pont de Nemours
Company, which is 20, 0005-0.003 inch ~z12.5-75 microns) thick
is pretreated to promote adhesion by reactive ion etching
(RIE), the substrate and chips are then coated with ULTEM~
1000 polyetherimide resin or another thermoplastic and the
Kapton film is laminated across the top of the chips, any
other components and the substrate with the ULTEM~ resin
serving as a thermoplastic adhesive to hold the xapton~ in
place. Thereafter, via holes are provided (preferably by
laser drilling) in the Kapton~ and ULTEM~ layers in alignment
with the contact pads on the electronic components to which
it is desired to make contact. A metallization layer which
is deposited over the Kapton~ layer extends into the via
holes and makes electrical contact to the contact pads
disposecl thereunder. This metallization layer may be
patterned to form individual conductors during the process of
depositing it or may be deposited as a continuous layer and
then patterned using photoresist and etching. The
photoresist is preferably exposed using a laser to provide an
accurately aligned conductor pattern at the end of the
process. Alternatively, exposure through a mask may be used.
Additional dielec~ric and metallization layers are
provided as required in order to provide all of the desired
electrical connections among the chips. Any misposition of
the individual electronic components and their contact pads
is compensated for by an adaptive laser lithography system
which is the subject of some of the Patents and Applications
which are listed hereinaf~er.
This high density interconnect structure provides
many advantages. Included among these are the lightest
.
,,J ~ C,~
- 4 - RD-18,938
weight and smallest volume packaqing of such an electronic
system presently available. A further, and possibly more
significant advantage of this high density interconnect
structure, is the shoxt time required to design and fabricate
a system using this high density interconnect structure.
Prior art processes require the prepackaging of each
semiconductor chip, the design of a multilayer circuit board
to interconnect the various packaged chips, and so forth.
Multilayer circuit boards are expensive and require
substantial lead time for their fabrication. In contrast,
the only thing which must be specially pre-fabricated for the
HDI system is the substrate on which the individual
semiconductor chips will be mounted. This substrate is a
standard stoc~ item, other than the requirement that the
substrate have appropriate cavities therein for the placement
of the semiconducto~ chips so that the interconnect surface
of the various chips and the substrate will be in a single
plane. In the HDI process, the required cavities may be
formed in an already fired ceramic substrate by conventional
or laser milling. This milling process is straightforward
and fairly rapid with the result th~t once a desired
configuration for the substrate has been established, a
corresponding physical substrate can be made ready for the
mounting of the semiconductor chips in as little as 1 day and
typically 4 hours for small quantit:Les as are suitable for
research or prototype systems to confirm the design prior to
quantity production.
The process of designing an interconnection pattern
for interconnecting all of the chips and components of an
electronic system on a qingle high densi~y interconnect
substrate normally takes som~where between one week and five
weeks. Once that interconnect structure has been defined,
assembly of the system on the substrate may begin. First,
the chips are mounted on the substrate and the overlay
structure is built-up on top of the chips and substrate, one
~S~ 3.~ .L
- 5 - RD-18,938
layer at a time. Typically, the entire process can be
finished in one day and in the event of a high priority rush,
could be completed in four hours. Consequently, ~his high
density interconnect structure not only results in a
substantially lighter weight and more compact package for an
electronic system, but enables a prototype of the system to
be fabricated and tested in a much shorter time than is
required with other packaging techniques.
This high density interconnect structure, methods
of fabricating it and tools for fabricating it are disclosed
in U.S. Patent 4,783,695, entitled "Multichip Integrated
Circuit Packaging Configuration and Method" by C.W.
Eichelberger, et al.; U.S. Patent 4,835,704, entitled
"Adaptive Lithography System to Provide High Density
Interconnect" by C.W. Eichelherger, et al.; U.S. Patent
4,714,516, entitled "Method to Produce Via Holes in Polymer
Dielectrics for Multiple Electronic Circuit Chip Packaging"
by C.W. Eichelberger, et al.; U.S. Patent 4,780,177, entitled
"Excimer Laser Patterning of a Novel Resist" by R.J.
Wojnarowski et al.; U.S. Patent Appl.ication Serial No.
249,927, filed September 27, 1989, entitled "Method and
Apparatus for Removing Components Bonded to a Substrate" by
R.J. Wojnarowski, et al.; U.S. Patent: Application Serial No.
310,149, filed February 19, 1989, ent:itled "Laser Beam
Scanning Method for Forming Via Holes~ in Polymer Materials"
by C.W. Eichelberger, et al.; U.S. Patent Application Serial
No. 312,798, filed February 21, 1989, entitled "High Density
Interconnect Thermoplastic Die Attach Material and Sol~ent
Die Attachm~nt Processing" by R.J. Wojnarowski, et al.; U.S.
Patent Applicatlon Serial No. 283,095, filed December 12,
1988, entitled "Simplified Method for Repair of High Density
Interconnect Circuits" by C.W. Eichelberger, et al.; U.S.
Patent ApplicAtion Serial No. 305,314, filed February 3,
1989, entitled "Fabrication Process and Integra~ed Circuit
Test Structure" by H.S. Cole, et al.; U.S. Patent Application
- ~
,~ ,: , ~, -.
- 6 - RD-18,938
Serial No. 250,010, filed September 27, 1988, entitled "High
Density Interconnect With High Volumetric Efficiency~ by C.W.
Eichelberger, et al.; U.S. Patent Application Serial No.
329,478, filed March 28, 1989, entitled "Die Attachment
Method for Use in High Density Interconnected Asse~blies~' by
R.J. Wojnarowski, et al.; U.S. Patent Application Serial No.
253,G20,filed October 4, 1988, entitled "Laser Interconnect
Process" by H.S. Cole, et al., U.S. Patent Application Serial
No. 230,654, filed August 5, 1988, entitled "Method and
Configuration for Testing Electronic Circuits and Integrated
Circuit Chips Using a Removable Overlay Layerl' by C.W.
Eichelberger, et al.; U.S. Patent Application Serial No.
233,965, filed August 8, 1988, entitled ~'Direct Deposition of
Metal Patterns for Use in Integrated Circuit Devices~' by Y.S.
lS Liu, et al.; U.S. Patent Application Serial No. 237,638,
filed August 23, 1988, entitled "Method for Photopatterning
Metallization Via UV Laser Ablation of the Activator" by Y.S.
Liu, et al.; U.S. Patent Application Serial No. 237,685,
filed August 25, 1988, entitled "Direct Writing of Refractory
Metal Lines for Use in Integrated C:Lrcuit Devices" by Y.S.
Liu, et al.; U.S. Patent Application Serial No. 240,367,
filed August 30, 1988, entitled "Mel:hod and Apparatus for
Packaging Integrated Circuit Chips Employing a Polymer Film
Overlay Layer" by C.W. Eichelberger" et al.; U.S. Patent
Application Serial No. 342,153, filed April 24, 1989,
entitled "Method of Processing Siloxane-Polyimides for
Electronic Packaging Applications" by H.S. Cole, et al.; U.S.
Patent Application Serial No. 289,944, filed Decem~er 27,
1988, entitled "Selective Electrolytic Deposition on
Conductive and Non-Conductive Substrates" by Y.S. Liu, et
al.; U.S. Patent Application Serial No. 312,536, filed
February 17, 1989, en~itled 1'Method of 8Onding a Thermoset
Film to a Thermoplastic Ma~erial to Form a Bondable Laminate"
by R.J. Wojnarowski; U.S. Patent Application Serial No.
363,646, filed June 8, 1989, entitled "Integrated Circuit
... ~ . ~' ' '': ~ .,
;;~. i ;~ ' ~3 ~) ~' L.5
- 7 - RD-18,938
Packaging Configuration for Rapid Customized Design and
Unique Test Capability" by C.W. Eichelberger, et al.; U.S.
Patent Application Serial No. 07/459,844, filed January 2,
1990, entitled "Area-Selective Metallization Process" by H.S.
Cole, et al.; U.S. Patent Application Serial No. 07/457,023,
filed December 26, 1989, entitled "Locally Orientation
Specific Routing System" by T.R. Haller, et al.; U.S. Patent
Application Serial No. 456,421, filed December 26, 1389,
entitled "Laser Ablatable Polymer Dielectrics and Methods" by
H.S. Cole, et al.; U.S. Patent Application Serial No.
454,546, filed December 21, 1989, entitled "Hermetic High
Density Interconnected Electronic System" by W.P. ~ornrumpf,
et al.; U.S. Patent Application Serial No. 07/457,127, filed
December 26, 1989, entitled "Enhanced Fluorescence Polymers
and Interconnect Structures Using Them" by H.S. Cole, et al.;
U.S. Patent Application Serial No. 454,545, filed December
21, 1989, entitled "An Epoxy/Polyimide Copolymer Blend
Dielectric and Layered Circuits Incorporating It" by C.W.
Eichelberger, et al.; Application Serial No. 07/504,760,
filed April 5, 1990, entitled, "A Building Block Approach to
Microwave Modules", by W. P. Kornrumpf et al.; Application
Serial No. 07/504,821, filed April 5, 1990, entitled, "HDI
Microwave Circuit Assembly", by ~. P. Kornrumpf, et al.;
Application Serial No. 07/504,750 filed April 5, 1990,
entitled, "An Ultrasonic Array With a High Den~ity of
Electrical Connections", by L. S. Smith, et al.; Application
Serial No. 07/504,303, filed April 5, 1990, entitled,
"Microwa~e Component Test Method and Apparatus", by W . P .
Kornrumpf, et al.; Application Serial No. 07/504,753, filed
April 5, 1990, entitled, "A Compact High Densi~y
Interconnected Microwave System", by w. P. Kornrumpf;
Application Serial No. 07/504,769, filed April 5, 19909
entitled, "A Flexible High Density Interconnect Structure and
Flexibly Interconnected System" by C. W. Eichelberger, et
al.; Application Serial No. 07/504,751, filed April 5, 1990,
.
! ~
., ~ :
,
'' ~ '''" '. ' ~-
; ~ ~ 3 3 ~;
- 8 - RD-18,938
entitled, "Compact, Thermally Efficient Focal Plane Array and
Testing and Repair Thereof", by W. P. Kornrumpf, et al.
Application Serial No. 07/504,749, filed April 5, 1990,
entitled, "High Density Intercon~ect Structure wi~h Top
Mounted Components", by R. J. Wojnarowski, et al.;
Application Serial No. 07/504,770, filed April 5, l990r
entitled, "A High Density Interconnect Structure Including a
Chamber", by R. J. Wojnarowski, et al.; and Appllcation
Serial No. 07/504,748, filed April 5, 1990, entitled,
~'Microwave Component Having Tailored Operating
Characteristics and Method of Tailoring" by W. P. ~ornrumpf,
et al. Each of these Patents and Patent Applications is
incorporated herein by reference.
Any additional dielectric layers which are required
for isolation between the first metalli~ation layer and any
subsequent metallization layers or for prevention of short
circuits due to contact with external conductors are formed
by spinning on or spraying on a solvent solution of a desired
thermoplastic dielectric material. The structure is then
baked to drive off the solvent in order to leave a solvent-
free dielectric layer. Alternative:Ly, in accordance with
U.S. Patent Application Serial No. 454,545, entitled, "An
Epoxy/Polyimide Copolymer Blend Dielectric and Layered
Circuits Incorporating It" a siloxane-polyimide/epoxy blend
may be spun-on, dried and cured to pro~ide this dielectric
layer. Thereafter, via holes are formed as n~eded and a
patt~rned metallization layer is formed thereover which is
disposed in ohmic contact with underlying metal in the via
holes. If needed, further dielectric and metallization
layers are formed thereover in a similar manner.
Unfortunately, there are a limited number of diPlectric
materials which are suitable for use as these upper
dielectric layers because of all of the material properties
they must exhibit. No~ only must the dielectric material be
available as a spin-on or spray-on solution, it must also
. ~ . 3 ~
- 9 - RD-18, 938
provide good adhesion to the underlying dielectric and
metallization and to the material of any overlying
metallization or dielectric layer which may subsequen~ly be
formed thereon and it should be inherently laser ablatable or
it should be rendered laser ablatable in accordance with U.S.
Patent Application Serial No. 456,421, entitled, "Laser
Ablatable Polymer Dielectrics and Methods".
By a thermoplastic polymer material, we mean a
polymer material which after multiple cycles of heating and
cooling substantially retains its initial melting point or
glass transition temperature. That is, no substantial cross-
linking of the material takes place during the heating,
melting and resolidification process. Such polymers are
suitable as adhesive layers for bonding higher temperature
materials, including polymers to substrates and may also
themselves be used as layers to be bonded to substrates
through the use of lower temperature adhesive layers. The
glass transition temperature of a polymer is the temperature
above which the viscosity of the polymer decreases greatly,
thereby allowing the polymer to flow and also to bond to
other materials. When cooled below this glass transition
temperature, the thermoplastic polymer "resolidifies" and
remains adherent to objects with which it is in intimate
contact. By a thermoset polymer material, we mean a polymer
material in which cross-linking takles place the first time it
is heated or during its preparation process, such that the
material either no longer melts or ~nelts at a much higher
temperature than it did prior to itq initial heating or its
formation, as the case may be.
While the use of spin-on or spray-on dielectric
layers for the second and higher dielectric layers of a high
density interconnect structure is effec~ive, it has a number
of potential drawbacks and process complications. In
particular, such dielectric layers must be baked to drive off
their solvent. The baking time and temperature profiles
r 3 ~ L
- 10 - RD-18,938
involved can adversely affect some electronic components.
Further, in some situations, there is poor adhesion between
adjacent dielectric layers. In other situations, excessive
stress in the dielectric layers or at the interface between
S adjacent dielectric layers can adversely affect the quality
and reliability of a high density interconnect structure.
During the coating of further dielectric layers, the solvent
vehicle tends to redissolve the surface portion of an already
formed, unreacted, thermoplastic dielectric layer on which it
is disposed. While this tends to improve adhesion, it can
also result in excessive interfacial stress and cracking or
crazing of the dielectric layers which renders the structure
unusable.
There are known techniques for using thermose~
materials as adhesives in the formation of multilayer printed
circuit boards. These include spinning on a precursor of a
thermoset material and reacting it in place to form a
thermoset dielectric layer. Once such a layer has reacted,
it is no longer soluble in the solvent which is used in
forming the next layer with the result that damage to
underlying layers does not occur during the formation of
subsequent layers. Such materials are available from
Sheldahl Corporation.
Another thermoset technique is the type of laminate
used in making laminated circuit boards. These include the
copper di~lectric laminate available under the trademark
Pyrolux~ from Dupont. These systems use acrylate adhesives
which become thermoset a~ a curing temperature of about 135C
Unfortunately, acrylate adhesives are not considered
suf~iciently thermally table for use in most Aigh density
interconnect structures of the type to which the present
invention is directed and once reacted ger.erally don't
solvent at all. In partîcular, it is considered desirable to
be able to operate these high density interconnect structure
systems in the vicinity of 200~C or higher. Acrylates are
?
" ~_t 3 ~ i~
~ RD-18,538
not considered usable above 150C. Epoxies also exhibit
thermal instabilities which prevent their use at these
temperatures. In particular, most epoxies turn tan a~ 150C
and turn black at 180C.
Printed circuit boards made by either of these
techniques cannot be disassembled for repair and most of
those printed circuit boards which are faulty must be
discarded. Printed circuit boards of whatever type are fully
tested prior to mounting expensive components thereon.
Consequently, expensive chips are not committed to faulty
printed circuit boards. While this lack of repairability is
a disadvantage, it is more than offset for printed circuit
board applications by the combination of relatively high
testing yield and the high durability the thermoset structure
imparts to the circuit board.
While use of a thermoset structure is beneficial in
the printed circuit board art, the use of such thermoset
systems is unacceptable in a high density interconnect
structure of the type to which this invention is directed
because the expensive chips are put: in place before the
interconnection structure is built. As a result, any fault
in a thermoset high denqity interconnect structure would
require scxapping not only of the interconnection structure
itself, but all of the chips as weLl. Thus, the conversion
of a high density interconnect st m cture of the type
described above into one having a thermoset structure is not
a solution to the problems associated with the formation of
multilayered high dPnsity interconnect structures
The use of multiple thermoset dielectric layers
which are laminated to the structure using a thermoplastic
adhesive to provide such a multilayer structure in which each
dielectric layer includes a thermoset upper sublayer and a
thermoplastic lower sublayer as discussed in U.S. Patent
4,783,695 has not been implemented because of the tendency
for the early laminated layers to shift, deform or otherwise
' ~ '` t
':
- 12 - RD-18,938
change during the lamination of subsequent layers in a way
which breaks via connections between layers.
This problem should be at least partially solved by
the multiple lamination process taught in related application
Serial No. (RD-20,487), entitled, "Multiple
Lamination High Density Interconnect Process and Structure
Employing a Variable Crosslinking Adhesive", since that
process employs a crosslinking adhesive to bond a thermoset
or high temperature thermoplastic laminated layer over each
metallization layer. However, that multilayer structure
itself is not repairable.
Consequently, an alternative process for providing
additional dielectric layers which avoids the problems
associated with multiple layers of spun-on thermoplastic
dielectrics is desirable.
Accordingly, a primary object of the present
invention is to provide upper layer dielectrics in a high
density interconnect structure by a process which avoids
solvent deposition and baking of those dielectric layers.
Another object of the present invention is to
provide a planar multi-laminated high density interconnect
structure whose fabrication avoids the problem of via
interconnection de~tructlon during fabrication.
Another object of ~he present invention is to
provide a planar multi-laminated high density interconnect
structure which is laminated using progressively lower Tg
thermoplastic adhesives.
Another object of the present invention is to
provide greater versatility and variety in high density
interconnect s~ruc~ures, the materialq of which they are
fabricated and th~ process of fabricating them.
Another object of the present invention is to
provide repair for each laminated layer in a high density
- 13 - RD-18,938
interconnect structure without the need for total dielectric
and interconnect removal.
$u~mary of ~b~InYentlQ~
The above and other objects which will become
apparent from the specification as a whole, including the
drawings, are accomplished in accordance with the present
invention by using multiple laminations to provide the
dielectric layers in a high density interconnect structure
through tlse of different adhesives in the different
laminating steps with each successive laminating step
employing a thermoplastic adhesive having a lower Tg than the
thermoplastic adhesive employed in the preceding lamination
step and being performed at a low enough temperature that
previous dielectric layers are not adversely affected.
In accordance with one embodiment of the invention,
a high density interconnect structure is fabricated by
laminating a first dielectric film over the electronic
components using a first thermoplastic adhesive having a
first glass transition temperature (Tgl), forming via holes in
that dielectric layer in alignment with the contact pads to
which contact is to be made, forming a patterned
metallization layer on top of that first dielectric layer,
laminating a second dielectric film over the first
metallization layer and the exposed portion~ of the first
dielectric layer by employing a second thermoplastic adhesive
having a second glass transition temperature Tg2 which is
lower than Tg1. This second lamination step is carried out at
a temperature which is low enough that via connections
between the fir~t metallization layer a~d contact pads on the
electronic components are neither destroyed nor o~herwise
adversely affected. After completion of the second
lamination step, via holes are formed in ~he second
dielectric layer in ali~nment with conductors to which it is
desired to form electrical contacts. These conductors may be
.
! .
' ~ ' ~ ~ '' ' ',
- 14 - ~D-18,938
conductors of the first metallization layer or contact pads
of the electronic components. A second metallization layer
i3 then formed over the second dielectric layer and patterned
appropriately. If more conductive layers are required,
additional dielectric films may be laminated to the structure
with still lower Tg adhesives and appropriate conductive
layers may be formed thereover.
Bri~ ~e~sriatiQn_~_ ~
The subject matter which is regarded as the
invention is particularly pointed out and distinctly claimed
in the concluding portion of the specification. The
invention, however, ~oth as to organization and method of
practice, together with further objects and advantages
thereof, may best be understood by reference to the following
description taken in connection with the accompanying
drawings in which:
Figure 1 is a schematic cross-section view o~ a
typical first level via connection :Ln a prior art high
density interconnect structure having spun-on upper
dielectric layers;
Figure 2 is a schematic cross-section view of a
broken via connection in a multi-laminate structure employing
a thermoplastic adhesive;
Figure 3 is a cross-section view of a high density
interconnect structure in accordance with the present
invention; and
Figure 4 is an illustration of the process steps
involved in fabrication of the Figure 3 structure.
~ail~d ~e~ i9~
In Figure 1, a small portion 100 of a prior art
high density interconnect structur~ which includes a first
level via connection is illustrated in cross-section. This
high density interconnect structure includes a laminated
.
:, , ; ; ~,
, . . . ..
- 15 - RD-18,338
first dielectric layer 122 and a spun-on second dielectric
layer 132. This structure comprises a chip 116 having a
contact pad 118 on its upper surface. A first layer 120 of
the overlying high density interconnect structure comprises a
5 dielectric layer 122 and a patterned metallization layer 128.
The dielectric layer 122 has separate lower and upper
sublayers 124 and 126, respectively. The sublayer 124 is a
thermoplastic adhesive such as ULTEM~ 1000 polyetherimide
resin available from General Electric Company and the
sublayer 126 is a Kapton~ polyimide thermoset film, available
from E.I. du Pont de Nemours Company. The metallization 128
extends down into a via hole 127 and into ohmic contact with
the contact pad 118. The sidewalls of the via hole are
sloped upward and outward as a result of its formation by
laser drilling. A second layer 130 of the high density
interconnect structure is disposed on layer 120 and comprises
a dielectric layer 132 and a patterned metallization layer
138. The dielectric layer 132 is a spun-on thermoplastic
layer such as SPI siloxane polyimide available from HULS
America.
For failure analysis we cross-sectioned multilayer
laminates which we made previously in which each dielectric
layer consisted of a thermoplastic :Lower layer and a
thermoset upper layer and in which via connections were
destroyed during the process of laminating subsequent
dielectric layer.
Figure 2 illustrates a small portion of such a
cross-section. The cross-sectioned high density interconnect
structure 200 includes laminated first and second dielectric
layers 222 and 232, respectively. This structure comprises a
chip 2l6 having a contact pad 218 on its upper surface. A
first layer 220 of the overlying high density interconnect
structure comprises a dielectric layer 222 and a patterned
metallization layer 228. The dielectric layer 222 has
separate lower and upper sublayers 229 and 226, respectively.
J :~ (, !'
- 16 - RD-18,938
The lower sublayer 224 is an ULTEM~ 1000 polyetherimide resin
available from General Electric Company thermoplastic
adhesive and the upper su~layer 226 is a KAPTON~ polyimide
thermoset film available from E. I. DuPont de Nemours. The
metallization 228 extends down into a via hole 227 and
includes a portion disposed in ohmic contact with the contact
pad 218. The upper part of the sidewalls of the via hole 227
are sloped upward and outward as a result of its formation by
laser drilling. A second layer 230 of the high density
interconnect structure is disposed on layer 220 and comprises
a dielectric layer 232 and a patterned metallization layer
238. The dielectric layer 232 has separate lower and upper
sublayers 234 and 236, respectively. The lower sublayer 234
is an ULTEM~ 1000 polyetherimide resin available from General
lS Electric Company thermoplastic adhesive and the upper
sublayer 235 is a KAPTON~ polyimide thermoset film available
from E. I. DuPont de Nemours.
The broken via shown in Figure 2 is typical of
broken vias we sectioned in that the via has been expanded
into the space underneath the thermoset upper sublayer 226
portion of the lower dielectric layer 222. The metallization
of the via i~ typically fractured at: the lower edge of the
upper sublayer 226, leaving a gap 229 in metallization 228.
This post-lamination via configurati.on results from the
thermoplastic adhesive 234 of the se!cond dielectric layer
pushing down into the via and applying side-wise pressure
which causes the second adhesive 234 to flow in under the
thermoset sublayer 226 of the first dielectric layer as the
adhesive 234 pushes the metallization ahead of it, in
underneath that thermoset sublayer 226, with the
metallization in turn pushing the adhesive sublayer 224 of
the first dielectric layer ahead of i~. Ne concluded that
this is a result of that second lamination being done at a
temperature at ~hich the thermoplastic adhesive of the first
dielectric layer is sufficiently fluid that the pressure
.:
: .:,
17 - RD-18, 938
applied to the via sidewalls during the second lamination
step can cause the first layer thermoplastic adhesive 224 to
recede from the via. This problem is avoided in the prior
art thermoset adhesive printed circuit board art by the
S thermosetting of that first adhesive layer prior to
laminating the second dielectric layer. AS has been
discussed above, such a solution is not acceptable in high
density interconnect structures o~ the type with which we are
concerned. We therefore concluded that a solution to this
problem is performing subsequent laminations at low enough
temperatures and lamination pressures that the first layer
thermoplastic adhesive does not flow.
A high density interconnect structure 10 in
accordance with the present invention is illustrated in a
cross-section view in Figure 3. The high density
interconnect structure 10 comprises a substrate 12 having
cavities 14 in the upper surface thereof in which integrated
circuit chips 16 or other electronic components are disposed.
For many high density interconnect structures, these
electxonic components are bonded to the substrate with a
thermoplastic adhesive 15. These electronic components have
contact pads 18 on an (upper) contact surface thereof. The
substrate 12 may have conductive runs 13 disposed on the
upper surface thereof. A first lay~sr 20 of the overlying
25 hi~h density interconnect structure lO comprises a dielectric
layer 2~ and a patterned metallization layer 28. The
dielectric layer 22 has separate lower and upper sublayers 24
and 26, respectively. The layer 24 is a thermoplastic
adhesive having a first glass transition temperature Tg1. The
layer 26 may be a thermoset material or a thermoplastic
material having a higher Tg than Tgl~ Where the components or
chips are bonded to the substrate with a thermoplas~ic chip
adhesive 15, it is preferrad that the chip adhesive have a
glass transition temperature (TgO) which is higher than Tgl.
The upper sublayer 26 of the first dielectric layer 22 should
.
'
- 18 -- RD-18,938
be stable over a range of temperatures above Tg1 in order that
it will remain stable during its laminacion to the chips
durlng the fabrication process. It is preferred that layer
26 be stable at least 100-C above Tgl. By stable, we mean it
has sufficient vlscosity that it doesn't shift, stretch or
otherwise change in an undesirable manner during the
lamination step. This layer 26 is preferably a thermoset
film, for example, Kapton~ which is sold by E.I. DuPont de
Nemours. Other materials, including thermoplastics, which
exhibit sufficient stability may also be used. The patterned
metallization layer 28 extends into contact with contact pads
18 and conductor runs 13, if any, on the substrate 12 within
via holes 23 in the dielectric layer 22.
A second layer 30 of the high density interconnect
structure comprises a second dielectric layer 32 and a second
patterned metallization layer 38. The dielectric layer 32
has separate lower and upper sublayers 34 and 36,
respectively. The second lower sublayer 34 has a second ;
glass transition temperature Tg2 and the upper sublayer 36 may
2Q again be a thermoset material or a thermoplastic material
having a Tg which is higher than Tg2. The patterned
metallization 38 extends into via holes 33 in the dielectric
layer 32 to make contact with the first metallization layer
28. If desired, selected via holes 33 may extend through
dielectric layer 22 as well to provide direc~ contact to
selected contact pads. However, that is not preferred
because of ~he added processing complexity which results from
having via holes of different depths.
A third layer of the high density interconnect
structure 40 comprises a dielectric layer 42 and a patterned
metallization layer 48. The dielectric layer 42 has separate
lower and upper sublayers 44 and 46. The third lower
sublayer 44 has a glass transition temperature Tg3 which is
lower than Tg2. The third upper dielectric sublayer 46 may be
; , ~:
. , ., :. '' ~ . ; ~
- 19 - RD-18, 938
a thermoset material or a thermoplastic material having a
higher glass transition temperature than Tg3.
In this structure, the thermoplastic adhesive
materials 24, 34 and 44 are selected so that their glass
transition temperatures decrease progressively. That is, Tg1
> Tg2 > Tg3. This difference in glass transition temperatures
is selected in order that the second dielectric layer may be
laminated onto the first layer of the high density
interconnect structure at a temperature at which the first
thermoplastic adhesive layer 24 is sufficiently stable that
the via connections between the first metallization layer 28
and the contact pads 18 and metallization runs 13 on the
substrate will not be disturbed. The required difference
between Tgl and Tg~ depends on the particular characteristics
of the thermoplastic materials. Where the sublayer 34
changes viscosity rapidly with temperature at its Tg, a
lesser difference in Tgls is required than is the case where
the viscosity of the dielectric adhesive 34 changes only
510wly with temperature. This is because the rapid change in
viscosity with temperature allows the second lamination step
to be carried out at substantially the Tg of that material
without a need to heat the structure significantly above that
temperature. The required difference between Tg2 and Tg3
involves similar considerations. Since it is desirable that
the final structure be able to operate at high temperatures,
it is desirable that the TglS of the various adhesive layers
differ by as little aq possible, while still permitting the
reliable fabrication of the overall structure. Thus, this
invention involves the use of thermoplastic adhesives which
exhibit dlfferential melting characteristics as a function of
temperature.
A variety of different adhesive materials are
available and suitable for use in thls structure. The Tg~S
of these materials range from greater than 300 C to the
vicinity of 150-C or lower. Where the chip 16 are bonded to
,
' :, ~ ' ' ' . ' ' !
'' .' ' '' ~ : ' '
. . ~
- 20 - RD-18,938
~he substrate 12 by a thermoplastic adhesive 15, the hlghest
Tg adhesive is preferably used ~o bond the chips to ~he
substrate with progressively lower Tg adhesives used for the
laminations.
A sequence of thermoplastic adhesives having
appropriately stepped Tgls is:
Approximate
Polymer Lamination
10 ~ ~ ~ ~
XU-21~polyimude CI~A-GEIGY 320 C360 C
ULTEM IIpolyetherimlde GE 275'C 350 C
2PADA/SDAN~ 3ulfonyl- GE 250 C 310-C
polyetherimude
ULTEM 6000 polyetherimide &E 237 C 300 C
ULTEM lO00 polyethPrimide GE 216-C 280C
SPI lO0~iloxane-polyimide HULS 137-C 200 C
America, Inc.
M&T 2065siloxane-polyimide M6T 85-C 160-C
Chemical3
30 Poly~terpolyest~r Sheldahl 120'C150'C
T-320 Corp.
E~VAX 410 ethylene-vinylDuPon:85'C 120'C
acetate copolymer
*A polymer made from bi~(4-aminophenyl) sulfone and bi3 phenol ~
dianhydride and furthe~ di3clo3ed i~ copending application Ssrial
No. (RD-20,055), entitled, "High ~emperatur~ Polyeth~r
Imlde Compo~ition3 and Method of Ma]cing~.
It is also possible to bLend thermoplastic
adhesives with differe~t Tg values to obtain a desired Tg and
laminating temperature which is otherwise unobtainable.
Examples of this are found in copending application Serial
No. _ ~RD-20,055).
: ' ~
?, j I ~
RD-18, 938
It is also noted that numerous other th~rmoplastic
adhesives are commercially available and their physical
properties well characterized. Potential materials for use
in this invention can be found from sources such as
"Plasticsi Thermoplastics and Thermosets", published by The
International Plastics Selector, Inc.
A preferred process 300 for producing the structure
shown in Figure 3 is illustrated in Figure 4.
The process 300 begins with a first step 301 of
mounting the chips on the substrate 12. This mounting may be
intended to be permanent where the substrate will remain part
of the completed structure or may be intended to be temporary
where the substrate will be removed following completion of
the fabrication process in order to provide a flexible high
density interconnect structure.
In step 302, the first upper sublayer 26 of
dielectric material is coated witA a thermoplastic adhesive
24. The thermoplastic adhesive 24 has a first glass
transition temperature Tgl.
In step 303, this first d:Lelectric layer is
laminated to the chips and substrate at a first lamination
temperature Tl.
Next, in step 309, the vial hole~ 23 are formed in
this first dielectric layer.
2S In step 305, a patterned metallization layer 2a is
formed on this first dielectric layer. This may be done by
any of the variety of techniques taught in the listed patents
or by other patterned deposition or uniform deposition
followed by patterning techniques. This completes the
fabrication of the ~irst layer 20 of the high density
interconnect structure, as illustrated in Figure 3.
In step 306, the second upper sublayer 36
dielectric material is coated with a thermoplastic adhesive
34 having second glass tran~ition temperature Tg2~ which i~
lower than the first glass transition temperature Tgl. This
~. .
r r3 ~
- 22 - RD-18,938
adheslve layer should be thicker than the metalliza~ion runs
it is to cover in order to avoid leaving voids in the
structure adjacent those metallization runs at the completion
of the laminating step.
In step 307, this second dielectric layer is
laminated on top of the existing structure, that is, on top
of the patterned metallization layer 28 and exposed portions
of the first dielectric layer 22. This second lamination
step is carried out at a temperature T2, which is lower than
the first lamination temperature T1.
In step 308, via holes are formed in this second
diele&tric layer.
In step 309, a second patterned metallization layer
38 is formed on top of the second dielectric layer 32 using
the same or a different metallization technique as was used
for the first metallization layer, as may be desired. This
completes the fabrication of the second layer 30 of a high
density interconnect structure of Figure 3.
Where a third layer 40 of the high density
interconnect structure is desired, as shown in Figure 3, the
process continues in step 310 with coating the third upper
dielectric sublayer 46 with a third thermoplastic adhesive
having a third glass transition temperature Tg3 whlch is lower
than Tg2-
In step 311, this third dielectric layer is
laminated to the existing structure at a temperature T3, that
is, to the patterned met.allization layer 38 and exposed
portions of the dielectric layer 32. The temperature T3 is
lower than the temperature T2.
In step 312, via holes 43 are formed in the third
dielectric layer 42 and in step 313, a third patterned
metallization layer 48 is formed on the third dielectric
layer.
As has been discussed, the temperature9 T1, T2 and
T3 are selected so that T1 > T2 > T3 in order that each of the
.
,
, ' '': ' ~
: : ",, , ,~ .
- 23 - RD-18,938
underlying layers of the high density interconnect structure
will remain stable during the subsequent laminating steps.
The required difference in temperature at successive
lamination steps depends on the particular adhesives and
other lamination conditions employed.
It will be understood that the lamination which
employs an adhesive with Tg2 can be performed at a temperature
above Tg1, so long as the first adhesive is sufficiently
stable at that lamination temperature that no shifting or
breakage of via interconnections takes place. Thus, with
appropriate control of the lamination temperatures and other
lamination conditions, the nine adhesives listed in the
table, or blends prepared from these adhesives, make a nine
lamination structure feasible. Obviously, most ci~cuits,
even very complex ones, can be interconnected in a structure
which includes substantially fewer laminations than nine.
The lamination temperatures of BPADA/SDAN and ULTEM 6000,
310C and 300C, respectively and those of M&T 2065 and
polyester T-230, 160C and 150C, respectively, are close
enough together that use of both mat:erials in each pair in
the same structure should be carefully controlled or avoided.
Each of these adheoives i'3 either inherently laser
drillable at 351 nm or may be modifi.ed to be so in accordance
with application Serial No. 456,421, filed December 26, 1989,
entitled "Laser ~blatable Polymer Di.electrics and Methods" by
H.S. Cole et al.
For the sake of repairability of the assembled
structure, each of the adhesive layers should to remain a
thermoplastic throughout the life of the ~tructure in order
to facilitate repair of the structure in the event that one
of the electronic components or a portion of the interconnect
structure should be found to be faulty.
As is described in some of the background patents,
the structure can be repaired by removing the overlay
structure by heating the overall structure to above the glass
..
,
.
: ~ .
,,, . ; .:: ., ~ ~
- 24 - RD-18,938
transition temperature of the adhesive layer 24 and then
peeliny the high density interconnect structure off the
substrate and electronic components 16. The presen~
invention provides additional versatility becau3e by
appropriately controlling the temperature to which the
structure is heated, only selected layers of the high density
interconnect structure need be removed where the fault is in
the interconnect structure itself, rather than in one of the
electronic components.
While in Figure 3 the structure is illustrated as
including a substrate 12, it should be understood that in
accordance with application Serial No. 250,010, entitled,
"High Density Interconnect With High Volumetric Efficiency`'
and application Serial No. 07/504,763, entitled, "A Flexible
High Density Interconnect Structure and Flexibly
Interconnected System", the substrate may be removed
following fabrication of the interconnect structure to leave
the electronic components 16 bonded directly to the high
density interconnect structure and otherwise unsupported.
It is preferred at each lamination step to coat the
upper sublayer with the thermoplastic adhesive prior to
adding it to the high density interconnect structure.
However, if desired, the thermoplastic adhesive may be
applied on top of the high denslty interconnect structure
prior to applying the upper sublayer either with an
addi~ional layer of that thermoplastic adhesive disposed on
the upper sublayer or without further adhesive thereon.
It will be recognized that in any of these
structures, a final upper spun-on dielectric layer may be
used, either for insula~ion purposes only or to support a
final me~allization layer. This avoids those problems with
spun-on layers which arise only when a second spun-on layer
is applied.
~hile the invention has been described in detail
herein in accord with certain preferred embodiments thereof,
. `. ~ : . ~.,
. .
- ~5 - RD-18,938
many modifications and changes therein may be effected by
those skilled in the art. Accordingly, it is intended by the
appended claims to cover all such modifications and changes
as fall within the true spirit and scope of the invention.
' ' ., '~ ` : ~ ',
: ~
