Note: Descriptions are shown in the official language in which they were submitted.
DI&ITAL SIGNAL MULTIPLEXER
The present invention relates to a digital signal
multiplexer according to the preamble of patent claim 1.
Digital voice signals and data having bit rates o~ an
intermediate or lower hierarchial level, in particular, having
bit rates of 2400, 4800 and 9600 bits/sec. are transmitted over
large distances preferably in time-multiplexed form at a higher
hierarchical level, for example, with bit rates of 64 kbits/sec.
or several M~its/sec. A multiplexer used for this purpose and
its employment in a digital data network is known from St.
Burgin, P. A. Merz "MXB.2-Datenmultiplexer 64kbits/s der 2.
Generation gemass CCITT X.50" (translated as: "2nd. ~eneration
MXB.2-Data Multiplexer 64kbits/s in accordance with CCITT X.50")
and P. A. Merz "Digitales Datennetz fur die Ubertragung von 2400,
4800 and 9600 bit/s auf festgeschalteten Leitungen", (translated
as: "Digital Data Network for the Transmission of 2400, 4800 and
9600 bit/s on Dedicated Lines"), Siemens Albis Berichte 3 (1987),
page 9 et_seq. and page 4 et seq. The described multiplexer
MXB.2 renders possible multiplexing five single channels of 9600,
ten single channels of 4800 or twenty single channels of 2400
bits/sec. and, with certain limitations, combinations thereof to
an aggregate bit stream of 64kbit/sec. The data transfer occurs
in envelope or frame structures on the single- and multi-channel
sides. Fig. 6 at page 12 depicts a multiple system containing
four MXB.2 multiplexars interconnected into a multiple system and
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which are each served by two multiplexer-, central clock-,
interface-, and monitoring- component groups. Each multiplexer
MXB.2 oontains four interface component groups, each of which can
receive five single channel interfaces and which are connected
by a serial bus with two respective channel processor component
groups. As a result, the flexibility of such a multiple system
is greatly limited. The channel processor component groups are
not interconnected with one another by the serial bus and only
can access a maximum of 4 x 5 single channel interfaces. Limited
possibilities exist of selecting the bit rates of the single
channel interfaces. A permissible new adaptation of this
multiple system to altered requirements of the users requires a
considerable amount of development effort and manual access to
mainly decentralized localized component groups. The serial bus
used in the system, which interconnects the single channel
interfaces with the channel processors, not only carries data but
also addresses and thus is under considerable load.
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It is therefore the object of the present invention to
propose a digital signal multiplexer which can be freely
configured as a function of different system constellations. The
configuration of a number of decentralized localized digital
signal multiplexers should be possible from a central location
and within the shortest possible time. The data traffic between
data lines of the ~ame or different hierarchial levels and bit
rates should occur efficiently and with low expenditure of
equipment and expense.
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'rhis object is solved by the measures set forth in the
characterizing portion of patent claim 1. Advantageous
constructions of the invention are set ~orth in further claims.
The inventive digital signa:L multiplexer possesses the
following advantages: It can be rapidly and optionally
configured by an external control station. Furthermore, it
exhibits an optimum flexibility with regard to data transfer
possibilities, system expansion and acceptance of optional data
transfer rates. It therefore also can be universally employedO
The invention will be explained in greater detail by
way of example hereinafter in conjunction with drawings. Thus
there i~ shown in,
Fig. 1 the block circuit diagram of a digital signal
multiplexer equipped with different internal multiplexer- and
inter~ace-component groups,
Fig. 2 an internal multiplexer compon~nt group,
Fig. 3 an internal interface component group.
Fig. 1 illustrates the block circuit diagram of an
inventive digital signal multiplexer possessing a data bus SH
with n lines, which is accessed at the single channel~side by two
interface component groups SSB-l, SSB-2 and on the multi-channel
side by two multiplexers MXH~ XH-2 which are connected by an
interface EPIC-Z with a parallel data bus DH. In this regard,
the data bus DH exhibits high, preferably standardized data
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transfer rates, such as 64 kbits/sec., 2 Mbits/sec., 8 Mbits/~ec.
and so forth. Apart from the multiplexer MXH-1 and the interface
component group SSB-1, which are provided as the minimum
equipment of th2 digital signal multiplexer, there can be
employed further multiplexers MXH-Z up to a maximum number which
corresponds to the number n o lines of the data bus SH (Z=n).
The interface component groups SSB-1, SSB-2 have ten single
channel interfaces EKS-ll, ...,~KS-25 which receive or transmit
data at low or intermediate, preferably standardized data
transfer rates such as 2400, 4800, 9600 bits/sec. by means of a
subscriber-side line. Consequently, each multiplexer MXH-Z
serves an optional number of single channel interfaces EKS-XY
which are localized at random interface component groups SSB-X
and which may have different data transfer rates. However, the
resultant data stream delivered to the multiplexer MXH-Z at most
corresponds to the data transmission rate of the data bus DH.
The data is serially applied in bits by the multiplexer
MXH-Z and the interface component groups SSB-X to one of the
lines of the data bus SH and retrieved therefrom. Such
interconnection of all of the component groups MXH-Z and SSB-X
at a continuous data bus SH affords maximum flexibility. Thus,
apart from single channel interfaces EKS-XY localized at
different interface component groups SSB-X exchanging data with
a multiplexer MXH-Z, also different single channel interfaces
EKS-XY or multiplaxers MXH-Z can exchange data with one another.
Bi-directional data transfer on tha lines of the data bus S~ is
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provided in order to increase the efficiency of the system. The
complete process for the resolu~ion and the generating of the
frame structures of the arriving data and the data to be
transmitted as well as for the correctly timed applying and
retrieving from the lines of the data bus SH, is communicated to
a housekeeping unit contained in each component group MXH-Z,
SSB-X by a preferably parallel control bus C~ depending upon the
prevailing component group configuration. This results in the
advantage that following changes in the configuration of the
component groups, it is possible to adapt the digital signal
multiplexer to the nsw conditions practically without time delay
from a cen~ral location. If, for example, the single channel
interfaces EKS-13 and EKS-25 transmit data with the same
transmission rate to the multiplexer MXH-2 and the operation of
the first EKS-13 is set and the transmission rate of the second
EKS-25 is doubled, then the digital signal multiplexer can be
rapidly adapted by appropriate information to the housekseping
units of the affected component groups MXH-2, SSB-l, SSB-2.
Fig. 2 depicts a multiplexer MXH-Z, a configuration and
alarm controller KAC-Z and a cycle counter æc which are connected
by the control bus CB with a programming and control station
CTRL. Furthermore, it contain~ a channel call-up mPmory KAR as
well as a multi-channel controller KVC connected by the interface
EPIC-Z with the data bus DH, and a single channel controller EKC.
The controllers EKC and VKC are interconnected by a processor-
register memory PR controlled by the configuration and alarm
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controller KAC-Z. The channel call-up memory KAR is connected
with the configuration and alarm controller KAC-Z, the single
channel controller EXC, the cycle counter ZC as well as with a
de-multiplexer DD and a multiplexer l~. The de-multiplexer DD
as wall as the multiplexer UM are connected, on the one hand,
with the single channel controller EXC and, on the other hand,
directly or via a buffer memory UR with the data bus SHo
The illustrated circuit functions as follows:
The multi channel controller VKC synchronizes to frames
of data which arrive via the data bus DH and the interface EPIC-
Z. The data contained in each frame is subsequently split into
single channel data and stored in the processor register msmory
PR. Single channel data, which is ready in the processor-
register memory PR for transmission to the data bus DH, is
removed from the multi-channel controller VXC, enclo~ed in a
frame and transmitted to the interface EPIC-Z. A respective
storage area is correlated in the processor-register memory PR
to each single channel for each transmission direction as well
as to the multi- and single channel-controllers for alarm
reporting to the configuration and alarm controller KAC-Z.
Furthermore, in the processor-register memory PR and in the
channel call-up memory KAR there is provided a storage area for
the configuration data for the multi- and the single channel-
controllers VKC, EXC. This configuration data is transmitted to
the configuration and alarm controller KAC-Z during start-up or
upon changing of the system in each instance by the control bus
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CB, which subsequently writes such data into the memories PR and
KAR. The multi- and the single channel-controllers VKC, EKC
monitor the course o~ the data trans~er and ~tore possible alarm
reports in the processor-register memory PR. These are removed
by the configuration and alarm controller KAC-Z and delivered to
the control station. The single channel controller EKC has
available for each transmission direction callable single
programs which serve for the single channel data transfer bit-by-
bit as well as for generating and checking of the single channel-
side frame structure. The configuration and alarm controllerKAC-Z writes program configuration data units into the channel
call-up memory KAR which are cyclically, while clocked by the
cycle counter ZC, read into the single channel controller EXC and
by means of which there is selected per cycle a single program.
By means of a single program there is retrieved a single data bit
from one of the lines of the data bus SH and delivered to the
processor register-memory PR by the multiplexer UM and the single
channel controller EKC or there is removed from the processor
register-memory PR a single channel data bit designated by the
multi-channel controller VKC and delivered by the single channel
controller EKC and the de-multiplexer DD to one of the lines of
the data bus SH. Accordingly, for a data transmission rate of
64 kbits/sec. for each transmission direction a single program
is run at least 128,000 times per second in the single channel
controller EKC. In order that the transfer of a single channel
data bit, carried out by the selected single program~ can
correctly take place, control data belonging to the respective
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program configuration data units are simultaneously delivered by
the channel call-up memory KAR to the de-multiplexer DD as well
as to the multiplexer UM and the buffer memory UR, so that,
depending upon the applied control d~ta, the de-multiplexer DD
transfers the single channel data bit from the single channel
controller EXC to the correct line of the data bus SH, or that
the single channel data bit is transferred, following
intermediate storage in the buf~er memory UR, by the multiplexer
UM from the correct line of the data bus SH to the single channel
controller EKC. Furthermore, single programs can serve for
checking individual component groups or the entire digital signal
multiplexer.
The inter~ace component group SSB-X depicted in Fig.
3, contains a configuration and alarm controller KAC-X and a
cycle counter ZC which are with a channal call-up memory KAR and
by means of the control bus CB with the programming and control
station CTRL. Furthermora, the configuration and alarm
controller KAC-X is connected by a control line with all of the
single channel interfaces EKS-Xl,...,EXS X5. The channel callup
memory XAR is connected by a further control line with the single
channel interfaces EKS-Xl...EKS-X5 and with a de-multiplexer UD
and a multiplexer DM. Furthermore, the de-multiplexer UD and ths
multiplexer DM are connected with the data bus SH and by mean~
of a respective data line with the single channel interfaces ÆKS-
Xl...EXS-X5.
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The configuration and alarm controller XAC-X writes
configuration data units into the channel call-up memory KAR
which are cyclically, while clocked by the cycle counter, applied
to the single channel interfaces EXS-XY and to the multiplexers
DM, UD. As a result, single channel data bits are removed from
one of the single channel interfaces EKS-Xl...EKS-X5 and
transmitted by the de-multiplexer UD to the respective line of
the data bus SH or, conversely, removed from one of the lines of
the data bus SH and transmitted by the multiplexer DM to one of
the single channel interfaces EKS-Xl...EXS-X5. The channel call-
up memory controls the multiplexers DM and UD in such a manner
that the single channel interfaces EXS-Xl...EXS-X5 for the data
transfer are always connected with the correct line of the data
bus SH. The control line, by means of which the confiquration
and alarm controller KAC-X is connected with the single channel
interfaces EKS-Xl...EKS-X5, serves for initializing this
component group EKS-Xl...EKS-X5 as well as for receiving
condition and alarm reports.
In order to ensure the synchronous coaction of the
multiplexer MXH-X and the interface component groups SSB-X, their
cycle counters ZC are commonly started. As a result, there is
ensured that the data bits are placed upon the lines of the data
bus SH and again removed from these lines at the proper point in
time and thus free of collisions.
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