Note: Descriptions are shown in the official language in which they were submitted.
2066282
Translation
CIRCUIT ARRANGEMENT ~OR ANPLIFYING AN ELECTRICAL SIGNAL
The invention relates to a circuit arrangement for
amplifying an electrical signal, particularly the photocur-
rent of a photodiode, which is generated as a function of the
intensity of the light incident on the photodiode.
In a known circuit arrangement of this type (D. Lutzke,
"Lichtwellenleitertechnik" [Light Waveguide Technology],
published by R. Pflaum Verlag, Munich, 1986, pages 282-285),
a transimpedance amplifier is provided which includes a
feedback resistor as its negative feedback network. With
this circuit arrangement, it is possible to realize a
transmission behavior with which a low impedance voltage
source for the further amplification is formed from the high
impedance current source (photodiode). However, the band-
width of this circuit is limited by the influence of the
feedback resistor.
In a further circuit arrangement (H.-D. Kirschbaum,
"Transistorverst~rker Z, Teil 1" tTransistor Amplifier 2,
Part 1], Teubner Studienskripten [Teubner Study Scripts],
Stuttgart, 1985, pages 199-202) a transistor amplifier
connected as current amplifier is provided with a current
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shunt feedback composed of a resistance network. The
circuit described here includes two transistor stages and a
divided emitter resistor at the second transistor as well as
a negative feedback resistor that is coupled back from the
center tap of this emitter resistor to the input, more
precisely to the base, of the first transistor. This prior
art circuit is suitable for the amplification of particularly
small input currents as they are generated, for example, by
photodiodes upon the detection of light signals. In this
connection, it is of particular significance to ensure a
sufficient signal to noise ratio for the further evaluation
of the current of the photodiode also after the necessary
amplification of the current so that the error rate in the
subsequent information processing can be kept as low as
possible. The relationships between the error rate and the
signal to noise ratio are described, for example, in the book
by G. Grau, entitled "Optische Nachrichtentechnik" rOptical
Data Communications], published by Springer Verlag Berlin,
Heidelberg, New York, at page 264. Additionally, it must be
considered that the gain should also be sufficient at high
frequencies since in optical data communications the band-
width to be transmitted is very wide.
~ his prior art circuit arrangement also has the drawback
that if the photocurrent of a photodiode, particularly a PIN
- 2 -
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diode, is amplified, the transmission behavior at high
frequencies is not the best.
It is an object of the invention to provide a circuit
arrangement having the features defined in the preamble of
the main ~laim for amplifying an electrical signal in which
the transmiesion behavior during the amplification of the
photocurrent of a photodiode is improved.
This is accomplished according to the invention by the
characterizing features of the main claim.
The circuit arrangement according to the invention is of
advantage primarily because of the use of a negative feedback
network composed of two capacitive voltage dividers, which is
very easy to realize from a circuit engineering point of view
and which does not adversely affect the other characteristics
of the current amplifier principle but nevertheless ensures a
considerable improvement of the transmission characteristics
of the circuit arrangement at high frequencies with a
sufficient signal to noise ratio in the signal to be process-
ed.
one embodiment of the circuit arrangement according to
the invention, incorporating the features of claim 2, permits
in an advantageous manner an optimum loop gain by way of
suitable dimensioning of the resistors and capacitors of the
capacitive voltage dividers, with particularly the low
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impedance circuit point at the source terminal of the second
transistor stage being utilized. This makes it possible to
select the resistor disposed in the negative feedback path
of the voltage divider to be highly resistant and to obtain a
favorable signal to noise ratio. This high resistance value
is possible since the relatively low impedance circuit point
at the center tap of the capacitive voltage divider allows
the latter to be capacitively loaded, thus permitting the use
of a relatively small capacitor in the negative feedback
path. However, it can always be ensured that the time
constants of the two components of the capacitive voltage
divider are identical and a dividing ratio of, for example,
1:10 can be realized. With this embodiment, an excellent
transmission behavior is thus also ensured for high
frequencies.
In the embodiment of the circuit arrangement according
to claim 3 of the invention which includes two field effect
transistors, the advantages resulting from a combination of a
PIN diode with a current amplifier circuit become particular-
ly evident. The use of a PIN diode is advantageous particu-
larly compared to the usually employed avalanche photo-
diodes, since the latter, although they have a very high
sensitivity, are very expensive and a high voltage is
required to supply such a photodiode with voltage. Thus the
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circuit arrangement is significantly simplified and made less
expensive.
Other advantageous features of the invention are
disclosed in the remaining dependent claims.
One embodiment of the invention will now be described
and explained with reference to Figures 1 to 4. It is shown
in:
Figure 1, a block circuit diagram for a current ampli-
fier with current-current feedback;
Figure 2, a basic circuit arrangement for a current
amplifier including a PIN photodiode at its
input;
Figure 3, a basic circuit diagram for a loop voltage
divider;
Figure 4, a basic circuit diagram for a transmission
voltage divider;
Figure 5, an example of an output circuit for the
current amplifier of Figure 2 including a
connected gate drain stage;
Figure 6, a further example of an output circuit for the
current amplifier including a transimpedance
amplifier.
Figure 1 shows a block circuit diagram including two
series connected amplifier stages Tl and T2 which are
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constructed as current amplifier including a current shunt
negative feedback by way of a voltage divider composed of
resistors R1 and R~. Resistor R1 is here fed back from the
second stage T2 to the input of the first stage Tl. A
current source Q is disposed at the input of the first
amplifier stage T1 and furnishes a current Io as the signal
to be amplified. An output resistor R at which the output
voltage U can be pi~ked up is disposed at the output of the
second amplifier stage T2. A current Io here flows through
resistor R1, a current
Io' = Io R1/R2
flows through resistor R2 and a current Io'' according to the
equation
Io'' = Io (1 + R1/R2)
flows at the output of the second stage, with the resulting
transmission constant of the current amplifier being Io''tIo.
Figure 2 shows a basic embodiment of the circuit
arrangement according to the invention in which the current
source is a PIN diode which is connected as photodiode P
between the gate G1 of a first amplifier stage formed of a
field effect transistor FET1 and the positive pole of the
operating voltage UB. This photodiode P furnishes a current
Io as the input signal for the current amplifier. Between
gate G1 of field effect transistor FETl and the zero
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potential of operating voltage UB, there is disposed a
capacitance C which is essentially composed of the switching
capacitances of the input region of the circuit arrangement
including the inherent capacitances of photodiode P and of
field effect transistor FETl. Connected thereto is a
capacitive transmission voltaqe divider composed of a first
parallel connection of a resistor R1 and a capacitor Cl and a
~econd parallel connection of a resistor R2 and a capacitor
C2. The transmission voltage divider is shown individually
in Figure 4, with the transmission constant being derivable
from the relationship Uo/U. Figure 3 is a schematic repre-
sentation of a loop voltage divider formed of a capacitance C
and the parallel connection of R1 and C1 which is determina-
tive for the calculation of the loop gain and can be repre-
sented by a calculated separation of the negative feedback
path.
The source terminal SO1 of the first field effect
transistor FETl (Figure 2) is connected directly to the zero
potential of operating voltage UB and the drain terminal Dl
is connected, on the one hand, by way of a resistor X1 to the
positive pole of operating voltage UB and, on the other hand,
directly to the gate G2 of a second field effect transistor
FET2.
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The source terminal S2 of the second field effect
transistor FET2 is brought to a center tap M of the capaci-
tive voltage divider and the drain terminal D2 of the second
field effect transistor FET2 lies, by way of a r sistor X2,
at the positive pole of operating voltage UB and, by way of a
capacitor C3, at an output resistor R; the resistance value
of drain resistor X2 must here be greater than the value of
output resistance R.
In order to obtain the optimum transmission behavior of
the circuit arrangement according to the invention, the
capacitive voltage divider must be dimensioned in such a way
that the time constants of both components of the capacitive
voltage divider are the same, that is, the following condi-
tion must be met:
R1 Cl = R2 C2.
The complex resistances of the two components of the
capacitive voltage divider Rl and R2 result as follows:
R1 = 1 + j~ R1 C1
R2 = 1 + j~ R2 C2
The current gain of the circuit arrangement thus results
as follows:
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Vi = 1 + Rl . 1 + j~ R2 C2
R2 1 + j~ R1 C1
and, under the condition that R1 C1 = R2 C2, it is the
following:
Vi = 1 + C2/C1 = 1 + R1/R2.
Under consideration of the negative feedback by way of
the capacitive voltage divider the loop gain Vs of the
circuit arrangement is calculated according to the following
formula:
S1 ~ X1
Vs = 1 + 1 + j~ Rl Cl
For low frequencies, the following applies:
Vst = Sl Xl
and the following for high frequencies:
Vsh = S1 X1
1 +
Under the assumption that the steepness S1 of field
effect transistor FETl is 50ms and, for example, the follow-
ing dimensions exist:
X1 = ~oo Ohm
C = 1 pF,
Cl = 0.25 pF,
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a gain of 20 dB results for low frequencies and a gain of
6 dB for high frequencies.
From these derivations it can be seen that the ratio of
C/Cl determines the loop gain at high frequencies. Thus the
optimum selection of capacitor C1 ensures a sufficient
amplification factor for the circuit arrangement according to
the invention even at high frequencies.
In the embodiment according to Figure 2, for example, a
resistance value of 50 Ohm can be selected as output resis-
tance R. As an alternative, however, a further transistor
stage in the form of a cascode circuit may b~ added as shown
in Figure 5. Instead of the load resistor X~, Figure 5
includes a gate stage and a cascode circuit including a
source follower, respectively. For this purpose, a field
effect transistor FET3 including a load resistor R3 is
provided. The output of this field effect transistor FET3 is
connectad to the gate terminal of an output field effect
transistor FET4 at whose source resistor R4 the output signal
is availa~le.
Another embodiment of an output configuration of the
circuit arrangement according to the invention is shown in
Figure 6. Here a transimpedance amplifier TV constructed in
a known manner is connected to the output of a current ampli-
fier SV, here shown as a block according to Figure 2, with
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the transfer function of transimpedance amplifier TV being
essentially dependent upon a negative feedback resistor RT.
