Note: Descriptions are shown in the official language in which they were submitted.
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Serniconductor device
TECHNICAL FIELD
The present lnvention relates to a semiconductor device
comprising a first field efEect transistor of a first
conductivity type, which transistor is arranged in a
semiconductor body and has a source region provided with a
source connection, a drain region provided with a drain
connection, a channel region arranged between the source and
drain regions, and members for creating a conducting channel
in the channel region between the source and drain regions.
The invention relates in particular to a so-called
semiconductor switch for use as a switching member.
BACKGROUND ART
It is previously known to use field effect -transistors of
MOS type as switching members. Such a transistor may be
given low on-state resistance. However, the very limited
maximum permissible voltage of the insulating layer located
between the control electrode of the transistor and its
channel region limits the maximum voltage, at which a
conventional MOS transistor may be used, to low values.
From Swedish published patent application 460 448 a
semiconductor device of MOS type, intended for switching
purposes, is already known. A device of this kind may be
designed for considerably higher working voltage than a
conventional MOS transistor. The maximally attainable
charge carrier density in the channel region of the
transistor during the conducting state of the transistor is,
however, limited, which entails a higher on-state resistance
of such a device than in a conventional MOS transistor.
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SUMMARY OE IHE INVENTION z~ 3~ ~
The present invention aims to provide a semiconductor device
of the kind mentioned in the introductory part of the
specification, which simultaneously exhibits a high power
handling capacity per unit of surface and a high speed of
action. To attain a high power handling capacity per unit
of surface, both the abiIity to withstand a high off-state
voltage and a low on-state resistance are required. This
purpose is attained to a high degree with a semiconductor
device according to the invention.
What characterizes such a device will be clear from the
appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
In the following the invention will be described with
reference to the accompanying Figures 1-7. Figure 1 shows
the fundamental configuration of a device according to the
invention. Figure 2 schematically shows how a device
according to the invention may be connected to control and
load circuits. Figure 3 shows how the two transistors in a
device according to the invention may be provided with so-
called stop zones at the ends of the channel regions.
Figure 4 shows an alternative embodiment with one single
stop zone for each transistor. Figures 5a and 5b show how,
according to two alternative embodiments of the invention,
control signals are supplied to the device and how members
for generation of suitable control voltages are integrated
with the device. Figure 6 shows an alternative embodiment
in which the substrate consists of a silicon wafer, in which
the lower of the two transistors of the device is produced.
Figures 7a, 7b, 7c and 7d show successive steps in one
example of a method for the manufacture of a device
according to the invention.
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DESCRIPTION OF THE PREFEE~R~D ~MBODIMENIS
Figure 1 shows a semiconductor device according to the
invention. The device is arranged on a substrate 1 in the
form of a silicon wafer. On the wafer an electrically
insulating silicon dioxide layer 2 is produced, which
separates the device from the substrate. On the surface of
the silicon dioxide layer 2 a monoc:rys-talline silicon layer
3 is applied, in which a first field effect transistor is
produced. The transistor has an N+--doped source region 31,
a P-doped channel region 32 and an N+-doped drain region 33.
The source regi.on is provided with a connection contact 311
and a lead 312. The drain region is provided in similar
manner with a contact 331 and a lead 332. On the surface of
the silicon layer 3 an electrically insulating silicon
dioxide layer 4 is arranged, and on top of this a second
monocrystalline silicon layer 5 is arranged. In the latter
silicon layer a second field effect transistor is produced,
which has the P+-doped source region 51, the N-doped channel
region 52 and the P+-doped drain region 53. The source
region is provided with a contact 511 and a lead 512, and
the drain region is provided with a contact 531 and a lead
532. The two field effect transistors are of enhancement
type. In the lower field effect transistor 31-33 the source
and drain regions are of N-type and the transistor is a so-
called NMOS transistor. In the upper transistor 51-53 the
source and drain regions are of P-type and the transistor is
a so-called PMOS transistor.
The silicon dioxide layer 2 should have a thickness of at
least 1 ~m and preferably has, at least at higher working
voltages, a thickness of 5-10 ~m. The silicon layers 3 and
5 may have a thickness of 60 nm and the silicon dioxide
layer 4 a thickness of 20 nm. The length of the channel
regions of the field effect transistors (the distance
between the source and drain contact of a transistor)
depends on the working voltage for which the device is
intended. The length may preferably lie within the interval
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10-100 ~m. At a maximum off-state voltage of, for example,
160 V, the length of the channel regions may be 18 ~lm and at
a working voltage of 300 V it may be 30-50 ~m. The doping
of the source and drain regions of the transistors may be
within the interval 101~-1020 cm~3 and of their channel
regions within the interval 10l5-1017 cm~3.
The channel regions should be formeci such that charge
balance prevails between these two regions. This means that
the number of doping atoms per unit of surface should be the
same for both regions, i.e. that the product of layer
thickness and impurity concentration per unit of volulne
should be the same.
As will be clear from Figure 1, -the channel region 32 of the
lower transistor has a somewhat greater length than the
channel region 52 of the upper transistor. Also other
embodiments are possible, and, for example, in the manner
shown in dashed lines a and b, the source and drain regions
of the lower transistor may be extended inwards towards the
channel region so that the length thereof is the same as the
length of the channel region of the upper transistor.
The width of the the channel regions ~their extent
perpendicular to the plane of the paper in Figure 1) is
adapted in a suitable manner in dependence on the desired
current handling capacity of the component. Possibly, in
order to achieve the desired current handling capacity, a
plurality of components may be connected in parallel.
Alternatively, the component according to the invention may
be arranged on an electrically insulating substrate, for
example a sapphire plate. The oxide laye 2 may then be
considerably thinner than what has been stated above.
According to another embodiment, the thick silicon dioxide
layer 2 may be replaced by a polycrystalline diamond layer
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arranged on a si].:icon substrate, on which diamond layer a
thin silicon dioxide layer may be arranged.
Figure 2 shows the principle of how the component according
to the invention is connected to a control and load circuit.
The component is schematically shown as being included in an
integrated circuit A. In addition to the component shown in
Figure 1, the circuit also comprises the resistors 61, 62
connected between the source connections 312, 512 and drain
connections 532, 332, respectively, oE the -transistors. Ihe
source connection 312 and drain connnection 332 o~ the lower
transistor constitute the main connections of the circuit
and are shown in Figure 2 eonnected into a schematic load
circuit consisting of a voltage source 9 and a load object
10. Control voltage sources 71, 72 are connected between
the source connections 312, 512 and the drain connections
332, 532, respectively, of the two transistors. The control
voltage sources are switched on and off with the aid of
switching members with the contacts 81, 82. The control
voltage sources suitably supply equally large voltages.
In the position of the switching member 81, 82 shown in
Figure 2, the supplied control voltage u is ~ero, and the
source regions of the two transistors are kept at the same
potential with the aid of the resistor 61, and the two drain
regions are kept at mutually the same potential with the aid
of -the resistor 62. With the polarity of the voltage source
9 shown in Figure 2, the junction of the lower transistor
shown on the lefthand side in Figure 2 and the junction of
the upper transistor shown on the righthand side in Figure 2
are blocking. Space charge regions are formed at the
blocked junctions and absorb the applied voltage. Because
of the relatively weaker doping of the channel regions, the
extent of the space charge layers will be greatest in these
regions, which take up the greater part of the applied
voltage.
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When switching on the control voltage by closing the
contacts 81, ~2, the control signal u will be equal to the
voltage of the control voltage sources. ~he upper
transistor is given a positive po-tentlal in relation to the
lower one. The voltage of the control voltage sources and
hence the potential difference between the two transistors
may, for example, be 5 V. The potential difference causes a
P-conducting channel to be induced in the channel region of
the upper transistor nearest the insulating layer q, and an
N-conducting channel to be induced in the channel region of
the lower transistor nearest the insulating layer 4. Thus,
the two transistors change from conducting state and a load
current may flow from the voltage source 9 through the lower
transistor and the load object 10. The two induced channels
influence and strengthen each other, and a high charge
carrier density may be obtained in the channels, typically
5X1012 - 1013 cm~2. This charge carrier density is
considerably higher -than what has been possible to achieve
in prior art components of the kind in question, for example
in the component known from Swedish published patent
application 460 448. This high charge carrier density
imparts to the conducting channels high conductance, of the
same order of magnitude as a conventional MOS transistor,
and the component according to the invention therefore has
low on-state resistance. At the same time, a component
according to the invention is able, in non- conducting
state, to take up high voltage be-tween the source and drain
contacts, which is due to the weak doping in the channel
regions and to the space charges in the channel regions on
either side of the insulating layer 4 balancing each other.
A component according to the invention will therefore have a
considerably higher power handling capacity per unit of
surface than prior art MOS transistors. The power handling
capacity approaches that of bipolar transis-tors, but a
component according to the invention, because of the absence
of minority charge carriers, has a considerably higher speed
of action than a bipolar transistor.
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As mentioned above, in the non-conducting state one of the
two junctions of a transistor is blocking. Because of the
balanced dopin~s and the thin intermediate oxide, a space
charge region, both in the upper and the lower transistor,
extends from the drain region and up to the source region.
The applied voltage between the source and drain regions may
then, at the source region, create an electric field which
acts in an injecting manner. At a certain length of the
channel region and a certain maximum applied voltage,
therefore, the doping in the channel region must be so high
that the injecting field does not reach to the opposite PN- -
junction. This limits the maximum working voltage of the
component. Figure 3 shows how this problem can be
eliminated by providing the channel region nearest the
source and drain regions with stop zones which have the same
conductivity type as the channel region but higher doping
than this. Figure 3 shows such an embodiment of a component
according to the invention, and the stop zones are there
designated 54, S5 and 34, 35, respectively. When the
voltage applied across the component increases, the stop
zone with its higher doping reduces the lateral field
intensity so as to avoid injection. In such a component,
the doping of the channel region may be made considerably
weaker than in a component according to Figures 1 and 2. In
Figure 3 this weaker doping has been designated v and ~,
respectively. The weak doping of the channel regions causes
the field intensity through the whole channel region to be
high and approximately constant in non-conducting state,
which makes possible a high working voltage of the
component. In the embodiment of a component according to
the invention shown in Figure 3, however, a maximum field
intensity is obtained at the blocking junction, which limits
the maximum voltage applied.
The disadvantage mentioned above may be eliminated with the
aid of the embodiment shown in Figure 4. In this
embodiment, each transistor has only one stop zone 35 and
54, respectively, and these are arranged at opposite ends of
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the channel regions. Whell a positive voltage is applied to
the source regions 31, 51 of the transistors in relation to
the drain regions 33, 53, the field intensity in the channel
regions will be approximately constant and equal to the
maximum field intensity occurring in the component. This
results in a very good voltage-absorbing capacity of the
component. However, this is only true at the polarity of
the applied voltage just mentioned. To make possible a high
voltage-absorbing capacity in both directions, therefore,
two oppositely directed components according to Figure 9 may
be connected in series.
In the embodiment of the invention described above, the
applied control voltage is zero in non-conducting state.
Alternatively, a negative control voltage may be applied
during this interval. A negative control voltage between
the two transistor systems also suppresses the injection.
The need of stop layers and their degree of doping may thus
be optimi~ed with respect to the degree oE negative control
voltage when the switch is to be non-conducting.
In a semiconductor device according to the invention, the
doping profiles of the channel regions should preferably be
such tha-t the potentials in the two channel regions
accompany each other, i.e. that within the entire extent of -
the channel regions the potentials of the two points in each
arbitrary pair of oppositely positioned points in the two
channel regions are equal or as equal as possible. In this
way voltage stresses across the insulating layer 4, other
than those caused by the control voltage, are avoided. This
can be achieved, for example, by making the doping of the
channel regions low, as in the components shown in Figures 3
and 4. The field intensity in each channel region will then
be approximately constant and the potential in each channel
region varies linearly between the source and drain regions.
This entails the desirable equality of potential between the
two points of each pair of two oppositely located points of
the two channel regions.
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Figure 5a shows how, in an embodiment of the invention,
members for supplying control voltages are integrated with
the actual component. The component A thus consists of an
integrated circuit which, in addition to the two field
effect transistors, also comprises the resistors 61, 62 and
two diode bridges 11, 12. The component has connections B,
C for the load current. When the component is -to be brought
into conducting state, the connections 17, 18 are supplied
with an alternating voltage signal s. This is supplied to
the rectifier bridges via capacitors 13, 14 and 15, 16,
respectively. From the diode bridges the direct voltages u
are then obtained, which, in the manner described above,
control the component to conducting state.
Figure 5b shows an alternative embodiment of the device
according to Figure Sa. The integra-ted circuit A comprises,
in addition to the two field effect transistors, two sets of
rectifier bridges, namely lla, llb and 12a, 12b,
respectively, and two sets of inverters, namely Ila, Ilb,
Ilc and I2a, I2b, I2c, respectively. The bridges lla, 12a
are supplied with a constant alternating voltage P via the
connections 17a, 17b and the capacitors 13a, 13b, 15a, 15b,
for example o~ such an amplitude that the bridges deliver
direct voltages of the order of magnitude 5 V. These direct
voltages are supplied to the inverters as supply voltages.
When the component is to be conducting, a control signal in
the form of an alternating voltage S is supplied to the
control connections 18a, 18b. This causes a control direct
voltage to be generated across the resistors 61a, 62a, which
makes the output signals of the inverters Ila and I2a "low"
and of the inverters Ilb and I2b "high", i.e. the control
voltages "u" become positive and the component becomes
conducting and is maintained conducting for as long as the
control signal S is supplied. When the control signal S is
removed, the output voltage from the bridges llb, 12b
becomes zero, the output signals from the inverters Ila and
I2a become "high" and from the inverters Ilb and I2b "low",
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and the control voltages "u" become negative. The component
becomes non-conducting and the negative control voltage "u"
suppresses injection and thus increases the maximum
permissible voltage of the component.
In the embodiments of the invention described above, both
the field effect transistors are produced in thin
semiconductor layers of which -the lower is arranged on an
electrically insulating layer located on a substrate.
Figure 6 shows an alternative embodiment oE the invention,
in which the lower transistor is produced directly in the
substrate, which consists of a monocrystalline silicon body
1. At the lower transistor this body has a P-doped zone
32a, which constitutes the channel region of the transistor.
In this zone N-conducting regions 31a, 33a are produced,
which constitute the source and drain regions of the
transistor. Otherwise, the component is formed in the
manner previously described.
A component accord.ing to the invention may be manufactured
in a plurality of different ways. A preferred method of
manufacture will be described in the following with
reference to Figure 7. In a monocrystalline silicon wafer X
there are generated, by ion implantation of oxyqen and
nitrogen, respectively, through the upper surface of the
wafer in the figure, a silicon dioxide layer 101 and a
silicon nitrode layer 102 (SiXNy). Those parts, 104, 105,
106, of the silicon body which are positioned outside the
two layers just mentioned are not influenced by this
treatment. Fiqure 7a shows the silicon body after the ion
implantation. Thereafter there is generated, by some known
method (e.g. thermal oxidation and/or deposition), a silicon
dioxide layer 103 on the surface of the body, which is shown
in Figure 7b. Figure 7c shows the silicon body X turned
upside down. A second body Y of monocrystalline silicon has
been provided, in a similar known manner, wi-th a silicon
dioxide layer 201 on its surface. The two bodies are
brought toqether in the manner indicated by the arrow in
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Figure 7c. Even at room temperature a bonding then takes
place between the plates. The bonding may be reinforced by
a heat treatment in the temperature range ~00-1000C. By a
subsequent treatment by etching, part 106 of the silicon
body X is etched away, the nitride layer 102 then serving as
stop layer during the etching. Then the nitride layer 102
is etched away. The body thus manufactured is shown in
Figure 7d. The silicon body Y constitutes a substrate; the
silicon dioxide layers 201 and 103 form an electrically
insulating layer between the substrate and the semiconductor
component according to the invention; in the monocrystalline
thin silicon layer 109 the lower transistor of the component
is produced; the silicon dioxide layer 101 serves as
electrical insulation between the two transistors of the
component; and in the upper monocrystalline silicon layer
105 the upper transistors of the component are produced.
The desired doping of the different regions of the
transistors may, for example, be made with the aid of ion
implantation, either after the manufacturing steps described
above, or earlier during the manufacturing process.
The component according to the invention has been described
above as a semiconductor switch for use as switching member.
The component may have other fields of use as well, for
example as a controllable element in integrated digital
circuits. Besides as switching member, the component may
also be used for stepless control in analog circuits.
In Figure 2, the output circuit of the component consists of
a voltage source and a load object. However, the output
circuit may be of an arbitrary kind, for example a digital
or analog circuit element or circuit.
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