Note: Descriptions are shown in the official language in which they were submitted.
2~72~2
A Single Instruction Data Transfer Method and
Apparatus
1 0 Field of the Invention
.
` This invention relates generally to data transfer processing
and more specifically to receiving data from a peripheral device
into the external memory of a processor.
1 5
Background of the Invention
Traditional techniques used for data transfers typically
employ either the continuous use of the processor unit for the
2 0 length of the transfer or an external dedicated controller
assigned to the tran~fer. Such routines are generally known
and widely used throughout the computer design environment.
Programmed routines which use the proeessor are inexpensive
and size efflcient, however, they are computation inefficient.
2 5 Each transfer cycle takes a minimum of two instruction cycles
and the processor is unable to make any other computations
during the entire length of the data transfer. An example of
using a programmed transfer to solve the problem of
transferring data from a peripheral device to memory can be
3 0 found on page 224 of Microprocessors and Microcomputers,
, . .: : ~ ~ .
. . ,:
. .
2~72~
,
Ha,rdware and Software by Tocci and Laskowski. Dedicated
controllers do not utilize the processor ~or the entire transfer
routine, however, the controllers must obtain control of the data
bus to trans~er data. The process of obtaining control of the data
bus from the processor requires the controller to send a bus
request and receive a bus grant from the processor; this adds an
unknown delay of at least two instruction cycles for each bus
grant. Additionally, the controller will employ the data bus for
all or part of the data transfer, thus limiting the amount of data
1 0 the processor can transfer between itself and the memory. An
example of using a dedicated controller to solve the problem of
data transferal from a peripheral device to memory can be
found in the following application note by Thomas Hardy, A
Transparent DMA using a MC6809E MPU and a MC6844
1 5 DMAC, (1984). The use of traditional techniques leaves the
designer with either the inefficient use of the processor's
computing power or a data bus not always available to the
processor, thus restricting the amount of calculations that can
be performed by the processor within a certain amount of time.
2 0 Although the above examples are well suited to their
applications, a need exists for an inexpensive, small, transfer
process which only uses one processor instruction cycle to load
data from a peripheral device to the external memory of the
processor and relinquish the use of the data bus for the use of
2 5 the processor.
,
. . .
.: ,
2 ~ r~ 2 ~ ~ ~
Summary of the Invention
The present invention encompasse~ a single instruction
data transfer apparatus responding to a single triggering event
5 from a governing device to transfer data from an output device
to an input device. The apparatus, responding to the single
triggering event, generates at least one signal which selects the
input device and the output device. Upon selection of the output
device, the apparatus couples the output device to the input
1 0 device. Following the coupling of the output and input devices,
the apparatus creates at least one signal to the input device
which causes a write function to be enabled.
Brief Description of the Drawings
Figure 1 is a block diagram of a radio frequency data
transmission system.
Figure 2 and 3 are, together, a block diagram of a receiver
which may employ a single instruction data transfer
2 0 apparatus.
Figure 4 is a memory map of the memor;y shown in FIG. 2.
Figurc 5 is a process flowchart of the controller 103 for a
data transfer from teh inphase ADC (209) to the memory (303).
2 5 Desc~ption of a Preferred Embodiment
A radio frequency systern conveying a data signal from a
transmitter 107 to a receiver 101 is shown in FIG. 1. In a
radiotelephone system, the transmitter 107 would be a ~ed site
3 0 transmitter serving a radio coverage area which would be
:
-
- ~
2~72fi~
populated by mobile or portable transceivers, the receiver 101 of
which is shown in FIG. 1. This radio contains a processor 105
which performs calculations on the data received by the radio.
The data which is received by the radio must be transferred to
5 the processor 105 for these calculations to be performed. The
transfer of the in-phase (I) data and the quadrature (Q) data
from the receiver 101 to the processor 105 is handled by the
controller block 103.
FIG. 2 depicts a block diagram of a radio receiver 101. The
10 receiver 101 acquires radio frequency (RF) signals from the
fixed transceiver 107. Upon receipt of the signals, the receiver
101 filters 221 the signals and mixes 219 the RF signals with a
local oscillator (LO) 223. After passing through an additional
filter 217, the result3 are intermediate frequency signals (IF).
1 5 Mixer 201 adds LO to the IF signals and mixer 203 subtracts LO
from the IF signals, this results in base band (BB) signals. The
BB signals is then passed through low pass filters 205, 207 to
form in-phase (I) and Quadrature (Q) signals. The I signals
are a result of directly mixing the LO 225 with the IF frequency
2 0 and the Q signals are a result of phase shif~ing the LO 22~ by 90
degrees and mixing it w~th the IF frequency. The I and Q BB
signals are input into the two Analog to Digital Converters
(ADC) 209, 211 where they are sampled at regular intervals by
the sarnple clock and the results are stored in the buffers 213,
2 5 215. Aflcer sampling, the I and Q data is primed for transfer
into the digital processing environment, where calculations
will be performed on the data. The data in the buf~ers 213, 215
can be accessed by the processor 10S via the data bus 113. If the
processor 105 requests data from the ADCs 209, 211 ~e
3 0 controller module 103 controls the transfer of the data. The data
::`
.
, : .~ . .. . .
.~ . . . .;
- . .
.. .
. . .
2~J~2
is made available on the data bus 113 when the outputs of the
tri-state buffers 213, 215 are enabled.
The digital processing env~ronment of processor 105 is
represented by the block diagram of FIG. 3. It consists of a
5 digital signal processor (DSP, such as the DSP56001 available
from Motorola, Inc. or similar DSP) 301 and a memory 303. The
DSP 301, the memory 303, the controller 103 and the ADC's
buf~ers 213, 21~ are conventionally interconnected by the data
and the address busses 113,111. The address bus 111 is used by
1 0 the proce~sor to point to a specific register location in the
memory 303 or to the ADCs 209, 211. The dedicated control
lines, such as the RD, WR and CS, are used to perform
functions on the specilSc register selected by the address bus
111. The ADC's tri-state buf~ers 213, 215 are arranged as
1 5 registers in th~ DSP's 301 memory maps 401, 403 enabling the
DSP to read from these bu~ers as if they were memory
locations. The available processor memory consists of internal
RAM and external RAM and ROM. The memory i~ addressed
according to the memory maps of FIG.4. The DSP 301 is used by
2 0 the radio to perform the equalization calculations on the data
received by the radio. In the preferred embodiment the
calculations include the following: (1) automatic frequency
control (AFC), (2) correlation, (3) match filter, (4) power
measurements, and (5~ automatic gain control (AGC). The data
2 5 used for the calculations are the sampled data from the .ADC's
buffers 213, 215 located in the receiver 101. The data and the
results of the calculations are stored in the memory 303 and
retrieved from the memory 303 by the combined use of the data
bus 113, the address bus lll and the memory maps 401, 403, 405.
.
, . : ~,, ~ , . .
. ,......................... . ~ ~ .
2~2~
The memory maps utilized by the DSP 301 are described in
FIG. 4. The addressable memory locations of the DSP 301 are
broken into three individual maps; the X data memory 401, the
Y data memory 403 and the program memory 405. All three
5 memory maps have memory located internally to the DSP 301
and externally to the DSP 301. The numbers preceded by a $
along the left side of the memory maps 401, 403, 405 are the
hexadecimal address locations used by the DSP 301 to refer to
specific locations in the memory maps. The X and Y data
1 0 memory 401, 403 and the program memory internal to the DSP
301 are addressed from $0000 to $00FF and in X memory from
$FFC0 to $FFFF. All of the other addressable memory is
external to the DSP 301. The external RAM for the X and Y data
memory banks are addressed between $2000 and $2800. The
1 5 addresses for the buf~ers of the ADCs 213, 215 are between $4000
and $4800. Notice that the I ADC buffer 213 location is in the X
memory bank 203 and the Q ADC buffer 215 location is in the Y
memory bank 205; this allows the DSP 301 to choose between the
I and Q data by toggling the x/y memory select line. The on chip
2 0 peripherals are addressed in the X data mem~ry 401 between
$FFC0 and $FFFF. The results of the calculations performed by
the DSP 301 are stored in the X and Y data memory 401, 403.
The results of the AFC calculations are written to Y: $FFF0,
and the results of the AGC calculations are written to Y:$FFD0
2 5 and Y:$FFE0. The external program ROM is addressed
between $8000 and $E000 in the program memory map 405.
The trans~er of data on the data bus is monitored by the
controller 103. If the DSP 301 requests a read from either of the
ADC buf~ers 213, 215, the controller alters the standard DSP 301
3 0 read routine. The read instruction from the DSP 301 is
:'.
,.
~26~
considered a single triggering event from a governing device.
Referring to FIG. 5, the transfer process from the controller 103
is ~riggered at 501 by a read instruction from the DSP 301. The
first test is carr~ed out at 517 to check if the read command is for
one of the receiver's two ADC buf~ers 213, 215. The controller
103 checks the address bus for an address between $4000 and
$4800 knowing that these are the address locations of the
receiver's ADC buffers 213, 215. If the read is requested for one
of the ADC buffers, bit 14 (A14) on the address bus will be high
1 0 and bit 13 (A13) will be low. If the read is for one of the ADC
bu~ers 213, 215, the controller 103 dec~des which ADC to read
from at 507. Upon determining this, the controller generates the
DSP's x/y memory select line. If the line is asserted high 503,
the D~;P 301 will be addressing memory in the X data bank 401,
1 5 low signifies memory in the Y data bank 403. If it i9 asserted
high, at 505 the controller 103 generates a signal which will
enable the outputs of the in-phase ADC's buffer 213; allowing
the I data onto the data bus 113. If the x/y memory select line is
low, then the controller 103 generates a signal which will
2 0 enable the outputs of the quadrature ADC's b~er 215; allowing
the Q data onto the data bus 113 at ~11. The preceding enable
~` signals select the appropriate output device. Since the DSP's
external memory 303 consists of several 8K ~ 8 bit menlories,
only the 11 least significant bits are necessary to address any
2 5 location within the memories. The higher order bits (A12 - A15)
are used by the controller to select between memory chips or
other peripheral device~ in the memory maps 401, 403, 405.
Since th~ lower bits of the external memory's address and the
ADCs' memory address are identical9 the only change
3 0 necessary to effectively alter the address in the memory map
`:
.
.
.
. . . : ~ ,
2~72~
401, 403, 405 from the ADCs 213? 215 to the external memory 303
is to assert the chip select (CS~ line for the external memory. At
507, the controller 103 generates signals which de-assert the
external memory's read line and assert the e~ternal memory's
5 CS lina, this i9 referred to as an altered read instruction. Next,
the controller 103 asserts the external memory's write line and
the external memory's ( S line at 509, this is referred to as an
altered write instruction. If the original DSP 301 address was
outside of the $4000 - $4800 window at ~03, then a standard DSP
1 0 301 read instruction would have been performed at 513. This
completes the controller's 103 routine at 511. The controller 103
i~ responsible for determining if the requested DSP 301 read is
for one of the ADC's buffers 213, 215, ~electing between the I or
the Q ADC buf~er 213, 215, creating a colTesponding write
15 address and executing the write command.
The preferred embodiment fulfills the radiotelephone'~
requirements of size of the controller, cost of the controller and
use of the processor. The controller 103 is irnplemented in a
16L8 PAL which i9 an inexpensive ~d small programmable
2 0 part. The transfer process requires only one read instruction
from the DSP 301 to carry out the entire transfer from one of the
two ADC'~ buf~ers 213, 215 to the external memory 303 of the
DSP 301. These m et or exceed the requests listed in the
background of the invention.
2 5 What is cl-imed i~:
~ .
,.~
,
