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Patent 2078940 Summary

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Claims and Abstract availability

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(12) Patent: (11) CA 2078940
(54) English Title: COMPOUND SEMICONDUCTOR DEVICE
(54) French Title: DISPOSITIF A SEMICONDUCTEUR COMPOSITE
Status: Expired and beyond the Period of Reversal
Bibliographic Data
(51) International Patent Classification (IPC):
  • H01L 29/778 (2006.01)
  • H01L 21/338 (2006.01)
  • H01L 29/812 (2006.01)
(72) Inventors :
  • NAKAGAWA, YOSHIKAZU (Japan)
(73) Owners :
  • ROHM CO., LTD.
(71) Applicants :
  • ROHM CO., LTD. (Japan)
(74) Agent: RICHES, MCKENZIE & HERBERT LLP
(74) Associate agent:
(45) Issued: 1996-11-12
(22) Filed Date: 1992-09-23
(41) Open to Public Inspection: 1993-04-30
Examination requested: 1993-02-19
Availability of licence: N/A
Dedicated to the Public: N/A
(25) Language of filing: English

Patent Cooperation Treaty (PCT): No

(30) Application Priority Data:
Application No. Country/Territory Date
Hei 3-311828 (Japan) 1991-10-29

Abstracts

English Abstract


A compound semiconductor device includes an undoped
semiconductor layer; a doped semiconductor layer formed on the
undoped semiconductor layer and having smaller electron
affinity than the undoped semiconductor layer; a gate electrode
formed on the doped semiconductor layer; a cap layer formed on
the doped semiconductor layer; and a source electrode and a
drain electrode respectively formed on the cap layer. In the
device, an undoped-material layer having greater electron
affinity than the doped semiconductor layer and the cap layer,
is formed between the doped semiconductor layer and the cap
layer. A layer which has the same composition and impurities
as those of the doped semiconductor layer and whose impurity
concentration is sufficiently higher than an impurity
concentration of the doped semiconductor layer may, be provided
between the doped semiconductor layer and the cap layer.


Claims

Note: Claims are shown in the official language in which they were submitted.


WHAT IS CLAIMED IS:
1. A compound semiconductor device, comprising:
an undoped semiconductor layer;
a doped semiconductor layer formed on said undoped
semiconductor layer and having smaller electron affinity than
said undoped semiconductor layer, impurities being doped in said
doped semiconductor layer;
a gate electrode formed on said doped semiconductor layer;
a cap layer formed on said doped semiconductor layer;
a source electrode and a drain electrode formed on said cap
layer; and
a source resistance decreasing layer comprising an undoped
semiconductor material layer having greater electron affinity
than said doped semiconductor layer and said cap layer for
decreasing a source resistance of said compound semiconductor
device by making electrons remain in a centre portion of said
doped semiconductor layer formed between said doped semiconductor
layer and said cap layer.
2. A compound semiconductor device as claimed in claim 1,
wherein said source resistance decreasing layer has a thickness
of several dozens angstroms.
3. A compound semiconductor device comprising:
an undoped semiconductor layer;
a doped semiconductor layer formed on said undoped
semiconductor layer and having a smaller electron affinity
than said undoped semiconductor layer, impurities being doped
in said doped semiconductor layer;
- 10 -

a gate electrode formed on said doped semiconductor layer;
a source electrode and a drain electrode formed on said
cap layer; and
a source resistance decreasing layer formed between the
doped semiconductor layer and the cap layer, wherein said
undoped semiconductor layer is formed of one of an InGaAs
layer and a GaAs layer, said doped semiconductor layer is
formed of an n+ AlGaAs layer, said cap layer is formed of a
GaAs layer, and said source resistance decreasing layer is
formed of an InGaAs layer.
4. A compound semiconductor device comprising: an
undoped semiconductor layer;
a doped semiconductor layer formed on said undoped
semiconductor layer and having smaller electron affinity than
said undoped semiconductor layer, impurities being doped in
said doped semiconductor layer;
a gate electrode formed on said doped semiconductor
layer;
a cap layer formed on said doped semiconductor layer;
a source electrode and a drain electrode formed on said
cap layer; and
a source resistance decreasing layer formed between the
doped semiconductor layer and the cap layer, wherein said
source resistance decreasing layer is a semiconductor layer
having the same composition and impurities as those of said
doped semiconductor layer, and an impurities concentration of
said source resistance decreasing layer is sufficiently higher
- 11 -

than an impurity concentration of said doped semiconductor
layer.
5. A compound semiconductor device comprising: an
undoped semiconductor layer;
a doped semiconductor layer formed on said undoped
semiconductor layer and having smaller electron affinity than
said undoped semiconductor layer, impurities being doped in
said doped semiconductor layer;
a gate electrode formed in said doped semiconductor
layer;
a cap layer formed on said doped semiconductor layer;
a source electrode and a drain electrode formed on said
cap layer; and
a source resistance decreasing layer formed between the
doped semiconductor layer and the cap layer, wherein said
source resistance decreasing layer comprises a first
semiconductor layer having the same composition and impurities
as those of said doped semiconductor layer and an impurity
concentration substantially indentical with an impurity
concentration of said doped semiconductor layer, and a planar-
doped semiconductor layer of high impurity concentration
provided in a vicinity of a centre of said first semiconductor
layer.
- 12 -

Description

Note: Descriptions are shown in the official language in which they were submitted.


2078940
COMPOUND SEMICONDUCTOR DEVICE
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a diagram of a HEMT structure of the prior
art;
Figs. 2(a) and 2(b) are energy band diagrams in cross
sections of the HEMT structure shown in Fig. 1 taken along line
X-X' and along line Y-Y' respectively;
Fig. 3 is a diagram of the structure of a compound
semiconductor device of a HEMT structure to which the present
invention is applied;
Fig. 4 is an energy band diagram in a cross section
taken along line X-X' of the device of Fig. 3 according to a
first embodiment;
Fig. 5 is a diagram of the structure of a device
according to a second embodiment of the present invention;
Fig. 6 is an energy band diagram in a cross section
taken along line X-X' of the device shown in Fig. 3 according
to a third embodiment;
Fig. 7 is a diagram of the structure of a device
according to a fourth embodiment of the present invention; and
Fig. 8 is an energy band diagram in a cross section
taken along line X-X' of the device shown in Fig. 7.
BACKGROUND OF THE INVENTION
The present invention relates to a compound
- 1 -

2078940
semiconductor device such as a HEMT (High Electron Mobility
Transistor).
A HEMT structure is attracting attention as a field-
effect transistor making use of a two-dimensional electron gas
accumulated in a heterojunction interface. As shown in Fig.
1, this HEMT structure comprises an undoped semiconductor layer
2 disposed on a substrate 1; a doped semiconductor layer 3
whose electron affinity is smaller than that of the undoped
semiconductor layer 2 and in which impurities are doped; a gate
electrode 4 formed on the doped semiconductor layer; and a
source electrode 6 and a drain electrode 7 which are
respectively formed in a cap layer 5 provided on the doped
semiconductor layer at both sides of the gate electrode 4. In
this HEMT structure, all the donor impurities added to the
doped semiconductor layer 3 having smaller electron affinity
are ionized, and electrons resulting from this ionization are
accumulated in a heterojunction interface with respect to the
undoped semiconductor layer 2 having greater electron affinity,
thereby forming a two-dimensional electron gas 8.
This two-dimensional electron gas 8 can be controlled
by application of a voltage to the gate electrode 4, so that
a current flowing across the source and the drain can be
controlled. At that time, the current flowing from the source
passes through a plurality of passages, as shown at I1 and I2,
to the two-dimensional electron gas 8.
. .. ~

2078940
Fig. 2 shows energy bands, in which Fig. 2(a) and Fig.
2(b) are energy band diagrams of a cross section taken along line
X-X' and of a cross section taken along line Y-Y', respectively.
It should be noted that, in these drawings, EF denotes the Fermi
level.
Since the doped semiconductor layer 3 is in a
completely ionized state, electrons must pass between the cap
layer 5 and the two-dimensional electron gas 8, i.e., though the
completely ionized doped semiconductor layer 3, by means of the
tunnelling effect. For that reason, there have been drawbacks
in that the source resistance becomes very large, and that the
noise characteristic particularly in a high-frequency band is
degraded.
SUMMARY OF THE Ihv~NllON
The present invention has been made in view of these
points, and has an object to provide a compound semiconductor
device of a HEMT structure in which the source resistance is
reduced and the noise characteristic is thereby improved.
To attain the aforementioned object, according to a
first aspect of the present invention, there is provided a
compound semiconductor device comprising: an undoped
semiconductor layer; a doped semiconductor layer formed on the
undoped semiconductor layer and having smaller electron
affinity than the undoped semiconductor layer, impurities being
doped in the doped semiconductor layer; a gate electrode formed
on the doped semiconductor layer; a cap layer formed on the
doped semiconductor layer at both sides of the gate electrode
-- 3

2078940
and a source electrode and a drain electrode respectively
formed on the cap layer, wherein an undoped-material layer,
having greater electron affinity than the doped semiconductor
layer and the cap layer, is formed between the doped
semiconductor layer and the cap layer.
In accordance with this arrangement, the overall
potential of the energy bands in a cross section on the source
side including the cap layer is lowered. For that reason, the
doped semiconductor layer is not completely ionized, and
electrons remain in a central portion of the doped
semiconductor layer. Correspondingly, it becomes easy for
electrons to pass through the doped semiconductor layer, and
the source resistance lowers.
According to a second aspect of the present
invention, there is provided a compound semiconductor device
comprising: an undoped semiconductor layer; a doped
semiconductor layer formed on the undoped semiconductor layer
and having smaller electron affinity than the undoped
semiconductor layer, impurities being doped in the doped
semiconductor layer; a gate electrode formed on the doped
semiconductor layer; a cap layer formed on the doped
semiconductor layer at both sides of the gate electrode; and
a source electrode and a drain electrode respectively formed
on the cap layer, wherein a layer which has the same
composition and impurities as those of the doped semiconductor
layer and whose impurity concentration is sufficiently higher
than an impurity concentration of the doped semiconductor layer
-- 4 --

2078940
is provided between the doped semiconductor layer and the cap
layer.
In addition, according to a third aspect of the
present invention, an arrangement may be provided such that a
layer which has the same composition and impurities as those
of the doped semiconductor layer and whose impurity
concentration is substantially identical with an impurity
concentration of the doped semiconductor layer is provided
between the doped semiconductor layer and the cap layer, and
a planar-doped layer of a high concentration is provided in the
vicinity of a centre of that layer.
Since the newly provided layer mentioned above
includes impurities of a high concentration, the potential of
this layer drops, with the result that the potential of the
doped semiconductor layer also drops. Then, in the vicinity
of the centre of the doped semiconductor layer is not
completely depleted, and electrons remain therein. For that
reason, the passage of the electrons through this doped
semiconductor layer is facilitated, so that a resistance value
on the source side in the HEMT declines correspondingly,
thereby improving the noise characteristic.
DETATT~n DESCRIPTION OF THE PREFERRED EMBODIMENTS
In Fig. 3 in which a first embodiment of the present
invention is implemented, a noticeable difference from the
prior art shown in Fig. 1 lies in that a new layer 9 is
disposed between a cap layer 5 and a doped semiconductor layer
..~". .
t~

20 78 940
3. This layer 9 is made of a material having greater electron
affinity than the doped semiconductor layer 3 and the cap layer
5, is formed with a very small thickness, and is formed as an
undoped layer. This layer 9 is formed of, for example, an
undoped InGaAs layer with a thickness of several dozens
angstroms.
Here, the reason for forming the layer 9 with a small
thickness is that if it is thick, the crystal lattice constant
becomes large, making it difficult to form the layer 9.
Accordingly, if the layer 9 can be formed easily even if it is
relatively thick, the layer 9 need not be formed with a small
thickness. In Fig. 3, materials of the other layers are, for
example, as follows: an undoped semiconductor layer 2 is formed
of GaAs or InGaAs; the doped semiconductor layer 3 is formed of
n' AlGaAs; and the cap layer 5 is formed of GaAs.
If the aforementioned layer 9 is formed, the overall
potential of the energy band in the cross section taken along
line X - X' in Fig. 3, is lowered as shown in Fig. 4, and the
doped semiconductor layer 3 is not completely ionized, so that
electrons exist in the vicinity of the center thereof. For
this reason, the passing of the electrons through this doped
semiconductor layer 3 is facilitated, and the source-side
resistance is reduced correspondingly.
Fig. 5 shows a second embodiment in which the
aforementioned layer 9 is provided in a HEMT in which two
undoped semiconductor layers 2a and 2b are provided instead of

207 89 4 0
a single undoped semiconductor layer. A similar effect is
produced in this case as well. In Fig. 5, for instance, the
undoped semiconductor layer 2a is formed of InGaAs, while the
undoped semiconductor layer 2b is formed of AlGaAs.
Furthermore, a buffer layer formed of GaAs ma~ be interposed
between a substrate 1 and the undoped semiconductor layer 2a.
According to a third embodiment of the present
invention, the structure of a compound semiconductor device is
the same as that shown in Fig. 3. However, according to the
third embodiment, the layer 9 has the same composition as the
doped semiconductor layer 3 and its impurities are the same,
but the concentration of the impurities is sufficiently higher
than the impurity concentration of the doped semiconductor
layer 3.
According to the third embodiment, the newly provided
layer 9 is formed of AlGaAs of a high impurity concentration.
It should be noted that also in this embodiment, the undoped
semiconductor layer 2 may be formed of a two-layered structure
comprising the InGaAs layer 2a and the AlGaAs layer 2b as shown
in Fig. S. In addition, a buffer layer of GaAs may be added
between the substrate 1 and the undoped semiconductor layer 2.
Since the layer 9 is provided according to the third
embodiment, the potential of an energy band in a cross section
taken along line X-X' of Fig. 3 drops in the portion of the
layer 9, as shown in Fig. 6, so that the potential in the
vicinity of the center of the doped semiconductor layer 3 also

207 89 40
drops together with the decrease of the former potential,
causing electrons to remain in the doped semiconductor layer 3.
For this reason, the electrons which advance from the cap layer
5 side to the undoped layer 2 side can easily pass through the
doped semiconductor layer 3. This means that the resistance on
the source side is lowered.
An noise figure is given by
NF = 1 + K(f/fT)~{gm(Rs + Rg)}
In this formula, K is a fitting constant; f, a frequency; fT,
a cutoff frequency; gm, a mutual conductance; Rs, a source
resistance; and Rg, a gate resistance.
As can be seen from this formula, the noise is reduced
in the HEMT having a small source resistance Rs as in the
above-described embodiments.
Next, in a fourth embodiment shown in Fig. 7, the layer
9 is arranged to have the same composition and impurities as
those of the doped semiconductor layer 3, and further the
concentration of the impurities of the layer 9 is set to be
substantially identical with that of the doped semiconductor
layer 3. However, a planar-doped layer 10 having the same
impurities and a high concentration is disposed in the vicinity
of the center of the layer 9. The arrangements of the other
portions are the same as those of Fig. 3.

2078940
According to the fourth embodiment, the energy band in
a cross section taken along line X-X' of Fig. 7 becomes such as
the one shown in Fig. 8, in which a portion whose potential
drops sharply by the planar-doped layer 10, exists in the layer
9. As a result, the potential of the doped semiconductor layer
3 also drops, and electrons exist in the vicinity of the center
thereof. Thus, in the same way as described in connection with
the former embodiments shown in Fig. 3, the source resistance
drops, and the noise figure is lowered.
As described above, in accordance with the compound
semiconductor device of the present invention, advantages are
obtained in that the source resistance becomes small, and that
the noise figure is improved.

Representative Drawing
A single figure which represents the drawing illustrating the invention.
Administrative Status

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Event History

Description Date
Inactive: IPC from MCD 2006-03-11
Inactive: IPC from MCD 2006-03-11
Time Limit for Reversal Expired 2003-09-23
Letter Sent 2002-10-21
Grant by Issuance 1996-11-12
Application Published (Open to Public Inspection) 1993-04-30
All Requirements for Examination Determined Compliant 1993-02-19
Request for Examination Requirements Determined Compliant 1993-02-19

Abandonment History

There is no abandonment history.

Fee History

Fee Type Anniversary Year Due Date Paid Date
MF (patent, 5th anniv.) - standard 1997-09-23 1997-08-13
MF (patent, 6th anniv.) - standard 1998-09-23 1998-08-12
MF (patent, 7th anniv.) - standard 1999-09-23 1999-08-18
MF (patent, 8th anniv.) - standard 2000-09-25 2000-08-16
MF (patent, 9th anniv.) - standard 2001-09-24 2001-08-17
Owners on Record

Note: Records showing the ownership history in alphabetical order.

Current Owners on Record
ROHM CO., LTD.
Past Owners on Record
YOSHIKAZU NAKAGAWA
Past Owners that do not appear in the "Owners on Record" listing will appear in other documentation within the application.
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Document
Description 
Date
(yyyy-mm-dd) 
Number of pages   Size of Image (KB) 
Abstract 1994-02-26 1 31
Cover Page 1994-02-26 1 21
Description 1994-02-26 9 331
Claims 1994-02-26 2 67
Drawings 1994-02-26 3 52
Description 1996-11-12 9 313
Cover Page 1996-11-12 1 14
Abstract 1996-11-12 1 27
Drawings 1996-11-12 3 31
Claims 1996-11-12 3 102
Representative drawing 1998-10-26 1 4
Maintenance Fee Notice 2002-10-21 1 175
Fees 1998-08-12 1 44
Fees 1997-08-13 1 43
Fees 1996-08-13 1 38
Fees 1995-08-10 1 41
Fees 1994-08-09 1 35
PCT Correspondence 1996-09-03 1 40
Examiner Requisition 1995-11-21 1 41
Prosecution correspondence 1993-02-19 1 31
Prosecution correspondence 1996-03-15 3 56