Note: Descriptions are shown in the official language in which they were submitted.
2n85~24
SEI 92-36
1 TITLE OF THE INVENTION
.
Field Eifect Transistor and Method ior
Manufacturing the Same
BACKGROUND OF THE INVENTION
Field o.4 the Invention
The present invention relates to a high power ~4ield
eil4ect transistor (FET) and method for manuiacturing the
same.
Related Background Art
Because a high power FET needs a high drain
breakdown voltage, an FET having the ~ollowing structure
has been proposed. An example is a recessed FET. In
such an FET, a recess is l40rmed in a gate region by
etching. As a gate electrode is iormed in the recess, a ~
source-gate distance is extended and a drain breakdown ~ -
voltage i8 enhanced. In order to enhance the drain
breakdown voltage, it has also been proposed to space a
reiractry gate electrode irom a drain region ("A New
Re4ractory Seli-Alighned Gate Tschnology ior GaAs
Microwave Power FET's and MMIC's" IEEE TRANSACTIONS ON
ELECTRON DEVICES, vol. 35, No. 5, May 1~88).
However, in the prior art FET having the recess :~
structure, since the gate region is recessed by etching,
it has been diiiicult to attain a highly reproducible
device characteristic because oi reproducibility and
controllability oi etching.
- 2~8~2~
SEI 92-36
1 In the FET discolsed in the above re~erence, the
gate region is o~ non-etched planar structure but the
material o~ the gate electrode must be a re~ractory
material having a heat resistance, and a gate resistance
is high. Further, it is dif~icult to attain a gate
electrode o~ sub hal~ micron such as gate length o~ 0.5
~m.
SUMMABY OF THE INVENTION ~ :
It is an object o~ the present invention to provide
a ~ield e~ect transistor having a high gate breakdown
voltage and a short gate length, and method ~or
manu~acturing the same.
In order to achieve the above object, the FET o~ the
present invention comprises:
an active layer ~ormed in a sur~ace layer o~ a
semiconductor substrate;
a source highly doped impurity region and a drain
highly doped impurity region iormed in the sur~ace layer
o~ the semiconductor substrate to sandwich the active
layer;
an insulation ~ilm ~ormed on the source highly doped
impurity region;
a gate electrode ~ormed on the active layer and the
insulation ~ilm while maintaining a constant distance
~rom the drain highly doped impurity region; and
a source electrode and a drain electrode ~ormed on
2~85$2~
SEI 92-36
1 the source highly doped impurity region and the drain
highly doped impurity region respectively.
The method ~or manu~acturing the FET o~ the present
invention comprises the step o~:
~ orming an active layer in a surface layer o~ a
semiconductor substrate;
~ orming a dummy gate on the active layer;
~ orming a source highly doped impurity region and a
drain highly doped impurity region in the sur~ace layer
o~ the semiconductor substrate by ion implantation using -
the dummy gate as a mask;
depositing an insulation ~ilm on the sur~ace o~ the
semiconductor substrate and liiting of~ the insulation
~ilm oi the dummy gate area by using the dummy gate;
removing the insulation ~ilms on the source highly
doped impurity region which are spaced ~rom the active :
layer and ~orming a source electrode and a drain elctrode
in the exposed areas; and : -
~orming on the active layer a gate electrode having . .
one end thereor spaced ~rom the drain highly doped
impurity region and the other end thereo~ overlapped on ~ .
; the imsulation ~ilm on the source highly doped impurity
region. .
In accordance with the FET oi the present invention,
since a portion o~ the gate elctrode is ~ormed on an
insulation ~ilm adjacent to the source electrode in an
20~24
SEI 92-36
~ 1 overlapped and or~set fashion, a certain distance is
; secured between the gate elctrode and the drain
electrode. As a result, a high drain breakdown voltage
is attained. An essential gate length is a portion Or
~ the gate electrode which contacts to an active layer, and
s it is shorter than the length Or the gate electrode
~^ itselr.
The present invention will become more ~ully
understood rrom the detailed description given
hereinbelow and the accompanying drawings which are
given by way o~ illustration only, and thus are not to be
considered as limiting the present invention.
Further scope Or applicability Or the present
invention will become apparent rrOm the detailed
description given hereinarter. However, it should be
understood that the detailed description and speciric
~ examples, while indicating prererred embodiments Or the
i invention, are given by way Or illustration only, since
~ various changes and modirications within the spirit and
¦~ 20 scope Or the invention will become apparent to those
skilled in the art iorm this detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
Figs. lA-lG show process sectional views Or one
embodiment Or the method rOr manuracturing FET Or the
¦ present invention,
I Fig. 2 shows a graph Or experimental data on a
2~8~24
SEI 92-36
1 relation between a distance lGD and a gate-drain
breakdown voltage, and
Fig. 3 shows a graph o+~ IdS-Vds characteristics of an
FET having distance 1~ o~ 1.5 ~m and an FET having
distance 16Dof 7.0 ~m. ~-
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
.
Figs. lA-lG show sectional views in a manuiacturing
process to complete a Schottky barrier type FET (MESFET)
in one embodiment oi the present invention. The
manu~acturing process is explained below.
First, an active layer 2 is ~ormed in a suriace -~ -
layer oi a semi-insulative GaAs semiconductor substrate
1. Then, a silicon nitride film 10 is deposited on the
suriace oi the semiconductor substrate 1 to a thichness
oi approximately lOOOA (see Fig. lA). The active layer 2
may be iormed by an ion implantation method in which Si+
ions having dose oi 3 x 1012/cm2 are accelerated under an
elctric iield oi 30KeV. The silicon nitride iilm 10 may
be iormed by a CVD method. The silicon nitride iilm 10
is used as a protection iilm ior a annealing process,
which will be taken place later, ior the active layer 2.
Then, a dummy gate 3 in iormed by a
opticallithography technique. A material oi the dummy
gate 3 is a resist material, and a dimension ld oi the
dummy gate 3 corresponding to the gate length is, ior
example, 2 ~m. Then, a highly doped n+layer (n+ region)
2~552~
SEI 92-36
1 4 having a high impurity concentration is formed by an
ion implantation method using the dummy gate 3 as a mask
(see Fig. lB). The ion implantation is carried out while
Si+ ions having dose o~ 4 x 10l3/cm2 are accelerated under
application Or an electric rield Or 120 KeV. In Fig. lB,
a lefthand n+ region 4 is a source highly doped impurity
region, and a righthand n+ region 4 is a drain highly
doped impurity region.
Then, the gate length Or the dummy gate 3 is
slightly reduced. It is done by slightly and
isotropically grinding the entire ~urrace (top surrace
and side surrace) Or the dummy gate 3 by 2 plasma
etching (see Fig. lC).
Then, an insulation rilm 5 made oi SiO2 is formed
on the entire æurrace Or the substrate including the
reduced dummy gate 3 (see Fig. lD). The dummy gate 3 is
then lirted o~i to rOrm an insulation iilm 5 having a
inversion pattern to the dummy gate 3 (see Fig. lE).
Then, in order to activate the Si+ ions implanted into
the semiconductor substrate 1, it is annealed at 800 C
ror ~0 minutes. Then, ohmic electrode rormation areas in
the insulation rilm 5 and the anneal protection rilm 10
are selectively removed by using a opticallithographic
technique and an RIE method. A source electrode B and a
drain electrode 2 which are made or AuGe/Ni metal are
~ormed on the n+ region 4 exposed by the removal (see
20~52~
SEI 92-36
- 1 Fig. lF).
-- A~ter the ~ormation o~ the ohmic electrodes, a gate
electrode pattern is formed on the substate by the
opticallithography technique. The pattern is ~ormed to
be of~set toward the source electrode 6, that is, the
center o~ the gate is o~set toward the source electrode
ff. A low resistance metal made of Ti/Pt/Au is vapor-
deposited on the gate electrode pattern, and the metal o~
unnecessary areas is removed by the li~t-o~ method to ~
~orm a gate electrode 8. As a result, an MESFET having a ;~-
structure shown in Fig. lG is completed. A portion o~
the gate electrode 8 contacts to the active layer 2 and
the remaining portion overlaps on the insulation ~ilm 5
which is adjacent to the source electrode 6.
Prior to the ~ormation o~ the gate electrode 8, the
anneal protection ~ilm 10 in the gate electrode ~ormation -
area on the active layer 2 is removed. Where the anneal
protection ~ilm 10 is the silicon nitride ~ilm as it i9
in the present embodiment, it may be removed by the RIE
' 20 method using CF4. I~ the active layer 2 is annealed in
! an atmosphere o~ AsH3, anneal protection ~ilm 10 is not
necessary.
In accordance with the present embodiment, since a
I portion o~ the gate electrode 8 is ~ormed on the
f insulation iilm 5 on the side o~ the source electrode 6
in the overlapped and oriset ~ashion, a constant distance
' ~.'
2~8~2~
SEI 92-36
lGD (1.5 ~m in the present embodiment) is secured between
the gate electrode 8 and the n+ region 4 on the drain
side. As a result, the drain breakdown voltage o~ the
' FET may be enhanced. Further, since only the portion of
Z the gate electrode 8 is ~ormed on the active layer 2, the
essential gate length lg is determined by the portion o~
the gate electrode 8 which contacts to the active layer
2. Namely, assuming that the metal length lM o~ the gate
electrode 8 is 1.0 ~m and the overlap o~ the source
electrode 6 on the insulation film 5 is 0.5 ~m, the
actual gate length lg is 0.5 ~m.
Fig. 2 shows a graph o~ an experimental result on a
relationship between the distance l~ and the gate-drain
breakdown voltage (drain breakdown voltage). According
to the experimental result, when the distance lOEZexceeds
1 ~m, the gate-drain breakdown voltage starts to saturate
and it substantially saturates over 1.5 ~m.
On the other hand, ii the distance lOEZis too long, a
device area increases and an electric ~ield concentrates
towards the drain electrode so that a channel may be
broken between the source and the drain. Fig. 3 shows a
graph o~ IdS-Vds characteristics ~or the FET o~ the
present embodiment having the distance lOE o~ 1.5 ~m and
an FET having the distance l~ of 7.0 ~m. As seen ~rom
the graph, when the distance l~ is 7.0 ~m, the breakdown
occurs when the source-drain voltage Vds exceeds 10
2~8~5~4
SEI 92-36
1 volts. On the other hand, when the distance lGD is 1.5
~m, the breakdown does not occur even if a higher voltage -
is applied. In practice, it is pre~erable that the
distance lGD is smaller than 5 ~m.
In accordance with the FET o~ the present invention, ~i
a high drain breakdown voltage is attained by controlling
the distance 1~.
Further, since the gate electrode 8 overlaps on the
insulation ~ilm 5, the real gate length lg by which the
gate electrode 8 contacts to the active layer 2 can be
readily shortened, and it is possible to readily
manu~acture the gate length o~ substantially sub-half-
micron.
In accordance with the manufacturing method o~ the
present invention, since the n~ region 4 is ~ormed by the
ion implantation method using the dummy gate 3 as the
mask, it is not necesæary to use a re~ractory material
ior the gate eletrode 8. Aceordingly, a gate metal
having a low resistanee may be used and the increase o~
the gate resistance is avoided. On the side o~ the
source eleetrode 6, the n~ region 4 is sel~-aligned to
the gate eleetrode 8 whieh is formed at the plaee oi the
dummy gate 3. As a result, the resistanee between the
Schottoky eontaet to the souree eleetrode 6 is redueed -~
and a source parasitie capacitance is reduced.
The FET o~ the present invention may be e~ectively
-
2a~5~2~
SEI 9Z-36
1 utilized as a high power device in a high ~requency band.
From the invention thus described, it will be
obvious that the invention may be varied in many ways.
Such variations are not to be regarded as a departure
~rom the spirit and scope o~ the invention, and all such
modi~ications as would be obvious to one skilled in the
art are intended to be included within the scope o~ the
~ollowing claims.
