Note: Descriptions are shown in the official language in which they were submitted.
- 1 2Q 9 4 7 ~ 4
MULTILAYER BOARD AND FABRICATION
METHOD THEREOF
The present invention relates to a multilayer
board used as a printed wiring board which consists of a
base material on which a plurality of circuit patterns
are formed through an insulating layer and a fabrication
method thereof.
BACKGROUND OF THE INVENTION
In order to increase the circuit density of a
board including a base material having formed thereon a
wiring pattern, or make it multifunctional or small-
sized, there have been developed and proposed variousboards such as one having interstitial via holes, and
one including a base material on which a plurality of
wiring patterns are laminated through an insulating
layer.
Typical examples of conventional multilayer
boards include the followings. The term "double-sided
board" as used herein refers to a board which has
provided thereon a wiring pattern on each side thereof.
(1) PRINTED CIRCUITS HANDBOOK, chapters 33.2-3.8
(3rd Ed.; 1988) describes a multilayer board as shown in
Fig. 2, which includes double-sided boards 105 and 105'
each having a wiring pattern 104 on each side thereof and
a via hole 103 formed by plating a through hole, are
laminated through a prepreg consisting of an adhesive
resin, with connection between the wiring patterns of the
laminated double-sided board being established by forming
a common via hole 102 penetrating all the layers.
(2) Denshi Zairyo (April, 1991) page 103-108
describes a multilayer board as shown in Fig. 3. That
is, a first layer wiring pattern 108 is formed on a base
material 106. A second wiring pattern 109 made of a
plating layer is formed on the first wirinq pattern 108
through an insulating layer 7, and a third wiring
pattern 109' made of a plating layer is formed on the
second wiring pattern 109 through an insulating layer
107'. In addition, a fourth or more wiring patterns are
formed, and a through hole 102 penetrating all the layers
is formed. Finally, an electric source layer 10 is
connected as an outermost layer.
t3) Japanese Utility Model Application Laid-Open
No. 16482/1988 describes a board as shown in Fig. 4.
That is, a base material 106 has provided thereon a first
layer wiring pattern 108 made of a plating layer, and
wiring patterns 109 and 109' are serially formed on the
first layer wiring pattern 108 through insulating layers
107 and 107', respectively. The insulating layers
between the wiring patterns are provided with inter-
stitial via holes 111 filled with a conductive paste so
- as to be flush with the insulating layer to thereby
establish electrical connection between the wiring
patterns.
Among the aforementioned, the multilayer board
described in (1) above is a popular one which is now put
into practical use. In such a multilayer board, a
plurality of double-sided boards 105 and 105' separately
fabricated are laminated through a prepreg 101, which
requires a very high precision in the alignment between
the boards. That is, it is necessary that the through
hole 102 provided after a plurality of boards are
laminated so as to penetrate all the layers should
certainly penetrate at predetermined places in each
wiring pattern. If such alignment of the laminate is
missed, there occurs faulty immediately. Therefore, it
has been necessary to ensure a penetration portion rather
with some allowance in each wiring pattern. This hinders
increase in the circuit density. When electroconduction
is obtained between the through hole 102 penetrating all
the layers and intermediate wiring patterns by means of
the through hole 102, the contact area between the two is
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small and a problem arises in the reliabi]ity of
electrical connection. In addition, through holes are
provided also in those wiring patterns which do not need
electroconduction, which limits freedom in wiring. This
also hinders increase in the circuit density.
Further, the aforementioned multilayer board is
very complicated in the manufacture since it not only
requires at least two plating operations in the step of
manufacturing a unit board but also requires steps of
laminating a unit board, producing an opening through the
board, plating, etc.
The multilayer board described in (2) above
also has a through hole 102 penetrating all the layers,
and like the multilayer board described in (1) above,
hinders increase in the circuit density. Wiring pattern
is laminated on one surface of the base material, and
hence the degree of increase in the number of electrical
connection terminals between the wiring patterns is
greater than the increase in the number of pattern
layers. This also hinders increase in the circuit
density.
Further, in the manufacture of the afore-
mentioned multilayer boards, formation of an insulating
layer and plating must be performed each once in order to
form a single layer of wiring pattern. After all the
wiring pattern have been formed, production of openings
through the board and plating must be performed, and this
leaves room for further improvement in the manufacture.
The multilayer board described in (3) above
connects a plurality of wiring patterns laminated through
an insulating layer by means of an opening provided in
the insulating layer and filled with a conductive paste.
However, the opening differs from a hole in that the
opening has a closed bottom and hence the conductive
paste filled and cured therein tends to form a space
between it and the surface of the wiring pattern which it
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originally contacted since it shrinks upon curing. There
is a room for improvement in reliability of electrical
connection. Similarly to (2) above, wiring patterns are
laminated on one side of the base material, and the
degree of increase of the number of electrical connection
terminals is greater than the increase in the number of
wiring pattern layers, which hinders increase in the
wiring density.
Furthert in the fabrication of the afore-
mentioned multilayer boards, curing of the conductivepaste filled in the insulating layer and the opening must
be performed for each layer. Thereforel the board is
subjected to thermal hysteresis twice for each connection
between the wiring patterns, which not only makes produc-
tion procedure complicated but also causes problem ofthermal deterioration of the board.
In the multilayer boards described in (2) and
(3) above, electronic components are mounted on only one
surface of the board, leading to decrease in the mounting
density.
Therefore, an object of the present invention
is to solve the aforementioned problems encountered in
- the conventional techniques, and to provide a multilayer
board which has a high reliability of electrical connec-
tion between wiring patterns laminated thereon, enables
increase in circuit density, and also increase in the
density of mounting components thereon.
Another object of the present invention is to
provide a method of fabricating the aforementioned
multilayer board.
SUMMARY OF THE INVENTION
The present inventors have made extensive
investigation in order to achieve the above-described
objects, and as a result they have found that use of a
double-sided board having a smoothed surface, fabricated
by forming a first layer wiring pattern on both sides of
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a base material, and filling a conductive material in a
hole penetrating through the base material to form a via
hole portion, enables formation of an insulating layer on
the double-sided board and of wiring patterns from a
plating layer with a high precision. It has been found
that formation of a plating layer through an insulating
layer on both sides of the double-sided board, and
formation of wiring pattern from the plating layer, as
well as electrical connection between the wiring
patterns, and between the wiring pattern and the via hole
portion enables formation of wiring patterns with high
degree of freedom without separately providing via hole
portions penetrating all the layers, which makes it
possible to increase circuit density. Further, it has
been found that lamination of wiring patterns on both
surfaces of the double-sided board enables mounting of
electronic components on both surfaces of the board. In
the fabrication procedure, lamination of wiring patterns
on both surfaces of the double-sided board enables
formation of insulating layers, plating layers, and
wiring patters from the plating layers to be performed
simultaneously, which makes the fabrication procedure
more efficient.
Thus, the present invention provides a
/ 25 multilayer board comprising: a smooth-surfaced double-
sided board having: a base material provided with a hole
penetrating therethrough, a first layer wiring pattern
provided on both surfaces of the base material and having
a surface, and a conductive material filled in the hole,
the filler material having end surfaces beîng flush with
the surface of the first layer wiring pattern, thus
forming a via hole portion having end surfaces; an
insulating layer provided on each surface of the base
material, the insulating layer being formed with an
opening having an inner wall; and a second layer wiring
pattern comprising a plating layer provided on at least
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one surface of the double-sided board through the
insulating layer; wherein at least a portion of one of
the end surface of the second layer wiring pattern is
exposed in the opening, and wherein the inner wall of the
opening and exposed portion of the end of the via hole
portion is continuously coated with a plating layer
connecting to the plating layer of the second layer
wiring pattern, thus establishing electrical connection
between the second wiring pattern and the via hole
10 portion~
Further, the present invention provides a
method of fabricating a multilayer board, comprising the
steps of:
fabricating a smooth-surfaced double-sided
board having: a base material provided with a hole
penetrating therethrough, a first layer wiring pattern
provided on both surfaces of the base material and having
a surface, an a conductive material filled in the hole,
the filler material having ends being flush with the
surface of the first layer wiring pattern, thus forming a
via hole portion having ends; providing on at least one
surface of the double-sided board an insulating layer
being formed with an opening having an inner wall in
which at least of a portion of the ends of the via hole
portion is exposed; coating an outer surface of the
insulating layer, the inner wall of the opening and
exposed portion of the ends of the via hole portion with
a continuous plating layer; and etching predetermined
places of the plating layer to form a second layer wiring
pattern.
Achievement of the aforementioned objects and
other objects will become apparent by the following
description.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a cross sectional view showing an
example of a multilayer board of this invention;
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Fig. 2 is a cross sectional view showing an
example of a conventional multilayer board;
Fig. 3 is a cross sectional view showing
another example of a conventional multilayer board;
Fig. 4 is a cross sectional view showing still
another example of a conventional multilayer board;
Fig. 5 is a cross sectional view showing
another example of a multilayer board of this invention;
Fig. 6 is a series of cross sectional views
showing an example of the fabrication procedure of a
multilayer board of this invention;
Fig. 7 is a series of cross sectional views
showing another example of the fabrication procedure of a
multilayer board of this invention;
Fig. 8 is a series of cross sectional views
showing the fabrication procedure of a double-sided board
used in the fabrication procedure shown in Fig. 6;
Fig. 9 is a series of cross sectional views
showing the fabrication procedure of a double-sided board
used in the fabrication procedure shown in Fig. 7;
Fig. 10 is a schematic diagram illustrating
patterns for thermal shock test on a multilayer board of
this invention according to JIS C-5102; and
Fig. 11 is across sectional view showing an
example of a multilayer board of this invention having
three layers of wiring patterns on a single surface.
DESCRIPTION OF PREFERRED EMBODIMENTS
Representative embodiments of the multilayer
board of this invention are shown in cross section in
Figs. 1 and 5.
As shown in Figs. 1 and 5, the multilayer board
of this invention includes a double-sided board 5 having
a smooth surface, which has first layer wiring patterns
2,2' on a base material 1, and a via hole portion A. The
via hole portion A is formed by filling a conductive
material 4 in a hole 3 penetrating the base material, and
2~9~754
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processing so that the ends of the material are
substantially flush with the surfaces of the first layer
wiring patterns 2,2'. On both surfaces of the double-
sided board 5 are formed second layer wiring patterns
7,7' made from a plating layer through an insulating
layer 6. The insulating layer 6 is provided with an
opening 8 so that a portion of the ends of the via hole
portion A can be exposed therein. Also, the insulating
layer 6 is provided with another opening 8' so that a
portion of a terminal portion 9 of the first layer wiring
patterns 2 can be exposed therein. A continuous plating
layer is coated over the outer surface of the insulating
layer 6, the inner walls of the openings 8,8', the
exposed surface of the via hole portion, and the exposed
surface of the terminal portion 9, and required places of
the plating layer on the insulating layer 6 are etched
to form the second layer wiring patterns 7,7'. The
continuous plating layer electrically connects the second
wiring patterns 7,7' to the via hole portion A, and the
first layer wiring patterns to the second layer wiring
patterns.
As the base material 1, any known ones made of
a known material and has a known configuration may be
used without restriction. Representative examples
include synthetic resin laminate such as phenolic paper
laminate, epoxy-paper laminate, polyester paper laminate,
epoxy-glass laminate, PTFE resin-paper laminate,
polyimide-glass laminate, BT (bismaleimide triazine)-
glass laminate, and composite laminate; flexible board
such as polyimide board or polyester board, metallic base
material obtained by coating with an epoxy resin a
- perforated plate of metal such as aluminum, iron,
or stainless steel, or ceramic board.
Material of the first layer wiring patterns
2,2' formed on both surfaces of the base material 1 is
not limited particularly and any known conductive
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g
material may be used freely. Representative materials
are, for example, copper, nickel, aluminum, etc. Among
them, copper is used most preferably. The thickness of
the wiring patterns is not limited particularly.
Generally, a thickness of S to 70 ~m is suitable.
In the aforementioned double-sided board, the
via hole portion A is formed by filling the material 4
having an conductivity in the hole 3 provided through the
base material in such a manner that the end surfaces of
the filler material are smooth and substantially flush
with the both surfaces of the double-sided board. As
I such a material having a conductivity, any known material
may be used without limitation. For example, it is
typically a cured material derived from a curable
conductive substance which gives rise to a cured material
having an conductivity. As the curable conductive
substance, there can be used known curable conductive
substances obtained by mixing a conductive material such
as gold, silver, copper, nickel, lead, or carbon with a
known crosslinking thermosetting resin, together with an
organic solvent as necessary to form a paste.
In order to form a via hole portion having a
good conductivity, it is preferred to select conductive
material and adjust the amount of each component when the
aforementioned curable conductive substance is prepared
so that the electric resistance after curing can be
1 x 10 2Q cm or less.
Further, the diameter of the via hole portion
is not limited particularly, and may be set freely.
Generally, the diameter of the via hole portion may be
one which enables filling of the aforementioned curable
conductive substance, specifically, at least 0.2 mn"
preferably within the range of 0.3 to 2 mm.
In the formation of the via hole portion, the
electric reliability of the via hole portion can further
be increased by forming the outermost layer of the filler
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material having an conductivity to be filled in the hole
3 from a plating layer.
Electrical connection between the first layer
wiring patterns 2,2' and the via hole portion A in the
aforementioned double-sided is preferably achieved by
providing a land portion 11 around the via hole portion A
in the first layer wiring pattern. In this case, in
order to further increase the electrical connection
between the land portion and the via hole portion, it is
preferred to coat the end surfaces of the land portion
and the via hole portion with a continuous plating layer
12. The plating layer 12 may be provided either inde-
pendently as shown in Fig. 1, or the plating layer
constituting the wiring patterns 7,7' laminated as shown
in Fig. 5 may be utilized.
In the present invention, on at least one
surface of the aforementioned double-sided board 5 is
formed at least one wiring pattern made of a plating
layer formed on the board through the insulating layer 6.
As the insulating layer 6, there can be used
any known material without limitation. For example,
suitable ones are conventional curable insulating resins
known as photosensitive insulating resist, for example
PROBIMER 52 ~trade name, produced by CIBA GEIGY),
PROBICOTE 5000 (trade name, proauced by NIPPON PAINT),
etc. The thickness of the insulating layer may be any so
far as the insulation between the wiring patterns present
on both surfaces thereof can be maintained, and generally
a thickness of 20 to 100 ~m is suitable.
The surface of the insulating layer is prefer-
ably roughened in order to increase adhesion of the
plating plate formed on the surface thereof. Method of
surface roughening is not limited particularly and there
can be any known methods such as physical scrubbing using
buff, brush, etc., chemical roughening by immersing in an
alkaline potassium permanganate solution, chromic acid
solution, etc.
.
2~9~7~
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Any known material may be used withaut limita-
tion for the plating layer constituting the wiring
pattern. For example, there can be cited, copper,
nickel, etc. Among them, copper is used most advan-
tageously. The thickness oE the plating layer may be anyso far as a thickness sufficient for exhibiting conduc-
tivity is ensured. Usually, the thickness is suitably 50
~m or less, preferably 5 to 35 ~m.
In the present invention, in the insulating
layer 6, there is provided an opening 8 for connecting
the wiring pattern and the via hole portion. The opening
is provided such that the terminal portion of the wiring
pattern and at least a portion of the end surface of the
via hole portion is exposed. In case the wiring patterns
are connected to each other, the opening 8 is formed so
that the terminal portion of the wiring pattern closer to
the double-sided board is exposed. The area of the
exposed portion may be to such an extent that electrical
connection can be established by coating a plating layer
10 as described below. Generally, the area of the
exposed portion exposed from the insulating layer may be
an area having a corresponding diameter of 50 ~m or more.
Furthermore, the shape of the opening is not limited
particularly, and any shape suitable for designing wiring
patterns, such as circle, ellipse, rectangle, square,
etc., may be adopted properly.
As shown in Fig. 5, the land portion 11 of the
first layer wiring pattern is provided around the via
hole portion A. If no plating layer is formed on the
surface thereof, it is desirable that all the end surface
of the via hole portion A is exposed and further area
including the land portion is exposed. The inner wall of
the opening and the land portion of the first layer
wiring pattern and the via hole portion which are exposed
in the opening are coated with a plating layer which is
continuous with the plating layer of the laminated wiring
~ 12 _ 2~947 ~4
patterns~ For example, Fig. 5 shows a structure in which
the land portion 11 of the first layer wiring pattern 2'
and the end surface of the via hole portion A exposed in
the opening 8 are coated with a plating layer 12' which
continuous with the plating layer constituting the wiring
pattern 7'.
As other configuration of the multilayer board
of this invention, any known multilayer board structure
may be used without limitation. For example, though not
shown in the drawings, it is preferred to provide a layer
having a good resistance using a solder resist at
required or desired places in the outermost layer.
The multilayer boards according to the embodi-
ments shown in Figs. 1 and 5 are examples of 4-layer
board having formed one layer of wiring pattern, through
an insulating layer, on the first layer wiring pattern
present on the both surfaces of a double-sided board.
However, the present invention is not limited thereto,
and may be configured as one in which a further wiring
board is laminated through an insulating layer on the
second wiring pattern. Such an example is shown in Fig.
11 (1) to (4). That is, Fig. 11 shows some embodiments
in which a third layer wiring patterns 19,19' made of a
plating layer, are formed on the surfaces of the second
layer wiring patterns 7',7 through an insulating layer
18. Fig. 11(1) shows an embodiment in which a third
layer wiring pattern is formed on the second layer wiring
pattern of the multilayer board according to the embodi-
ment shown in Fig. 5. Fig. 11(2) shows an embodiment in
which a third layer wiring pattern is formed on the
second layer wiring pattern of the multilayer board
according to the embodiment shown in Fig. 1. Further,
Figs. 11(3) and 11(4) show an embodiment in which in the
position of the via hole portion the second layer wiring
pattern and the third layer wiring pattern connecting to
the via hole portion in order, or in which the third
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I layer wiring pattern is directly connected to the via
hole portion without intervention of the second layer
wiring pattern.
In these embodiments, formation of the
insulating layer 18 and the third layer wiring pattern,
and electrical connection between the third layer wiring
pattern and other layer or the via hole portion are
performed in a manner similar to the method of forming
the insulating layer 6 and the second layer wiring
10 pattern.
For example, the formation of the third layer
wiring pattern may be carried out by forming an insulat-
ing layer having an opening at predetermined places,
forming a plating layer, and etching it off at pre-
determined places. The electrical connection between thethird layer wiring pattern and the other wiring patterns
or the via hole portion may be performed as follows.
That is, the insulating layer 18 is provided with an
opening 21 such that at least a portion of the terminal
portion 9 of the first layer wiring pattern, the terminal
portion 20 of the second layer wiring pattern or the end
surface of the via hole portion can be exposed therein,
and the inner wall of the opening and the exposed portion
are coated with a plating layer which is continuous with
the plating forming the third layer wiring pattern 19,19'
to thereby connecting the third layer wiring pattern to
the second layer wiring pattern, the first layer wiring
pattern or the via hole portion.
In the aforementioned connection, in case the
third layer wiring pattern is directly connected to the
first layer wiring pattern or the via hole portion, it is
sufficient to provide an opening in the insulating layers
6 and 8 serially and then perform coating with the afore-
mentioned plating layer, as shown in Fig. 11(4).
Representative fabrication method of the
multilayer board of this invention is exemplified as
follows.
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That is, Fig. 6 is a cross sectional view
showing a fabricatlon procedure for fabricating a
multilayer board. As shown in Fig. 6, (1) on at least one
surface of a smooth-surfaced double-sided board S having
a base material 1 provided with a hole 3 penetrating
therethrough, first layer wiring patterns 2,2' provided
on both surfaces of the base material, and a conductive
filler material 4 filled in the hole, thus forming a via
hole portion A; (2) an insulating layer 6 is coated such
that an opening 8 is formed in which a terminal portion
13 of the first layer wiring pattern and the via hole
portion A which need be connected to a second layer
wiring pattern formed on the first layer wiring pattern
are exposed; (3) thereafter, the exposed portion, the
inner wall of the opening 8, and the surface of the
insulating layer are coated with a plating layer 14; (4)
predetermined places of the plating layer are etched to
form wiring patterns to thereby form second layer or more
wiring patterns 7,7' and a plating layer 10 for conduc-
tion which is continuous with the wiring patterns.
The method of forming the insulating layer 6 isnot limited particularly and any conventional method may
be used freely. &enera-lly, there can be used curable
insulating resins of various forms which cure by light or
heat, such as photosensitive dry film, liquid solder
resist, combination of photosensitive dry film and liquid
solder resist, etc. As the method of forming the insulat-
ing layer, printing method, photographic method, etc. may
be selected properly depending on fineness using the
aforementioned curable insulating resin. For example,
liquid solder resist which cures upon irradiation of
lightl or curable insulating resin layer such as photo-
sensitive dry film is laminated on all over the surface
of the double-sided board, and after irradiating light
except where formation of an opening is needed, uncured
portion is removed by development to form an insulating
layer.
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In the aforementioned method, use of photo-
sensitive dry film which cures with light for forming an
insulating layer results in high precision of thickness
of the insulating resin layer and allows simultaneous
formation on both surfaces, thus enabling formation of
insulating layers efficiently and with high precision.
In the embodiment shown in Fig. 6, the
dimension of the opening 8 in the insulating layer 6 is
preferably within the aforementioned range which can
establish electrical connection with a plating layer.
Fig. 7 is a variation to the embodiment shown
in Fig. 6, i.e., an embodiment in which a dou~le-sided
board is used of which the plating layer 12 is omitted.
In this case, in order to ensure conduction to the via
hole portion A which needs electrical connection to the
first layer wiring pattern 2', the opening 8 provided in
the insulating layer 6 is formed so that the total area
of the end surface of the via hole portion A and the land
portion 11 of the wiring pattern therearound are exposed.
This configuration enables simultaneous plating of the
exposed portions by subsequent formation of the plating
layer 14, ensuring electrical connection of these
portions.
By the procedure shown in Fig. 7, it is
possible to omit one plating step from the procedure
shown in Fig. 6.
In the aforementioned method, while the method
of forming the plating layer 14 is not limited parti-
cularly, generally electroless plating of a metal is
preferred.
Also, in order to form the wiring pattern from
the plating layer, there can be used a similar method to
the formation of the aforementioned first layer wiring
pattern. Generally, etching methods are preferred.
In the present invention, similarly, an
insulating layer and a wiring pattern can be laminated in
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order on the second layer wiring pattern.
The aforementioned laminated wiring pattern can
be used in various applications without limitation, such
as signal conductor, power line, ground plane, electro-
magnetic interference shielding layer, etc.
While Fig. 6 shows the embodiment in which end
surfaces of the via hole portion ~ of the double-sided
board are coated with the plating layer 12 in advance,
such a plating layer is not indispensable.
In case the plating layer is absent, a plating
layer may be provided so as to be continuous with the
plating layer of the second layer wiring pattern when it
is formed, as shown in Fig. 7. That is, Fig. 7 shows the
embodiment in which the insulating layer is formed so
that the end surfaces of the via hole portion A which
needs to be connected to the first layer wiring pattern
and the layer portion 11 formed therearound can be
exposed, and the exposed portions can be simultaneously
plated.
In the aforementioned fabrication method,
specific method of fabricating the double-sided board in
not limited particularly, and may be decided property
depending on the structure of the multilayer board. To
exemplify such a fabrication method for the double-sided
board, there can cited, for example, the fabrication
method shown in Fig. 8 as a representative method for the
double-sided board used in the fabrication procedure
shown in Fig. 6, and the method shown in Fig. 9 as a
representative method for the double-sided board used in
the fabrication procedure shown in Fig. 7.
That is, Fig. 8 shows the embodiment in which
the hole 3 for the via hole portion is provided in the
base material 1 having on each side thereof a conductive
layer 15, curable conductive substance which gives rise
to the cured material 4 having conductivity is filled in
the hole and cured in such a manner that after curing the
2~9~7~
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cured material projects out of the hole, and the surfaces
of the conductive layer and the cured material are
scrubbed smooth so that the surfaces of the conductive
layer and the cured material are sub~tantially flush with
each other to form the via hole portion A between the
aforementioned conductive layers, and then the plating
layer 1~ is provided on the smoothed surface, followed by
etching predetermined places of the conductive layers
composed of the conductive layer and the plating layer to
form the first layer wiring patterns 2,2'. On the other
hand, Fig. 9 shows the embodiment in which the base
material 1 having on each surface thereof the conductive
layer 15 is provided with the hole 3 for the via hole
portion, a curable conductive substance which gives rise
to the cured material 4 having conductivity is filled in
the hole and cured in such a manner that after curing the
cured material projects out of the hole, and the surfaces
of the conductive layer and the cured material are
scrubbed smooth so that the surfaces of the conductive
layer and the cured material are substantially flush with
each other to form the via hole portion A between the
aforementioned conductive layers, and then predetermined
places of the conductive layer are etched to form the
first layer wiring patterns 2,2'.
Hereinafter, the aforementioned procedures will
be described in more detail.
The base material provided with a conductive
layer on each surface thereof is formed with the hole 3
for forming a via hole portion. The diameter of the hole
may be selected properly so as to correspond to the
diameter of the objective via hole portion. As the
method of forming the hole 3, there can be sued any known
means for fabricating ordinary boards such as drilling,
punching, laser processing, etc. without particular
limitation. In this case, in order to increase the
reliability of electrical connection between the cured
209~7~4
material of a curable conductive substance filled in the
hole 3 and the conductive layer, an inclined surface is
provided on the conductive layer positioned around a
peripheral portion of the hole so that the contact area
with the cured material can increase. There is no
limitation on the method of forming an inclined surface
on at least a portion of the hole surrounding the con-
ductive layer, and there can be used a method in which
after a base material having a conductive layer on each
surface thereof is formed with a hole for a via hole
portion, mild etching is performed with a mild etchant to
form the desired inclined surface, a method in which
after the hole is formed, the conductive layer and the
insulating layer are tapered by scrubbing using a drill
having a diameter slightly larger than that of the hole,
a method in which etching is performed with an etching
resist having a diameter slightly larger than that of the
hole formed around the hole, and so, on.
It is preferred that the conductive filling
material present in the via hole portion A of the
double-sided board is formed by filling the curable
conductive substance in the hole 3 in the base material
and curing it.
To fill the curable conductive substance in the
hole, it is recommended that the curable conductive
substance is filled so that it occupies all the space of
the hole and protrudes slightly out of the both surfaces
thereof, specifically by 0.05 mm or more, preferably 0.1
to 2 mm. As representative method for filling the
curable conductive substance, there can be used
advantageous various means such as a method in which one
or more coatings are performed by printing, a method in
which the substance is pressed in using a pair of
squeezees on both surfaces of the base material, a method
in which the substance is filled by a roll coater or a
curtain coater, and excessive coating composition is
20947~4
-- 19 --
removed using a squeezee, and so on.
Curing method for the curable conductive
substance filled in the hole may be selected properly
from known curing methods that are suitable for curing of
the curable conductive substance, such as curing oven,
infrared oven, far infrared oven, UV curing oven, electron
beam oven, etc.
It is important that after curing the curable
conductive substance, the surface of the conductive layer
and the surface of the cured material of the curable
conductive substance are scrubbed so that the both
surfaces are substantially flush with each other. That
is, such scrubbing enables pattern formation using an
etching resist and etching with high precision in the
subsequent wiring pattern formation, and also enables
formation of an insulating layer on the wiring pattern
with high reliability.
As the method of scrubbing the surfaces of the
conductive layer and the cured material of the curable
conductive substance smooth as described above, there can
be used generally conventional methods such as slurry
scrubbing, buff scrubbing, etc.
Fig. 8 shows the embodiment in which the
plating layer 16 is formed on the smoothed surface of the
conductive layer 15 containing the via hole portion A.
By forming such a plating layer and etching it to leave
the conductive layer so that the land portion 11 is
formed around the periphery of the via hole portion, the
via hole portion and the land portion of the wiring
pattern can be coated with a common plating layer.
Formation of the common plating layer increases the
reliability of electrical connection by the via hole
portion. Of course, the coating of the via hole portion
and the land portion of the wiring pattern by the plating
layer may be performed through an insulating layer at the
time of laminating the second layer wiring pattern.
- 20 _ 2~947~4
The method of forming the plating layer 16 may
be either by an electroless plating process or an
electroplating process. As the material of the plating
layer, while any conventional conductive metal may be
used without limitation, yenerally it is preferred to
select the same material as the conductive metal, such as
copper, used as the curable conductive substance which
gives conductive cured material. The thickness of the
plating layer is not limited particularly, and it may be
on the order of usually 50 ~m, preferably 5 to 35 ~m.
As described above, the first layer wiring
pattern is formed on the via hole portion, the conductive
layer or the smoothed surfaces of conductive layer and
the plating layer as shown in the steps shown in Fig. 8
and Fig. g.
That is, the first layer wiring pattern is
formed generally by forming an etching pattern using an
etching resist 17 and subsequently performing etching.
The etching resist used here is not limited particularly,
and photosensitive dry film, liquid resist, etc. may be
used that may be selected properly depending on the
fineness of the pattern. The etching pattern may be
selected properly from positive pattern and negative
pattern depending on the type of the etchlng process.
For example, positive patterns are used in the etching
process represented by tenting, and negative patterns are
used in a pattern plating method, and an SES method.
. As will be understood from the above, according
to the present invention, a double-sided board having a
smoothed surface, fabricated by forming a first layer
wiring pattern on both sides of a base material, and
filling a conductive material in a hole
penetrating through the base material to form a via hole
portion, is used in the formation of an insulating layer
and a second layer wiring pattern on the double-sided
board, and this enables formation of the laminated second
20~47~4
- 21 -
layer wiring pattern with a high precision. Formation of
an insulating layer on both sides of the double-sided
board, and subsequent formation of a plating layer
thereon are used in the formation of wiring pattern and
establishing electrical connection between the wiring
patterns, or between the wiring pattern and the via hole
portion. This enables formation of wiring patterns with
high degree of freedom without separately providing via
hole portions penetrating all the layers, which makes it
possible to increase circuit density.
Further, in the fabrication procedure, wiring
patterns can be laminated on both surfaces of the double-
sided board, which enables formation of insulating
layers, formation of plating layers, and processing of
wiring patterns from the plating layers to be performed
simultaneously, making the fabrication procedure more
efficient.
Furthermore, since wiring patterns are formed
on both surfaces of the double-sided board, electronic
components can be mounted on the both surfaces thereof.
- Hereinafter, the invention will be described
concretely by examples. However, the invention should
not be construed as being limited thereto.
A double-sided board was fabricated by the
procedure as shown in Fig. 8, and a multilayer board was
fabricated using the double-sided board by the procedure
as shown in Fig. 6.
More specifically, as shown in Fig. 8, (1) an
epoxy glass copper clad laminate of 1.6 mm thick was used
as the base material 1 having the conductive layer 15 on
each surface thereof, and (2) the hole 3 having a
diameter of 0.4 mm was provided in the laminate by
drilling. (3) In the hole 3 was filled commercially
available thermosetting silver paint (PS-652 (trade
name), produced by TOKURIKI KAKEN CO., LTD.) as the
2~947~4
- 22 -
conductive substance 4 by screen printing so that its
cured material slightly protruded out of the hole 3. The
silver paint was drled and cured in a curing oven under
the conditions of 80C for 4 hours, and 150C for 2 hours
to form the cured material 4 having a conductivity. (4)
Then, using No. 320 buff and No. 600 buff serially, the
protruding surfaces of the cured material, i.e., cured
silver paint to smooth the surface of the conductive
layer including the cured material. Next, (4') the
smoothed surface of the conductive layer including the
via hole portion A was subjected to copper electro-
plating. As the electroplating bath was used CUPRACID GS
(trade name, produced by NIHON SHERING K.K.), and
electroplating was carried out at a current density of 2
A/dm2 to form the copper plating layer 16 of 10 ~m thick.
Next, (5) on the smoothed surface of the con-
ductive layer, a photosensitive dry film (AQUAMER CF, 1.5
mil, produced by HERCULES) was laminated as the etching
resist 17, and exposed to light, and developed to form a
resist pattern. Therefore, (6) etching was carried out
with ferric chloride etchant, and (7) the etching resist
was stripped. Thus, the double-sided board 5 having the
first layer wiring patterns 2,2' with the land portions
11 on both surfaces thereof.
Next, as shown in Fig. 6, (1) using the double-
sided board 5, (2) in order to form an insulating layer
on the first layer wiring pattern including the via hole
portion A, a photosensitive insulating resist (PROBICOTE
5000: trade name, produced by NIPPON PAINT) was coated
and dried, exposed to light, and developed, followed by
thermal curing, to form a pattern provided with openings
8 in the insulating layer 6 at predetermined places where
electrical connection was needed. Next, (3) after the
surface of the insulating layer was roughened, both
surfaces were subjected to electroless copper plating and
- 23 - 2 ~9 ~7 ~4
electroplating to form the copper plating layer 14.
Then, (4) on the surface of the copper plating layer 14,
the etching resist 17 used in (5) above was laminated,
which was exposed and developed to form a resist pattern,
followed by etching using ferric chloride etching solu-
tion, and the etching resist was stripped to form the
wiring patterns 7,7'. Thus a multilayer board having 4
layers of wiring patterns was obtained.
Measurement was made of the resistance of the
wiring patterns 7,7' positioned on both surfaces of the
multilayer board thus obtained and electrically connected
through the common via hole portion, and the result
obtained was 31 mn. In thermal shock test according to
JIS C-5012 (-65C x 30 minutes <-> 125C x 30 minutes)
using a test pattern including the wiring pattern 7,7'
positioned on both surfaces of the multilayer board as
shown in Fig. 10 (i.e., measurement of resistance between
(1)-(1), (2)-(2), and (3)-(3) in Fig. 10), conductance of
the test pattern including the wiring patterns 7,7'
positioned on both surfaces of the multilayer board was
maintained at a cycle of exceeding 500 times, and
thereafter, almost no increase in the electric resistance
was observed.
Example 2
A double-sided board was fabricated by the
procedure as shown in Fig. 9, and a multilayer board was
fabricated using the double-sided board by the procedure
as shown in Fig. 7.
More specifically, as shown in Fig. 9, (1) an
epoxy glass copper clad laminate of 1.6 mm thic~ was used
as the base material 1 having the conductive layer 15 on
each surface thereof, and (2) the hole 3 having a
diameter of 0.4 mm was provided in the laminate by
drilling. (3) In the hole 3 was filled commercially
available thermosetting silver paint (PS-652 (trade
name), produced by TOKURIKI KAKEN CO., LTD.) as the
2~947~
- 24 -
conductive substance 4 by screen printing so that its
cured material slightly protruded out of the hole 3. The
silver paint was dried and cured in a curing oven under
the conditions of 80C for 4 hours, and 150C for 2 hours
to form the cured material 4 having a conductivity. t4)
Then, using No. 320 buff and No. 600 buff serially, the
protruding surfaces of the cured material, i.e., cured
silver paint to smooth the surface of the conductive
layer including the cured material.
10Next, ~5) on the smoothed surface of the
conductive layer~ a photosensitive dry film (AQUAMER CF,
1.5 mil, produced by HERCULES) was laminated as the
etching resist 17, and exposed to light, and developed to
- form a resist pattern. Thereafter, (6) etching was carried
out with ferric chloride etchant, and (7) the etching
resist was stripped. Thus, the double-sided board 5
having the first layer wiring patterns 2,2' with the land
portions 11 on both surfaces thereof.
Next, as shown in Fig. 7, (1) using the double-
sided board 5, (2) in order to form an insulating layeron the first layer wiring pattern including the via hole
portion A, a photosensitive insulating resist (PROBICOTE
5000: trade name, produced by NIPPON PAINT) was coated
dried, exposed to light, and developed, followed by
- 25 thermal curing, to form a pattern provided with openings
8 in the insulating 6 at predetermined places where
electrical connection was needed. In this example, the
insulating layer 6 was formed so that the via hole
portion A and the land portion 11 therearound are exposed
at a place where the via hole portion and the first layer
wiring pattern 2' contact with each other (cf. the lower
part of the via hole A in Fig. 7).
Next, (3) after the surface of the insulating
layer was roughened, the both surfaces of the board were
subjected to electroless copper plating and electroplat-
ing to form the copper plating layer 14 of 10 ~m thick.
- 25 _ 2~9~7-54
Then, (4) on the surface of the copper plating layer 14,
the etching resist 17 used in (5) above was laminated,
which was exposed and developed to form a resist pattern,
followed by etching using a ferric chloride etching
solution, and the etching resist was .stripped to form the
wiring patterns 7,7'. Thus a multilayer board having 4
layers of wiring patterns was obtained.
Measurement was made of the resistance of the
wiring patterns 7,7' positioned on both surfaces of the
multilayer board thus obtained and electrically connected
through the common via hole portion, and the result
obtained was 33 mQ. In thermal shock test according to
JIS C-5012 (-65C x 30 minutes <-> 125C x 30 minutes)
using a test pattern including the wiring pattern 7,7'
positioned on both surfaces of the multilayer board as
shown in Fig. 10, conductance of the test pattern
including the wiring patterns 7,7' positioned on both
surfaces of the multilayer board was maintained at a
cycle of exceeding 500 times, and thereafter, almost no
increase in the electric resistance was observed.
Example 3
A curable conductive substance composed to
copper paint was prepared by the following method. That
is, linolic acid was blended with dendrite copper powder
having an average particle diameter of 6.8 ~m, a tap
density of 2.99 g/cm3, and a specific surface area of
4,200 cm2/g in a proportion of 0.25 x 105 mmol/cm2 of
copper powder surface, and the mixture was preliminarily
mixed in a mortar for 15 minutes in a nitrogen
atmosphere. The copper powder thus pretreated (456 parts
by weight) was added to 100 parts by weight of a binder
composed of neopentyl glycol glycidyl ether (epoxy
equivalent = 150)/novolak type phenol resin (hydroxyl
equivalent = 105) = 74/26 (weight ratio), and further 2.8
parts by weight of 2-ethyl-4-methylimidazole per 100
parts by weight of binder was added thereto. Therefore,
2~9~7~4
- 26 -
the mixture was kneaded for 30 minutes using a three-roll
mill to form a paint.
In the method of Example 1, fabrication of a
multilayer board was performed in the same manner as
described above except that the aforementioned copper
paint was used in place of the silver paint.
Measurement was made of the resistance of the
wiring patterns 7,7' positioned on both surfaces of the
multilayer board thus obtained and electrically connected
through the common via hole portion, and the result
obtained was 39 mQ. In thermal shock test according to
JIS C-5012 (-65C x 30 minutes <-> 125C x 30 minutes)
using a test pattern including the wiring pattern 7,7'
positioned on both surfaces of the multilayer board as
shown in Fig. 10, conductance of the test pattern
including the wiring patterns 7,7' positioned on both
surfaces of the multilayer board was maintained at a
cycle of exceeding 500 times, and thereafter, almost no
increase in the electric resistance was observed.
Example 4
A multilayer board was fabricated in the same
manner as described in Example 1 above except that the
copper plating layer 16 as shown in Fig. 8 (4') was not
provided on the smoothed surface of the conductive layer
containing the via hole portion.
Measurement was made of the resistance of the
wiring patterns 7,7' positioned on the both surfaces of
the multilayer board thus obtained and electrically
connected through the common via hole portion, and the
result obtained was 37 m . In thermal shock test
according to JIS C-5012 (-65C x 30 minutes <->
125C x 30 minutes) using a test pattern including the
wiring pattern 7,7' positioned on both surfaces of the
multilayer board as shown in Fig. 10, conductance of the
test pattern including the wiring patterns 7,7'
positioned on the both surfaces of the multilayer board
209~7~4
- 27 -
was maintained until a cycle of 300 times, and there-
after, commencement of a slight increase in the electric
resistance was observed.
.
