Note: Descriptions are shown in the official language in which they were submitted.
w093/06652 PCT/US92/0621X
2 Q ~
MI~ ATIO~ O~ ~TO ~ DXIV2R ~08~8
WX~N AN~IPARaLL~ DIOD~ CONDU~T
~ACXGROUND OF THE INV~:NTIO~ i
This invention relates to inverter ~y~tems and,
more particularly, to inverter systems using gate
turn-off (GTO) deYices ~or controlling power to a
reactive load and to a method and apparatus for
reducing power consumption in such GTO devices and
assoclated gate driver circuits when r¢active current
prevent3 current trans~er ~nto the GTO deviaa.
Power conversion systems ~or converting direct
current (DC) power to alternating current ~AC) power,
commonly re~erred to as inverters, are well known in
the art. In a typical form, these inverters comprise
pair o~ switching device~, such as GTO devices,
serially connected between relatively positive and
15 relatively negative power busses. A junction
intermediate the GTO devices is connected to a load,
such a~ an AC motor. For a multi-ter~inal load, such
as a three-phase electric motor, thrae such inverters
are utilized, each coupled to a respactive one o~ the
motor phases. In each inverter phase, only one GTO
device conducts current at any time, one o~ the
devlces being connected to conduct current in a first
direction t~rough the }oad and the other of the
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W O 93/0665~ PCT/US92tO6218
devices being connected to conduct current in a second
direction through the load.
Since current or voltage to the load is regu~ated
by controlling the conduction cycles o~ the GTO
devices in each inverter phase, there are times when
neither of the device~ in a phase are conducting and
yet a current path must b~ prsvLded for reactive
current. For this reason, dlodes are connected in
parallel with each o the GTO devicles w~th the diodes
lo being poled oppos$tely o~ the associated GTO device~
for conducting current in a reverse direction. In an
exemplary inductively reactive load such as a ~otor,
current through a phase winding is shunted from a GT0
device into a dlode when the GTO device is forced out
o~ conduction.
During a time period when a substantial current
exists ln a diode, gatlng of th~ associated GTO device
is ine~fective to rever~e the direction o~ current in
the connected reactive load. Mors speci~ically, when
current is ~lowing through the diode, the parallel
connected GT0 i~ reversQ biased. If gate curren~ is
applied to the GT0 device d~ring this ti~e period, the
only effect i8 to draw a relatively large current from
the GTO gat2 driver circuit. Since the gate current
when the GTO de~ice is being gated i~ much higher than
when it is not being gated and the power dissipation
even without anode current iq relatively large, it i5 ~ i~
desirable to avo$d gatin~ of th~ GTO device when the
device is rever~e biased, i.e., when the parallel
connected diode is carrylng current. When the GTO
device i~ connected in an inverter for supplying power
to an induction motor, current lags thQ voltage
resulti~g in a significant portion of time in which
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W093/~665' PCT/~IS92/0621X ~:
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current is carried by a diode in parallel with a GTO
device. Thus, there is a siqnificant portion of time
in which it is not desirable to apply gating current
to a GTO device in order to avoid unnecessary power
consumptlon and to minimize unnecessary heat
dissipation.
~12~Yu~L~ IS~l~y~3IoN
The above and other desirable advantages are
attained in a power control system for an AC electric,
multi-phas~ ~otor including an inverter circuit
coupled to the motor ~or supplying regulated AC power
to control the power output and/or speed of the motor.
In one for~, ~he sy~te~ includes an inverter having a
plurality o~ ~tag~ each coupled to a respective one
of the phase wlnding8 o~ the motor. Each Lnverter
stage includQ~ a p~ir o~ serie3 connected
semiconductor swltching devices serially coupled
between r~latively positiv~ and relatively negative DC
power bus~c~. A unid$rect~onal devic~, such as a
Z0 diods, i~ couplsd in anti-parallel circuit arrangement
with each switching de~ice. ~eans are providsd for
determining current ~low in each phase winding o~ the
- motor. A micrwomputsr control ~uppli~8 gatlng
signals through a gats driver circuit to each o~ the
switching d~vices to e~fect their ccnduction at
preselected tim~s in ord~r to regulatQ operation of
the motor. Tha control include~ means re~ponsive to
the current in the motor windings ~or inhibiting
gating o~ the ~witching devlce~ when current in an
associated anti-parallel diode exceeds a threshold
value that prevent~ th~ ~witching device to effect a
- current re~erYal $n the re~pective motor pha~e
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W093/0~652 ~ 3 PCT/US92/06218
winding. The swltching devices are preferably GTo
thyristors and current in at least one phase of the
motor is computad from monitored current in the other
phases.
BRIEF ~ESCRIPTIO~ OF T~E DR~ING~
For a better understanding of the present
invention, re~erence may be had to the following
detalled description taken in con~unction with the
accompanying drawings in which:
FIG. 1 i~ a partial schematic, partial block
diagram of a power conversion circuit implementing the
present invention: and
FIG. 2 i5 a functional blocX diagra~ of the
method o~ the pre~ent invention.
DETAILE~ ~SCRI~rION QF~ xE~IQ~
FIG. 1 is a ~impli~ied partial schematic, partial
block diagra~ of a power conversion syste~
incorporating the teaching5 o~ the present invention.
The power conversion syste~ i8 illustrated as a three
phase inverter compri~lng inverter ~ection~ lOA, lOB,
and lOC connected for controlling power to a three
phase induction motor ~. ThQ inverter sections are
coupled between relatively positive and relatively
negative voltage rails 12 and 14, respectively. The
rails 12 and 14 are connected to a power source 16
which may comprisQ a battery or other power generating
means. A ~ilter comprising serles inductor 18 and
shunt capacitor 20 isolates the battery 16 from the
tran ients genarated by the inverter circuit.
Each of the inverter sections lOA, lOB, and lOC
are substantially identical. Each section includes a --~
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WO 93/066;' PCI/US92/0621X
2~9~ 3
pair of controllable swltching devices 22 and 24
coupled in series between ralls 12 and 14. Each Or
the switching devices 22, 24 has coupled in parallel
with it a snubber circuit 26, ~8, respectively, to
limit the rate of change o~ curre!nt when turning on
and to limit the rats of change of voltage wher
turning off. Variou3 types o~ snubber circults are
well 3cnown in t~e art and no additional de~;cr~ption is
deem~d neces~ary. Discu5sions of snu~ber circuits are
set forth in a p~p¢r by A. Ferraro, "An Overv:Lew of
Low Loss Snubber Technology for Transistor
Converters~', publi~;hed in the Con:Eerence Record IE~:E
Power ElectronicS Specialists Conference, 1982, pp.
4 66-477,
The controll~lble 8witching devicas 22, 24 may be
thyristors, tr?nsl8tors, or o~her sa~iconductor
dsvices but in a pr~errQd ~or~ compri3e gat~ turn-off
(GT0) davic~ or GTO ~hyristor8. A GTO thyri~tor i8
a multi-lay~r aQ~iconductor deBigned to freely conduct
"~orward" anode current, $.e., current ~lowing into
its anodQ and out of it8 cathode, whQn its gats
electrod2 is trigg~rad by a ~uitabl~ turn on or ~iring
signal. A GTO ~hyri~tor ~ d~stingui~h~d fro~ a
conventional thyri~tor by it~ nbllity to interrupt or
block forw~rd ~nod~ curr~nt if a vo}tag~ o~ relatlvely
negatlYs polarity and appropriate ~agn~tude and
duration i~ applied acros~ its gate-cnthode junction.
Such VoltagQ i5 nQgatiVQ in the s~n~e that the
electrical potential o~ the gate i5 negative with
re~pect to the cathoda. It cau~Qs current to ~low in
a reverse direction in the thyri3tor'~ gat~. In other
words, to turn o~ a GTO thyristor, cur~ent i~ drained
from the gate. ~ereina~ter, Euch current iB referred
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wos3to66~ pcT/~lss2/o62l~
2Q~'~2-l3
to a~ ether "negative gate current~ or the "turn-o~
sigrlal ~ . '',
In ~ormal operation, the anode c~rrent-blocking
or turn-off process of a GTO thyristor can be
initiated at any time without waiting for a natural or
externally forced zero cros~lng of th~ anode current. -~
During thQ turn-o~f procaaB~ the ~egatlvs gate curre~t
rapidly ri8e~ to a high pea~ that depend~ on the
magnitudQ of anode current to be $nterrupted and then
subsides a~ the thyr~stor recover~ its ability to
withstand off-state anode vo}tage. Once a turn-off
process is successfully completed, the resistance of
the gate-~athode ~unction i~ very high and limits
negative gat~ current to a trivial magnltude.
15In the prssent inventlon, the GTO device~ 22, 24
are alternately conductivs 80 ag to provlde bi-
directional current to each phase of the induction
motor M. Consldering in~ert~r section 10A having
corresponding GTO devices 22A and ~4A, when device 22A ~;
i9 conductive, current ~1 is directed into ~otor M in
the direction o~ ~rrow 30. A~ter a predet~rmined time
period, GTO devlcs 22A is gated out o~ conduction.
Since ~he ~otQr M i~ an inductiv~ reacti~e load,
current Il cannot ~mmediately cea e without creating an
25 inf init~ voltage ris~. Accordingly, current I
tran~ers ~rom the GTO devic~ 22A tD unidirectional
conducting d~vice 32A. Tha de~ice 32A, preferably a
powQr diode, i~ connected in a parallal circuit path
w~th GTO d~vic~ 24A but poled rQversQly with respect
to devica 24A. A companion unidirectional device 34A
is connected in parallel with GTO d~vice 22A in the
same manner a3 devicQ 32A. Current I1 transfers to
device 32A since the ~olIap~ing current in th~ phase
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W093/066~2 ~ ,3~ 3 PCT/US92/06218
winding o~ motor M causes a voltage reversal across
the windins ~hereb-i ,Grward biasing diode device 32A.
At anotAer predetermined time period, GTO device 24A
is gated into conduction to thereby reverse the
direction of current I1 ln the corre-~ponding phase
windlng of motor ~ a~ lndicated by arrow 36. When GTO
device 24A i~ thereafter gated out o~ conduction,
current I1 trans~er~ to diode device 32~. This sama
proces~ occurs for each winding of th~ motor ~ with
the respecti~e GTO device~ 22, 24 being gated into and
out of conduction in a manner to regulate power
developed by motor M. One form of three phase
inverter using GTO device~ for contro~ling power to a
motor is de~crib~d in a paper by gansaki et al.,
"Inverter Control System Por Driving Induction Motors
in Rapid Transit Car~ Using High Power Gate ~rn-of~
Thyri~torsn, published in the Con~erQnce Record o~ the
ISPCC, 1982, pp. 145-156.
SlncQ GTO device~ can be gated i~to and out o~
ZO conductio~, they require gate drive current o~ two
polar~ties. The initial power required at the instant
when polarity bia~ power required to hold the d~vice
on or off. FurthQr, the bias current to hold the
device in conduction may be ~ro~ three to 8iX amp8 ~or
a typical induction motor load wherea~ the gate
leakage current when the d~vicQ i8 o~f may be only a
few microamps. Consequently, the power di~sipated in
the GTO device when initially gated between on and of~
state~ and when in the on state i8 slgnificantly
higher than when the GTO devic~ is in an o~ state.
The gate driver circuit 38, which is connected to
provide the bipola~ gate drive current to ea~h o~ the
GTO device~ 22, 24, experience ~imilar high power
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WO 93/066~2 ~ 2 ~ 3 PCI/IIS92/0621
dissipation each time that the circuit 38 switches
polarity at onQ o~ lts output~ or when it is cupplying
"on" gate drive current. A gate drive circuit
suitable for us~ as yate drive ci:rcuit 38 may take
variolls forms and one exemplary for~ is shown in U.S.
Patent No. 4,593,204 issued ~unQ 3, 1986 to ~c~urray,
a~signed to th~ assignee of the present invention.
The present lnvention i~ intendl~d to minimize the
power dissipation in the gate driver circuit 38 and in
the GTO de~ices 22, 24 by inhibiting generation of
gate drive current to respective ones of the GT0
devices 22, 24 when a corresponding parallel connected
diode dev~c~ 32, 34 is conducting c~rrent above a
predetermin~d 1~VQ1. In ordar to ach$eve this
desirable reRult, the dr~v~ current to at least two of
the three phases of motor M i8 ~on~tored by current
sensors 40 and 42. Although the third phase could
al~o be monitored, the ~um o~ Il, I2, and I3 must equal
zero allowing current in the thlrd phass to be
determlned ~rom current in the other phase In the
illustrativfi exampl~, current I1 and 13 are ~onitored
by sensor~ 40 and 42, respectively, and current I2 is
calculatad with~n control procassor 4~.
Proc~sor 44 ~ay t~kQ the ~orm o~ a microco~puter
programmed to control gatlng o~ GTO de~lces 22, 24 in
a manner to regulate power output o~ motor M or to
maintain a prsselected speed profilQ o~ motor ~. The
proce~qor 44 may include v~riou~ logic circuits and
include analog-to~digital (A/D) converter 46 for
tran~lating the ~nalog current signals ~rom sensors
40, 42 to corresponding dlgital value~. Control
processors ~uitable for use a~ procesRor 44 are well
known in th- art. Th~ inhibit function described
w093/066~ PCT/~IS92/06~
2 0 ~ 3
herein may b~ implemented by logically combining the
current signals from sensors 40, 42 with the gating
commands to the GTO devices 22, 24. For example, .~f
current Il i5 in the direction of arrow 30 and
processor 44 initiates a si~nal to attempt to cause
gate driYQr circuit 38 to g~n~rat~ an "on~ command to
G~O dQ~ice -24, the si~nal ~rom ~ensor 40 can be
logically ANDED w~th th~ ~gn~l ~ro~ proce~sor 44 to
inhiblt the a~tuation of gat~ driver circuit 38 until
current I1 i~ les than a pre~Qlected threshold ~alue.
For a clearer understanding of ~e operatlon of
the inventive system, re~erence is made to the
functional flo~c~art of FIG. 2. At block 48, the
current ~ign~ , i.e., Il, I2, or I" is tested to
determine lr lt exceeds th~ thrashold ~alu~ IT. I~ may
be zero or som~ predat8rmined non-zQro value at whlcb
gating o~ a corr8sponding GTO devic~ will be e~fective
to reverse current ~low in a respective on~ o~ the
motor pha~9. I~ the Ix ~$gnal is representatlve o~
pha~e current lesB than ths t~re~hold value, no
inhibitlng o~ gating Or khQ GTO device5 ls necessary
and the progr~m ~unctlon loop~ ~a~k to ~he ~tart
location. I~ the valuQ o~ I~ Qxc~e~ IT~ ~h~ direction
of current i~ d~t~r~ln~d, i.~., iB Ix greatQr than or
les~ than z~ro, bloc~ S0. If Ix i~ greatQr than zero,
th~n either GTO 22 i~ conducting or diod~ 34 i~
conducting. convQrsely~ x i~ less than z~ro, then
either G~O 22 is conducting or diode 32 iB conducting.
Block 52 determ~n~, from the gating signals issued to
gate dri~er circuit 38, if G~O devicQ 22 is
conducting. If dovice 22 i~ conducting, inhibiting is
unneces~ary ~nd the program loops to start. If device
22 i~ not conducting, thQ progra~ checks for gating
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wos3/066~2 PCT/~S92/OG21X
commands to GTO 24, block 54, and inhibits such
commands, block 56. Thu~, gatins OL GTG device 24 is
inhibited if current in parallel connected diode 32 i~
above a preselected threshold value I~ s~nce such
gating i9 lneffectiva with the device 24 reversed
biased except to increase power dissipation in device ;~
24 and gate driver circuit 38.
In a similar manner, the sy~tem verifies the :
operation o~ GTO devicQ 24, block 58, testing for . : .
10 gating signals to GTO devic~ 22, block 60, and :
inhibiting such gating slgnals, block 62, if the
system attempts to gate GTO device 22 while current i.
through diode 34 has device 22 reverse biased. ~
The functlonal block diagram o~ FIG. 2 is .-
15 descriptive o~ syste~ operation whether the ~: :
implementation is in a microcomputer or a hardwired
logic circuit. The arrangement assures that an "on"
gate drive current i~ only supplied when nesded and
not when the assoclated GTO dsvicQ i~ reverse biased
by a ~orward biasQd anti-parallel dlodo. Further,
additional losse~ occurring due to redundant switching
are avoided, including ~h~ aforementioned losse~
associated with switching the GTO device to an "o
state even if the deviGe does not experience an anode- ~:.
cathode ourrent.
While the principles of the present invention
have now been made clear in an lllustrative
embodiment, it will become apparent to tho8a skilled
in the art that ~any modifications of thQ structures,
arrangements, and components pra~entQd in the above
illu8tra~0ns may be made in the practlce of the
invention in order to develop alternate embodiments
suitabl~ to speci~ic operating r2quirement~ WithQUt
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W093/066~ 2 ~ 2 ~ 3 PCT/US92/0621~
departing from the spirit and scope of the invention
a~ set forth in the claims which follow.
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