Note: Descriptions are shown in the official language in which they were submitted.
WO 93/07S6~ PCI/US92/06455
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M~3MORY WRlTE PROTECqlON ~:THOD A~
APPARATUS
Field of t~e In~rention
1 0 T'ni8 in~ention generally relates to the i~astructure of
systems, and more specifically, to access~g a memory device
contained ~nt~in the microproce3sing cystem.
Bacl~ground of the Invention
1 5
l~pically, a microprocessing system contains a memory, a
data bus, a n~icroprocessor and penpheral dev~ces. The
memory contau~s a data bus input, an a~dress bus input, a
chip ~elect input and a wnte enable input. Genera~ly, t~ere
are t~ree systems for ~mtulg data to an estern~ memory in a
microprocessor en~ironment.
In the f~t ~t~ a ca~trolling device is used to create
the address on the address bus. The chip select and the wnte
ei~able li~e~ are direc~ly coupled between the controlling device
2 5 ~d the memory de~ice. During a power-up or a data tran~fer,
the wnte enabb dg~al may be ac~vated for too long or f~lsely
trigpred. T~ ma~r allo~ estraneous data to be wntten into
the memo~r dence; corrupt~g the data contained in the
memo~y, whic~ may ~enou~ly effect the operation of tl-e
microproce~sor s~t~ Additioually, the ccntro~ling device
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may esecute the ~vrong code dursng a write cycle, causing
unpredictable results within the memory device.
In the second system, an attempt is made to protect the
memory from corrapt data. The controlling device triggers a
logic device and the logic device creates the wnte enable signal
for the memory device for a predetermined amount of time.
This predetennined amount of time i~ typically fised for the
amount of time required to wnte the largest block of data to the
memory device, ~uch that it does not limit the amount of data
1 û that is written to the memory location of t}~e memory dence.
This sy~tem lea~res a wiDdow of opportunity for corrupt data to
be written into the data dence when blocks of data, smaller
than the largest block of data, are written to the memory device
or a write enable signal is falsely triggered. ~gain, the
1~ controllin;g de ice may esecute the wrong code du2~ng a write
c~rcle and cause unpredictable results within the memory
de~ice.
T'ne third l~ystem ha~ a protection d vice built into the
2 0 memory. The memo~r require~ the controller to write a byte of
data to three specific addresse~ prior to wri~g the desired
data to the memor~ de~ice. Tnis implementation is discu~ed
in the data ~eets X28C64, from the ~lCOR Da~a Book, Second
Edition, lg90. After the t~ree bvte sequence is written to the
2 ~ proper addres~es, the page write window i8 open, allowing the
controller to write ~om 1 to 64 b~te~ of dats to the memory
d~rice. T~is protection device protects the memorv f~om false
trig~er~g, but allows corruption of the memory device dunng
the ~Yariable pap write window. Agai~ the controlliDg
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device may e~ecute the w~ong code dunng a wnte cycle and
cau~e unpredictable result~ within the memory device.
Therefore, a need e~ists for an adaptive data protection
device which varies tl~e duration of the ~rrite enable sign~l
depending upon the ~ize of the data blocl~ to be writSen So the
memory dence or the ac~ r momSored wit~ e cont~olling
device, and eliminates false triggering of t}le wnte enable
sig~al.
1 0
Summary of the Invention
The present invention encompasse~ a write protection
~ paratus for protecting a memory device fhm receiving
1 5 c3rrupted data while wnting a block of data from a data
suppljing device to the memo~r device. The memory de~ice
has a write enable input and a data input. The write
protection apparatus couples 1;he data ~upplying device to the
data input of the memory device. The memor~ protection
2 0 de~ce generates a first signal wbich ~igE~ers geners~on of a
second ~g~ e second sig~al is active for a first
predet~ined 1ime and i8 coupled to the input of the memorg
device, thereby allowing the data device to wnte data to the
memory device duling this f~rst predeten~ed time. A third
2 5 8ignal may be g~erated di~abling said second signal.
.
3 ~ Brief l)escription of the Drawing~
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FIG. 1 is a block diagram of radiotelephone
communication system which may employ the present
invention.
FIG. 2 is a circuit diagram of the present invention.
P IG. 3 is a timing diagram of the present invention.
FIG. 4 i8 a process flow c}lart of the method of the present
invention.
1 0 ~etailed l)escription of the Preferred Embodiment
The pre~ent invention encompasses a microprocessor
system incorporated into a digital radiotelephone, such as the
Japan Digital Cellular Telephone. In the preferred
15 embodiment, an electronically erasable PROM (EEPROM) is
used as the memory de~ice in the radiotelephone to ~tore
permanent infonnation nece~sary for operating the
radiotelephone, although the invention mav be u~ed to protect
ang type of non-valatile memorg device. Various dzes of data
2 0 blocks are written to the ~ ROM from different de~ces. In
tne past, when adiotelephones were returned for
mamtenance problems, the EEPROM contsined co~upted
data w~ich disabled or impaired the operation of the
radiotelephone. By implementing the present invention, the
25 corrupt data ~mtten to the EEPROM i~ minin~zed.
Essentially, the invention encompasses a method and
apparatus of writD~g data blocl~s to the EEPROM ~nthout
cormpt~g the data stored wit~in the memor~r device.
FIG. 1 is a blo~k diagrsm of a radiotelephone
3 0 commu~icatio~s ~ystem. Within this system there i~ a f~ced-
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site transcei~er 103 which sends and receives radio frequency
(RF) ~ignals to and from mobile and portable radiotelephones
located in the geographic area 6er~iced by the f~ed site
transceiver 103. Radiotelephone 101 is one such
radiotelephone served by the f~sed site transceiver 103.
Upon reception of radio frequen~y signal~, radiotelephone
antennas 105, 107 con~ ert the radio f~quency signals into
electrical radio frequency signals where then they are
tra~mitted to the receiver~ 111,113 respec~vely. The
1 0 receiver~ 111, 113 convert the electrical radio frequency signals
into usable data for use bg other parts of the radiotelephone
101. Upon tran~nisfiion of radio frequency signals, the
microprocessor 121 inputs the data into the transmitter 109.
T,he transmitter takes the data and converts it into ~e
electrical radio frequency signals and transmib it through
antenna 106 which con~erts its radio frequenc~ sig~ and
trangmits lhose back to the fi~ed-site transcei~er 103. In or~er
for the radiotelephone 101 to operate properly, many
parameters need to be stored in a ~rm~-nent memory la7. ,
2 0 Thi~ permanent memory is EEPR0~ 127. T~e EEPROM 127 is
accessed na t~e microprooessor 121.
During the or,iginal program~ng of the radiotelephone in
the factory the ~ ROM 127 is progrsmmed wit~ essential
operating parameter~ in~luding: recei~ved ~ignal ~trength
2 5 infosmation (RSSI), identification information and power level
information.
Tbe RSSI i~fonnation is nece~sary to calibrate the current
recei~ed Bignal ~trengths. The calibrated received signal
streDgths are used to ~elect the appropriate fised site
3 0 transceiver 103. T'ne current recei~ed ~ignal strength
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recovered from the receivers 111,113 is uset to reference the
RSSI value stored in the EEPROM 127. If the RSSI values are
cosrupted, then the wrong f~sed site transceiver may be
selected, resulting in redu~ed performance quality of the
5 radiotelephone 101.
The iden'dfication infosmation includes a unique serial
number and phone number. I~nis info~ation is stored in the
EEPROM 127 dunng the orig~nal programm~g procedure.
This information must be protected to insure the
10 communication system's integrity. If the serial number is
c}~s~ged or corruptet, then the phone may be identifiet as
someone else's or phone calls may be made and the charges
applied to another's phone bill.
The power le~el table is loaded into the EEPROM 127 in the
1 6 factory. The output po ver levels are measured for a given
input, the output power fluctuate from radio to radio
depending upon component and hybrid ~ariations. The
transmit output power is tuned such that it meets the FCC
specification or equi~alent Japanese specifications at five
2 0 predetermined levels. I~ne information necessar~ to escite the
power amplifier to the desired output level is stored in the
EEP~O~ 127 and is retrieved whenever the power amplifier
needs to be tuned to a predetermined power output. If this
infonnation is corrupted the power amp~ifier contained in the
2 5 trans~tter 109 will not operate within the specifications and
ma~r cause serious performance problems for the
radiotelephone 101. After the information is loaded into the
EEPROM 127, the radiotelephone 101 is ready to operate.
W~ile the radiotelephone 101 i8 in use, some user feature
3 0 data and vanous parameters are stored in the EEPROM 127 to
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assist in maintenance procetures when the phone is returned
to a dealer for sernce. E irst, a timer i~ used to store the
amount of elapsed time the radio is in use from the beginning
of ~me. In order for the radiotelephone 101 to msintain this
counter the radiotelephone 101 stores the counter in the
EEPROM 127. When power i9 turned off or loct, the tamer does
not reset. &econd, the radiotelephone 101 contains an error
monitor which utilizes a set of error codes to describe problems
within the radiotelephone 101 dunng operation. If 6uch sn
1 0 error occurs while operating the radiotelephone 101, the error
co~e ant the time of ocrence is stored in the EEPROM 127 to
assist in maintenance of the radiotelephone 101 at a later point
in time. Additionally, the EEPROM 127 is used to store phone
numbers and preferences such as ringer volume. The
1 5 preceding operations are controlled by the microproces~or 121
v~ile operating the radiotelephone 101.
~IG. 2 is a block diagram e~nploying the in~rention. The
write cycle of data from ~e microprocessor 121 begins by
~ending a known bit pattern to a predeten~ined address. The
2 0 ptedete~ned addres~ corresponds to the data lrerifier 207.
The data verifier 207 recei~es the lcnown byte of data from the
microprocessor 121 and che~ks it against its l~nown byte of
data. Upon ~erification, the microprocessor 121 then change6
the address to the E~i~ROM 127 and begins to load the desired
2 5 data onto the data bus 217. Simultaneously, data verifier 207
generates a write_en~ble_trigger ~ignal 211 which i~ input
i~to the one-~ot 203. The one-shot 203 genérates a write_ok
dg~ 213 for a predete~ned ~ne. T~e predetermined time
i~ e~usl to ~he time required to write the largest data block
3 0 firom the microproce~sor 121 to ~he EEPROM 127. In the
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preferred embotimentt the one-shot time is ~et to 50 uS. The
write_ok signal 213 ant the reat/write signal 219 are input
into the AND gate 205. Tnis ensures that in case of a false
trigger from the one-shot the EEPROM's write_enable_signal
215 is not falsely enabled, protec~ng t~e EEPROM 127 from
corrupted data. T~e AND gate 205 and tile data verifier 207 in
tlle preferred anbodim~t are implemented in a
programmable logic arTay (PLA) model number PAL16V8,
a~ailable from AdYanced Micro DeYice~. Upon wccessfill
1 0 ANDing of t~e three signals 211, 213, and 219 the A21D gate 20B
outputs a wnte_enable_signal 21~ to the write enable input of
the ~EPROM 127. I~is allows the data on the tata bus 217 to be
itten into the ~;~;rROM 127 at addresses dete-~inet by the . .
microprocessor 121.
- 1 5 The one-shot re~et signal 209 may be used to shorten the
dura~on of the one ~hot ~rite enable dgnal, thus crea~g a
~anable duration wnte enable ~ignal. There are se~eral
reason~ thi~ ~ariable write enable signal duration i8 desirable.
First, if the data block wbich i~ to h writbn to the EEP~OM
2 0 127 i8 of ~horbr duration than t}le largest block of da~a, then,
the one shot reset dgnal 209 may be tIiegered by
microproce~sor 121, subsequently, di~abling t~e write_ok
signal 213 to the ~ rRoM 127 at the end of the shorter data
bloclc l~a~ been written The duration of the wnte enable signal
2 5 i8 equal to the le~ of the data bloclc to be written to the
EE~ROM 127, ~us, substantially eli~nating the po~bility of
~mtiDg corrupt data to the EEPROM 127. Alte~ati~ely, the
resot d~l 209 may be u~d to di~continue a wnte cycle to the
EEPROM 127 upon detmi~i~g a problem within the radio.
I~ the prefemd embodiment, the reset ~ignal 209 i8 used to
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discontinue a write cycle when the radiotelephone detects a
read request signal or a chip ~elect ~ignal to a devioe other
tha~ the EEPROM 127. Problems are particular to the ~ystem
within which the invention i8 employed and equally sufficient
5 I:ntena for disabling the write cycle may be employed by one of
average 81~ill in the art.
Note t~at a one-shot 203 is particular to this embodiment.
Other embodiments may employ equally sufficient timing
devices, includi~ digif,al timers, shift registers and
1 0 resistor/capacitor (RC) circuit3, in place of the one-shot.
I~ewise, an~ memory device may be substituted in for the
EEPROM 127 by one of average skill in the art.
FIG. 3 reveals tbe timi~g of all the eE~ential signals
included in the block diagrarn of F~G. 2. The microproce~sor
1 5 121 sets the data bus 305 to a known bit pattern, and the
address bus 307 to the data ~erifier 207. After the data verifier
207 receives the known bit pattern, the microprocessor 121 sets
the addre~s bus 3C7 to a memory location witbin the hl3PROM
127 and beg~ tra~ferr~g desired data onto t~ data bus 307.
Upon verification ofthe known bitpatte~ he data verifier 207
creates the write_enable_trig~er signal (211) 313. This signal
is input into the one shot 203. The one-shot 203 subsequently
creates a write_ok_signal 311(213) which endures for 50
microseconds (uS) and is input into the logic AND device 205.
2 ~ l~e logic AND device 205 u~es inpub of the microprocessor's
RD/WR dgnal 309 (219), the ~vrite_enable_tngger dgnal (211)
313, and the ~rite_ok_dgnal 311 to create the EEPROM's
~vnte_e~able_6ig~ 315. The duration of the
~nte_e~able_dg~al 31~ may be ~ortened by the
3 0 microprocesor 121 ensbling the reset signal 317 (209). The
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re~et signal 317 (209) will reset the one-shot 203, subsequently
inactivating the wnte_enable_~ignal 315 (215).
~IG. 4 is a proce~s flow chart of the method employed by
this embodiment to reduce the opportunity of ~mting colTupt
data to the EEPROM 127. The flow chart starts at 401. At 4Q3,
the microproce~sor 121 generates a known bit pattern onto the
data bus 21? and it sets the address on the bus 217 to the data
verifier 207. At 405, the microprocessor 121 sets tlle address
bus 217 to an address located within the EEPROM 127 and
1 0 begins transfemng desired data onto the data bus 217. At 407,
the data verifier 207 upon verif ying the known recei~red bit
patten~, generates a svnte_enable_trigger signal 207, which is
coupled to both the input of a one-shot 203 and to the AND gate
205. At 409, the one-~hot 203 generates, responsive to the
1 5 write_enable_trigger signal 313, the write_ok_signal 311 for
the time requiret to transfer the largest bloc~ of desired data to
the ~i~ROM 127. In the preferred embodiment, the time is 50
uS.
At 411, if a data blo~ sent by microprocessor 121 is shorter
2 0 ~an the largest data blo~k sent, then the reset ~ignal 317(209)
is generated by microprocessor 121 and input into the one-shot
reset input, thereby disab}ing the write_enaWe_signal 315 to
the EEPROM 127. The reset sigDal 317(209) functio~s a~ a
variable window for the v rite_enable_signal 315 which is
2 5 adju~ted to fit the lengt}~ of data block written to the EEPROM
127. AlterDati~ely, the reset signsl 317(209) may be generated
in respon~e to proWem in ~he rsdioteaephone 101, thereby
canceJling th~ =- der of t~e write cy~e to avoid any filrther
damage to the EEPROM 127. In the preferred embodiment, the
3 0 reset signal 317(209) is tngered in response to an attempted
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read or an additional chip select e~ecuted by the
microprocessor 121. T'nese signals indicate that the
microprocessor 121 may be e~ecuting the wrong code.
In the aforementioned description we ~ave described an
5 apparatus and method of ninimizing data comlption of a
memory device wit~ a simple ~anable window write enable
circuit.
What i8 claimed is:
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