Note: Descriptions are shown in the official language in which they were submitted.
093/12566 2101~ 4 9 PCT/US92/10250
REMOTELY PROGRAMMABLE ELECTRONIC TRIP SYSTEM
BACKGROUND OF THE INVENTION
,
Fleld of the Invention
This invention relates to a method and apparatus for remotely prograrnming
multiple operating parameters into a breaker system. In particular, the method
and apparatus of the present invention comprises one or more breaker units, each5 unit having remotely programmable trip characteristics.
Description of the Relevant Art
Trip systems used for breaking electrical flow to a load or current sink are
well known in the art. Trip systems generally respond to current fluctuations inthe power lines by activating a responsive open condition at the trip unit which10 detects the corresponding fluctuation. Most simple trip systems employ an
electromagnet to trip the circuit in response to current or voltage fluctuations. The
electromagnet provides a magnetic field in response to current flowing through the
breaker unit. When the current level increases beyond a predetermined threshold,or trip point, the magnetic field "trips" a mechanism which causes a set of circuit
15 breaker contacts to release, thereby "opening" or "breaking" the circuit path.
Many simple trip systems also employ a slower responding bi-metallic
strip, which is useful for detecting subtle overload fault. This is because the
extent of the strip's deflection represents an accurate thermal history of the circuit
breaker and, therefore, even slight current overloads can be detected. Generally,
20 the heat generated by the current overload will cause the bi-metallic strip to deflect
into the tripping mechanism to open or break the circuit path.
The tripping systems described above have been useful for many years, but
there has been an increasing demand for a more intelligent and precise tripping
system. For example, many businesses today use expensive 3-phase power
25 equipment which provides critical functions to the business and its customers.
Due to the cost of the equipment and the functions that the equipment provide, the
power supply to the equipment must be precisely measured and controlled. For
this reason, microprocessor-based tripping systems have been developed in an
attempt to provide programmable control to the equipment user.
WO 93/12566 21 0l 8 ~ 9 PCr/US92/1
.
A major problem in the design of microprocessor-based tripping systems
has been the difficulty in programming the trip characteristics in each trippingunit. Quite often, a tripping system employs numerous trip or breaker units, andin order to reconfigure the system, each unit must be prograrnmed at the unit cite
Thus, while microprocessor-based tripping systems can accurately and reliably
measure the power provided to the equipment user, microprocessor-based tripping
systems often require physical access and laborious programming of each unit. `
Each unit in the entire trip system must be separately programmed.
Three-phase power equipment is becoming more sophisticated requiring
more flexibility in h~w the trip characteristics are configured. For example,
equipment may be more sensitive to ground fault interrupt than to other forms ofcurrent fluctuation. Accordingly, the trip system must be quicldy and easily
reconfigured for ground fault interrupt in lieu of other forms of trip
characteristics. Other equipment may be more sensitive to short circuit conditions,
thereby requiring quick and easy reconfiguration for short circuit trip
characteristics. Failure to quickly reconfigure each breaker or trip unit within a
trip system to perforrn the specific designated trip function may result in
inadvertent (nuisance) trips or missed trips which may damage the sophisticated
three-phase power equipment attached at the current path load.
SUMlvlARY OF THE INVENTION
The problems outlined above are in large part solved by the apparatus and
method of the present invention. While conventional microprocessor-based trip
units require operator to physically contact the unit in order to reprogram tripcharacteristics, the trip system of the present invention comprises remote
programmability to select units within the system. Thus, a trip system of the
present invention can be quickly and easily reconfigured at a remote location. 'rhe
engineer or operator need not physically contact each and every unit within the
system in order to reconfigure the system trip characteristics to fit the specific
need of the load power equipment. Remote programmability thereby can
accommodate power equipment interchange by the trip characterisdcs necessary
for a specific load.
~ O 93/12566 2 1 0 1 8 4 9 P ~ /US92/10250
Because each microprocessor-based trip unit is provided as a generic unit
which can be programmed in the field to a desired characteristic, the present trip
system is particularly suited for zone selective interlocking (ZSI) in which thelocation of a short circuit and/or ground fault is isolated and cleared without any
5 harm to the load or any unintentional time delay. The present system provides a
higher level of ZSI sophistication by allowing breaker units to communicate witheach other over a single interconnect line and regardless of the type of currentfluctuation (ground fault, overload, short circuit, etc.) encountered. Conventional
microprocessor-based systems are generally limited to detection of only one
10 specific current fluctuation (i.e., ground fault) and were generally incapable of
reconfiguration to other forrns of fluctuations. The microprocessor-based systemof the present invention not only allows remote programmability but
reconfiguration for various types of fluctuations as well as allowing remote power
up or power down of one or more selective breaker units within the overall
15 system. Accordingly, an important advantage of the present system is the ease by
which the system can be reconfigured in a flexible format to receive and
accommodate various trip points for substantially any form of current fluctuation.
Broadly speaking, the trip system of the present invention includes one or
more programmable breaker units. Each programmable breaker unit comprises a
20 3-phase current path and a trip solenoid means for breaking the current path. A
microcomputer is coupled between the current path and the trip solenoid having
stored trip points which activate the trip solenoid when current within the current
path exceeds the trip points. In addition, each breaker unit is remotely accessed
via a remote programmer means which is coupled to the microcomputer for
25 remotely monitoring the stored trip points. Each breaker unit may also include a
trip system housing which contains the trip solenoid and microcomputer. The
housing also includes a local display and binary coded decimal (BCD) input for
allowing local programming of each unit if so desired.
In one preferred embodiment, the programmable trip system comprises at
30 least one trip unit, or downstream trip unit, including three current sensorscoupled tc a 3-phase current path, and a microcomputer coupled to the sensors.
The microcomputer is capable of adding AC current transmitted through all three
21;~18~9
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of the current sensors as well as measuring RMS current through each of the
current sensors. A solenoid placed within the downstrearn trip unit can break the
current path when the output of the added AC current and/or the output of the
RMS current exceeds a plurality of stored trip points. The stored trip points are
placed in a memory media within each microcomputer and can be remotely
accessed and/or changed via a remote programmer. Accordingly, trip points for
summed AC current (i.e., ground fault condition) or for RMS current (short
circuit) can be remoteiy monitored and changed according to the specific type ofload equipment used. Either ground fault of short circuit trip points can be
remotely programmed into the system as well as the relative magnitudes of each
trip point.
The present invention also contemplates a method for remotely
programming ground fault trip characteristics and short circuit trip characteristics
in a breaker system. This method comprises coupling at least two programmable
breakers to a current path between the current path's source and load. The
breakers are interconnected with a single interconnect line, and at least one
breaker can be remotely programmed to break the current path when the current
path receives current fluctuations which exceed a set of trip points stored within
the respective breaker. Furtherrnore, a restraint out signal can be transmitted from
the breaker to the other breaker over the single interconnect line. The restraint
out signal is utilized for ZSI short circuit or ground fault isolation within the
current path.
~RIEF DESCRI~ION OF THE DRAWINGS
Other objects and advantages of the invention will become apparent upon
reading the following detailed description and upon reference to the accompanying
drawings in which:
FIG. la is a remotely programmable trip system according to the present
invention;
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i`~" 5
FIG. lb is a block diagram of a microprocessor based remotely
programmable breaker unit of the present invention;
FIG.2is a perspective view of a remotely prograrnmable breaker unit as
set forth in the block diagram of FIG. lb;
S FIG. 3a is a diagram illustrating a local display 150 of FIG. lb;
FIG 3b is a flow chart illustrating a manner in which a local processor 316
of FIG. 3a may be programmed to control an LCD display 322 of FIG. 3a;
FIG. 4 is a schematic diagram illustrating an analog input circuit 108, a
sensor circuit 110, a gain circuit 134, and a power supply 122 of FIG. lb;
FIG.5 is a timing diagram illustrating the preferred manner in which
signals received from the gain circuit 134 are sampled by the microcomputer 120
of FIG. lb;
FIG. 6a is a side view of a rating plug 531 ofFIG. 4;
FIG. 6b is a top view of the rating plug 531 of FIG.4;
FIG. 7is a schematic diagram illustrating a thermal memory 138 of FIG.
lb;
FIG. 8is a schematic diagram illustrating the reset circuit 124 of FIG.lb;
FIG. 9is an illustration of a user select circuit 132 of FIG. lb;
FIG. 10a is a diagrarn of the remote program interface 116 shown in FIG.
lb; and
FIG. lOb is a flow chart illustrating the configuration and programming
protocol used in conjunction with the remote prog~arn interface 116 for down
loading configuration parameters to the programmable trip system.
While the invention is susceptible to various modifications and alternative
forms, a specific embodiment thereof has been shown by way of exarnple in the
drawings and will herein be described in detail. It should be understood,
however, that it is not intended to limit the invention to the particular form
disclosed, but on the contrary, the intention is to cover all modifications,
equivalents, and altematives falling within the spir~t and scope of the invention as
defined by the appended claims.
DETAILED DESCRIPIlON OF THE PREFERRED EMBODIME~TS
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210'1~'~9 ~' ~
Turning now to the drawings, a remotely prograrnmable tripping system 10
is illustrated in FIG. la. Tripping system lO includes a power source 12 and a
power load 14 connected by 3-phase current path or line 16. Line 16 carries
phases A, B and C, as well as a neutral line, ~N). Tripping system 10 also
S includes one or more remotely programmable breaker units lO0 coupled to curjrent
path 16. Each unit 100 is interconnected with a single ZSI conductor 18. ZSI
line 18 allows units lO0 to communicate with each other in a zone selective
interlocking configuration. ZSI, and its mode of operation, will be described indetail below.
Along with ZSI interface and communication capabilities, the present
invention also provides remote programmability of selective units 100 via remoteprogrammer 20.
The present invention has direct application for monitoring and interrupting
a current path in an electrical distribution system according to parameters which
lS may be programmed by the user at a remote location via programmer 20.
Furthermore, the user can monitor current flowing within path 16 at remote
programmer 20. Thus, programmer 20 either transmits or receives optical
configuration signals 22 which correspond with the internal configuration or setpoint configuration of each unit lO0. Also, signals 22 include current and/or
20 voltage readings taken from line 16 as well as trip history maintained within each
unit 100. It is important to note that any form of current or trip indicia can be
sent via signals 22 and analyzed, acted upon or monitored by programmer 20. As
will be discussed below, the various indicia, of which can be accessed by
programmer 20, is useful in reconfiguring and monitoring the entire system 20
25 based upon any changes made to either source 12 or load 14. According}y, the
present invention allows a generic unit 100 be placed in the field and programmed
at a remote location to any forrn of trip forrnat or desired operating parameters
dictated by the end user. The generic unit 100 thereby achieves advances over
previous computer or microprocessor-based systems. In addition, ZSI line 18
30 allows direct interface between units 100 to provide restraint in/out isolation of
either short circuit or ground fault conditions without using multiple ZSI lines.
~0 93/12566 2 1 01 ~ ~ 9 Pcr/US92/10250
FIG. lb shows a block diagram of programmable breaker unit lOO for use
with 3-phase current path 16 having source inputs 102 and load outputs 104.
Breaker unit 100 uses an analog input circuit 108 and a GF/SC sensor llO to
detect 3-phase current on the current path 16. When the tripping system det~cts
S any forrn of current fluctuation such as short circuit, ground fault, overload, or
otherwise determines that the current path should be interrupted, it engages a
solenoid 112 which trips a set of contactors 114 to break the curIent path carrying
phases A, B and C. Consequently, any current fluctuations such as short circuit
or ground fault circuit through the earth ground path or through an optional
neutral line (N) may be broken.
Breaker unit lOO utilizes a number of circuits to determine when current
path 16 should be interrupted. This determination is cent~alized at a
microcomputer 120, preferably an MC68HCllAl, which is described in
MC68HCll HCMOS Sin~le Chip Microcomputer Programmer's Reference
Manual, l985 and MC68HCl lA8 Advanced Inforrnation HC Sinele Chiy
MicrocomDuter, 1985, all being available from Motorola, Inc., Schaumburg,
Illinois. Peripheral circuits that support microcomputer 120 include a reset circuit
124 that verifies the sanity of breaker unit 100, a voltage reference circuit 126 that
provides a stable and reliable reference for analog to digital (A/D) circuitry
located within the microcomputer 120, ROM 128 that stores the operating
instructions for the microcomputer 120, and a conventional address and data
decoding circuit 130 for interfacing the microcomputer 120 with various circuitsincluding the ROM 128 and a user select circuit 132. The address and data
decoding circuit 130, for example, includes an address decoder part No. 74HC138
and an eight-bit latch, part No. 74HC373, to latch the lower eight address bits
which are alternatively multiplexed with eight data bits in conventional fashion.
The ROM, for example, is part No. 27C64. The user select circuit 132 allows the
user to physically contact the outer face of breaker unit 100 and to programmably
designate tripping characteristics for breaker lOO, such as short circuit, overload
and phase imbalance fault (ground fault) conditions. Thus, not only may unit lOObe remotely programmed, but user select circuit 132 provides that, as a backup,
each unit 100 can be locally programmed on the outer face of the unit.
WO93/12566 21~8i~4~ PCI/US92/10250
~'
Breaker unit 100 is operatively coupled with a conventional electrical
distnbution system through a restrain in/out circuit 105. As shown in FIG. la,
signals received over ZSI line 18 from a "downstream" breaker unit 100 indicate
that a current fluctuation condition is present between the downstream unit 100 and
load 14. Thus, the downstream unit 100 transmits, via ZSI line 18, a restraint
signal to the upstream unit 100 to signal a delay or restraint on the upstream unit
to allow the downstream unit a chance to trip first. Thus, ZSI allows coordination
between the units so that when a downstream breaker senses a current fluctuation,
it sends a restraint signal to the upstream breaker instructing that breaker to carry
out a selected or programmable time delay. If the upstream circuit breaker does
not receive a resttaint signal from a downstrearn breaker, it ignores the remotely
progra nmed trip delay setting and trips instantaneously. Thus, the trip unit shown
in FIG. lb can either receive restraint information from a downstream or it can
transmit restraint information to an upstream unit via restraint in/out circuit 105
and ZSI line 18. Unit 100 uses these restraint signals in conjunction with its
ground fault and short circuit protection functions.
(iround faults are a result of leakage current to ealth in an electrical
dist~ibution system. The leakage current level is usually low compared to the
normal loading characteristics of an electrical circuit or load 14. Protection levels
for ground fault on an industrial circuit breaker unit would typically be adjustable
from 20% to 75% of the circuit breaker unit's full load current carrying capacity.
The ground fault trip delay is adjustable from 0.1 to 0.5 seconds. If a circuit
breaker unit 100 detects a ground fault it will immediately raise its restraint-out
line 105 to communicate, via ZSI line 18, to an upstream breaker unit that a fault
condition has been detected. This upstream breaker unit is then szud to be
"restrained". Any breaker witnessing a ground fault must receive a ground fault
restraint signal from a downstream breaker within 33 milliseconds or it will
initiate an immediate trip without delay. If it receives a restraint signal from a
downstream breaker, it will begin its time delay and trip after time-out unless the
fault is removed from the downstream breaker unit. Because ground fault
protection is not required for all circuits, it may or may not be installed depending
upon the type of load 14 or tripping system lO desired.
~o 93/12566 21 ~18 ~ 9 PCI/US92/10250
Short circuits are similar in nature to ground faults with the exception that
the fault current is not generally leakage to earth but rather a high current short to
a nonnal circuit conductor. Short circuit protection levels are typically adjustable
from 200% to 1000% of the breaker unit's full load carrying capacity. The short
5 circuit trip delay time is adjustable, for exarnple from 0.1 to 0.5 seconds. Time
delay short circuit protection is not required for all circuits and may or may not be
installed.
Because of the obvious difference in fault level, it should be apparent that
ground fault restraint signals must be differentiated from short circuit restraint
10 signals Typically two sets of restraints have been used in conventional unitswhich would provide the independent fault restraining signals required for both
ground fault and short circuit functions. Thus, conventional tripping systems
which require ground fault and short circuit protection utilize at least two ZSI lines
18 Conversely, the present invention requires only one ZSI line 18 since each
15 unit 100 can be reconfigured for short circuit, ground fault, or short circuit and
ground fault, the conditions of either being transmitted over a single ZSI line to
interconnected units 100 The geographic location between upstream and
downstream breaker units may be much as 1000 feet, making installation and
maintenance of numerous communication links, or ZSI lines 18, quite e~pensive.
20 In addition, the electronic circuitry and connection means for restraint signals
becomes difficult and costly on small frame circuit breaker units If duplicativeground fault and short circuit restraint in/out circuits are required, then breaker
unit space is needlessly wasted in conventional units Conversely, the present
invention utilizes only one restraint in/out circuit 105, useable for ground fault
25 and/or short circuit, wherein all ZSI communication is achievable over a single
interface ZSI line 18.
Breaker unit 100 requires circuitry for only one restraint in/out circuit 105
with the restraining function, either ground fault or short circuit, performed via an
option in the configuration programming protocol. Remote programmer 20
30 communicates over transmission media, optical configuration signals 22 to a local
remote program interface 116 electrically coupled to microcomputer 120 as shown
in Figure lb Programmer 20 thus monitors microcomputer 120 at a remote
WO 93/12566 2 1 0 1 8 ~ 9 PCI`/US92/10~0
, ~. . . - ;` ,
location to set ZSI configuration bits in the resident non-volatile memory of the
microcomputer 120. These bits indicate the type of ZSI response that the trip
system is to perforrn with respect to a given fault condition. If the ground fault
ZSI bit is set to logic 1, the breaker unit 100 will treat the restraint in/out circuit
5 105 with reference to ground fault protection. If the short circuit ZSI bit is set to
logic 1, the breaker unit 100 will treat the restraint in/out circuit 105 with
reference to short circuit protection. If both ground fault ZSI bit and short circuit
ZSI bit are set to logic 1, breaker unit 100 will respond according to the fault
condition it detects. In this case, should ground fault and short circuit fault be
10 detected simultaneously, breaker unit 100 will preform independent time delays
and trip contactors 114 when the shortest time delay expires. In the case where
ZSI bit is a logic 0, breaker unit 100 will always perform a delayed trip function
on that fault condition.
The selectable ZSI approach provides a flexi~le and less expensive
15 alternative to the conventional independent and duplicative restraint circuits
incurred prior to the present invention. For further details regarding restraint
in/restraint out elec~ical distributions systems of conventional design, reference
may be made to U.S. Patent No. 4,706,155 to Durivage et al.
Other circuits are used along with the above circuits to provide reliability
and integrity to the breaker unit 100. For instance, the microcomputer 120
utilizes the analog input circuit 10~ along with a gain circuit 134 to measure
precisely the RMS (Root Mean Squared) current on each phase of the lines 16.
The accuracy of this measurement is maintained even in the presence of non-linear
loads.
The analog input circuit 108 develops phase signals A', B' and C' that are
representative of the current on lines 16. The gain circuit 134 amplifies each
phase signal A', B' and C' through respective dual gain sections, from which the
microcomputer 120 measures each amplified signal using its A/D circuitry. By
providing two gain stages for each signal A', B' and C', the microcomputer 120
30 can immediately perform a high gain or low gain measurement for each current
phase depending on the resolution needed at any given time.
~WO 93/12~66 2 1 0 1 ~ ~ 9 PCI/US92/10250
11
The analog input circuit 108 is also utili~ed to provide a reliable power
source to the breaker unit 100. Using current developed from the lines 16, the
analog input circuit 108 operates with a power supply 122 to provide three powersignals (VT, +9v and +5v) to breaker unit 100. The power signal VT is
monitored by the microcomputer 120 through decoding circuit 130 to enhance
system dependability.
System dependability is further enhanced through the use of a thermal
memory 138 which the microcomputer 120 interacts with to simulate a bi-metal
deflection mechanism. The thermal memory 138 provides an accurate secondary
estimate of the heat in the breaker unit 100 in the event power to the
microcomputer 120 is interrupted.
GF/SC sensor 110 is used to detect the presence of any form of GF/SC
current or voltage fluctuations (e.g., overload, ground faults and/or short circuits)
on one or more of lines 16, and to report the faults via input line 136 to the
microcomputer 120. Using user selected trip characteristics, the microcomputer
120 determines whether or not the fluctuations are present for a sufficient timeperiod at a sufficient level to trip the contactors 114. The microcomputer 120
accumulates the ground fault and/or short circuit delay time in its internal R~M.
A RAM retention circuit 140 is used to preserve the ground fault history for a
certain period of time during power interruptions.
llle RAM retention circuit 140 exploits the built-in capability of the
microcomputer 120 to hold the contents of its internal RAM provided that an
external supply voltage is applied to its MOPDB/Vstby input 141. This external
supply voltage is stored on a 150 microfarad electrolytic capacitor 143 that is
charged from the +9 volt supply through a 6.2 K ohm resistor 145. The
capacitor 143 is charged from the +9 volt supply, and clamped by diodes to the
+5 volt supply, so that the capacitor will be rapidly charged during power-up.
The ground fault and/or short circuit delay time stored in intemal RAM
becomes insignificant after a power interruption that lasts longer than about 3.6
seconds. To test whether such an interruption has occurred, the RAM retention
circuit 140 includes an analog timer 149 having a resistor 161 and a capacitor 153
establishing a certain time constant, and a Schmitt trigger inverter 155 that senses
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2 1 ~ 9 12 i~
whether the supply of power to the microcomputer 120 has been interrupted for a
time sufficient for the capacitor 153 to discharge. Shortly after the microcomputer
reads the Schmitt trigger 155 during power-up, the capacitor 153 becomes `
recharged through a diode 157 and a pull-up resistor 159. Preferred component
values, for example, are 365 Kohms for resistor 161, 10 microfarads for capacitor
153, part No. 74HC14 for Schmitt trigger 155, lN4148 for diode 157, and 47
Kohms for resistor 159.
Another important aspect of breaker unit 100 is its ability to transfer
information between itself and the remote or local user. This information includes
the real-time current and phase measurements on lines 16, the system
configuration or trip points stored within breaker unit 100 and information relating
to the history of trip causes (reasons why the microcomputer 120 tripped the
contactors 114). As discussed above, the real-time line measurements are
precisely determined using the analog input circuitry 108 and the gain circuit 134.
The system configuration of breaker unit 100 and other related information is
readily available from ROM 128 and the user select circuit 132. The information
relating to the history of trip causes is available from a nonvolatile trip memory
144. Information of this type is displayed for the user either locally at a local
display 150 or remotely at a conventional display terminal of remote programmer
20 via remote program 116.
To communicate with the remote program interface 116, the tripping
system utilizes a serial communication interface 151 functionally derived by theasynchronous communication interface internal to the microcomputer 120.
Preferably, using the MC68HC11, the serial communication interface (SCI) can be
achieved internal to microcomputer 120.
Breaker unit 100 configuration parameters can be downloaded into the
nonvolatile memory (EEPROM) resident within the microcomputer 120 from
remote programmer 20 via program interface 116. Specifically, the circuit
breaker type, current carrying capacity and zone selective interlocking functions
are configured by this program interface 116. The data may be stored in the
nonvolatile memory resident using multiple (adjacent) cells to check for data
corruption. The data bytes are stored in even cell addresses with their 2's
O93/12566 2~ Pcr/us92/10250
complement stored in the next odd cell. If the sum of the data byte pair (data and
2's complement) does not equal ~ero, then that data is corrupt. The data is stored
at 2 location pairs in the EEPROM (separated by at least l page), and the data is
verified in both location pairs. If any of the pairs do not correspond with the
5 other, or do not sum to zero individually, the data is corrupt and the pair that
sums to zero is assumed to be correct. This value is rewritten to the ne~ct pair of
cells. The cell set that was corrupted is rewritten such that the cell pairs sum to
OFFH implying bad cells. Before any data can be rewritten, all data is read and
safely stored for security.
For example, all data is read from the EEPROM into temporary RAM,
using a combination of configuration byte counter and end of data masker. This
assures that all configuration data is safely stored to RAM and the EEPROM data
is correctly copied. After all configuration data has been read, both the original
and redundant data pairs are checked for validity. If any data is found to be bad,
the remaining data is shifted (opening two memory locations after the bad data),the data is reconstructed from the remaining good pair and the data is stored at the
opened locations. The bad data cells are then marked wit~ OFFH, and a bad
~EPROM cell flag is set. After all configuration dah has been checked, and
corrected if necessary, it is copied to RAM. If the bad EEPROM cell flag is set,the corrected data is rewritten from temporary RAM into the EEPROM.
Accordingly, trip points are stored in a redundant form in nonvolatile,
remotely-programmable memory such that upon an inadvertant loss of trip point
data therein, the microcomputer recovers an error-free copy of the data.
Fig. 10a is a circuit diagram illustrating program interface 116. In general,
prograrn interface 116 provides a means of electrically isolating the communication
signals between the remote programmer 20 and the tripping system's serial
communication interface 151. The electrical isolation is achieved through the use
of optocouplers 781 and 782 shown in Fig. 10a; otherwise, the program interface
cormection is preferably an electrical connection (although other forms, e.g., radio
communication, may be used). The resistors 783 and 784 limit the current
flowing in a respective receive circuit 777 and transmit circuit 778 respectively.
The transmit drive transistor 785 provides current drive for the transmit circuit
2lals~s
..
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14
778. Schmitt trigger 786 provides a data inversion for the transmit drive transistor
785. Another Schmitt trigger 787 provides data inversion and squaring of the
digital data edges coming from the receiver optocoupler 781.
Preferred components for the program interface 116 are 1.0 Kohm for
resistor 783, 270 ohm for resistor 784, part No. 4n35 for the optocouplers 781
and 782, part No. BS170 for the drive transistor 785 and part No. 74hc14 for theSchmitt triggers 786 and 787. `
FIG. 2 is a perspective view of the tripping system 100 as utilized in a
circuit breaker housing or frame 210. The lines 16 carrying phase currents A, B
and C are shown passing through line embedded current transformers 510, 512
and 514 (in dashed lines) which are part of the analog input circuit 108. Once the
solenoid 112 (also in dashed lines) breaks the current path in lines 106, the user
reconnects the current path using a circuit breaker handle 220.
Except for the circuit breaker handle 220, the interface between the breaker
unit 100 and the user is included at a switch panel 222, an LCD display panel 300
and a communication port 224. The switch panel æ2 provides access holes 230 to
permit the user to adjust binary coded decimal (BCD) dials (FIG. 8) in the user
select circuit 132. The communication port 224 is used to receive or ~ansmit
information as described above to the remote programmer 20 via an optic
transmission channel. Thus, set point data may be entered either locally via holes
230 or remotely via communication port 224.
In the following sections, the breaker unit 100 is further described in detail.
A. Local DLsplav
FIG. 3a is a schematic diagram of the local display 150 of FIG. lb. The
local display 150 is physically separated from the remaining portion of the breaker
unit 100, but coupled thereto using a conventional connector assembly 310. The
connector assembly 310 carries a plurality of communication lines 312 from the
microcomputer 120 to the local display 150. These lines 312 include ~ripping
system ground, the ~5V signal from the power supply 122, serial communication
lines 314 for a display processor 316, and data lines 318 for a latch 320. The data
lines 318 include four trip indication lines (overload, short circuit, ground fault
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and phase unbalance) which are clocked into the latch 320 by yet another one of
the lines 318.
An LCD display 322 displays status information provided by the latch 320
and the display processor 316. Different segments of the LCD display 322 may
5 be implemented using a variety of devices including a combination static
drive/multiplex custom or semi-custom LCD available from Hamlin, lnc., Lake
Mills, Wisconsin. For additional information on custom or semi-custom displays,
reference may be made to a brochure available from Hamlin, Inc. and entitled
Liquid Crvstal Displav.
The latch 320 controls the segments 370-373 to respectively indicate the
trip conditions listed above. Each of these segments 37~373 is controlled by thelatch 320 using an LCD driver circuit 326 and an oscillator circuit 328. The
corresponding segment 37~373 illuminates when the associated output signal from
the latch 320 is at a logic high level.
The display processor 316 controls four seven-segment digits 317 as an
ammeter to display the current in the lines 16. The display processor 316, for
example, is an NEC part No IJPD7502 LCD Controller/Driver which includes a
four-bit CMOS microprocessor and a 2k ROM. This NEC part is described in
NEC UPD7501/02/03 CMOS 4-Bit Single Chip Microprocessor User's Manual,
available from NEC, Mountain View, Ca. Other segments 375 of the LCD
display 322 may be controlled by the display processor 316 or by other means to
display various types of status messages.
For example, a push button switch 311 may be utilized to test a battery
338. To perforrn this test, the battery 338 is connected through a diode 313 to
one of the segments 375 so that when the switch 311 is pressed, the condition ofthe battery is indicated. The push-button switch 311 prefe~ably resets the latch320 when the switch is depressed. For this purpose the switch 311 ac8vates a
transistor 315. The latch, for example, is a 40174 integrated circuit.
Additionally, the switch 311 may be used to select the phase current to be
displayed on the LCD display 322 to control segments 375 such that they identifythe phase current (A, B, C or N) on lines 16 being displayed on the four seven-
segment digits 317. For this purpose the switch 311 activates a transistor 327 to
wo 93/12566 ~ ' Pcr/us92/tO250
21~49 ~"
16
invert a signal provided from the battery and to interrupt the display processor316. Each time the display processor 316 is interrupted, the phase current that is
displayed changes, for example, from phase A to B to C to ground fault to A, etc.
An optional bar segment 324 is included in the LCD display 322 to indicate
S a percentage of the maximum allowable continuous current in the current path.
The bar segment 324 is controlled by the +SV signal via a separate LCD driver
330. The LCD driver 330 operates in conjunction with the oscillator circuit 328
in the same manner as the LCD driver 326. However, the LCD driver 330 and
the oscillator circuit 328 will function at a relatively low operating voltage,
approximately two to three volts. An MCl4070 integrated circuit, available from
Motorola, Inc., may used to implement the LCD drivers 330 and 326. Thus,
when the tripping system fails to provide the display processor 316 with sufficient
operating power (or current), the LCD driver 330 is still able to drive the bar
segment 324. The LCD driver 330 drives the bar segment 324 whenever the
tripping system detects that less than about 20% of the rated trip current is being
carried on lines 16 to the load 14.
As an alternative embodiment, the bar segment 324 may be disabled by
disconnecting the LCD driver 330.
Additional bar segments 332-335 are driven by the display processor 316 to
respectively indicate when at least 20-40%, 40-60%, 60-80% and 8~100% of the
rated trip current is being carried on lines 106 to the load.
The oscillator 328 also uses part No. MC14070 in a standard CMOS
oscillator circuit including resistors 329, 336 and a capacitor 331 that have values,
for example, of 1 megohm, 1 megohm, and 0.001 microfarads, respectively.
~ven when a power fault causes the system to trip and interrupt the current on
lines 16, the local display 150 is still able to operate on a limited basis. This
sustained operation i5 performed using the battery 338 as a secondary power
source. The battery, for example, is a 3 to 3.6 volt lithium battery having a
projected seventeen year life. The battery 338 supplies power to portions of thelocal display 150 only when two conditions are present: (1) the latch 320 has
received a trip signal from the microcomputer 120 (or the test switch 311 is
activated), and (2) the output voltage level of the +SV power supply is less than
~O 93/12566 21 01 8 ~ 9 ` PCr/US92/10250
the voltage level from the battery 338. When the latch 320 latches in any one ofthe four trip indication lines from the data lines 318, a control signal is generated
on a latch output line 340. The control signal turns on an electronic switch 342which allows the battery 338 to provide power at Vcc so long as a diode 344 is
5 forward biased.
The diode 344 is forward biased whenever the second condition is also
present. Thus, when the output voltage level of the +5V power supply is less
than the voltage level from the battery 338, the diode 344 is forward biased andthe battery 338 provides power to the local display 150. In addition, the diode
344 is forward biased until a switch 346, activated by a power-up circuit 348,
allows the ~5V signal to provide power at Vcc. The power-up circuit 348
activates the electronic switch 346 only aRer resetting the display processor 316.
The power-up circuit 348, for example, is part No. ICL7665 working in
connection with resistors 349, 351, and 353 having values of 620 Kohms, 300
Kohms and 10 megohms, respectively.
Power is provided from Vcc only to the latch 320, the LCD driver 326, the
LCD driver 330, and the oscillator circuit 328. The LCD driver 330 and the
oscillator circuit 328 receive power from either the battery 338 or the +5V power
supply output via diodes 350 and 352. This arrangement minimizes current drain
from the battery 338 while allowing the user to view the status of the tripping
system lOû during any power fault situation.
Power cannot be drawn from the battery 338 unless the battery 338 is
interconnected wi~h the remaining portion of the tripping system via connector
310, because the connector 310 provides the ground connection for the negative
terminal of the battery 338. This aspect of the local display 150 further prolongs
battery life and therefore minimizes system maintenance.
In FIG. 3b, a flow chart illustrates the preferred programming of the
display processor 316. The flow chart begins at block 376 where the memory
internal to the display processor is initialized. The memory initialization includes
clealing internal RAM, input\output ports and interrupt and stack registers.
At block 378, a software timer is reset and the display processor waits for
a data ready flag which indicates that data has been received from the
wo 93/l2566 21~ ~:8 4~ I Pcr/us92/10250
18
microcomputer 120 of FIG. lb. The software timer provides a conventional
software watchdog function to maintain the sanity of the display processor. If the
software timer is not reset periodically (within a certain time interval), the display
processor resets itself.
S The data ready flag is set in an interrupt routine, illustrated by blocks 390
through 398 of FIG. 3b. The display processor is programmed to execute the
interrupt routine when it receives data from the microcomputer 120 of FIC~. lb.
At block 390 of the interrupt routine, a test is performed to determine whether the
data byte just received is the last data byte of the packet sent from the
microcomputer. If the data byte just received is not the last data byte, flow
proceeds to block 398 where a return-from-interrupt instruction is executed. If the
data byte just received is the last data byte, flow proceeds to block 392.
At block 392, a test is performed to deterrnine the integrity of the received
data packet. This is accomplished by comparing the 8-bit sum of the previously
lS received 7 bytes with the most recently received byte (last byte). If the 8-bit sum
and the last byte are different, flow proceeds to block 398. If the 8-bit sum and
the last byte are the same, the display processor sets the data ready flag, depicted
at block 396, and returns from the interrupt, via block 398, to block 380. At
block 380, the received data is stored in memory and the data ready flag is reset.
At blocks 382 and 384, the display processor utilizes a conventional
conversion technique to convert the stored data to BGD forrnat for display at the
LCD display 322 of FIG. 3a. The data that is sent and displayed at the LCD
display 322 is chosen by the operator using the switch 311 to sequence through
e~ch of the three phase currents and the ground fault current, as indicated in the
data that is received from the microcomputer 120.
At block 386, the display processor utilizes received data, including the
sensor identification, the rating plug type and the long-time pickup level, to
determine the percentage of rated trip current (short circuit or ground fault) being
carrie~d on lines 16. At block 388, the bar segments (324 and 332-335 of FIG. 3a)
are driven by the display processor in response to this determination. From block
388, flow returns to block 378.
,~Wo 93/12566 ~ i8 ~ ~ ` pcr/uss2/1o25o
19
Blocks 40~406 of FIG. 3b represent a second interrupt routine that the
display processor may be programmed to execute in response to the depression of
the switch 311. At block 400 of this second interrupt routine, the display
processor determines which phase (short circuit or ground fault) current the
operator has selected by depressing the switch 311. At blocks 402 and 404, the
display processor monitors its I/O port to deterrnine when the switch 311 is
released and to debounce the signal received from the switch 311. At block 406,
the display processor executes a return from interrupt command.
It should be noted that the display processor 316 is optional for the local
display 150 and therefore not required for its operation. Further, the local display
150 is itself an option to the tripping system and is not required for operating the
tripping system.
B. Short Circuit Current and Ground Fault Detection
FIG. 4 illustrates an expanded view of the analog input circuit 108, SC/GF
sensor 110, power supply 122 and the gain circuit 134 of FIG. lb. Each of these
circuits receive power from the three-phase current lines 16. Using this power,
these circuits provide signals from which breaker unit 100: (1) determines the
phase and current levels on lines 106 and detects the presence of a shon circuit,
(2) detects the presence of a ground fault and instantaneous short circuits, (3)provides system power, and (4) establishes its current rating.
(1) Determining Phase And Curreut
Levels And Detectin~ Short Circuits
In FIG. 4, the analog input and GF/SC sensing circuits 108 and 110
include current transformers 510, 512 and 514 that are suitably located adjacentthe lines 16 for receiving energy from each respective phase current path A, B,
and C. ~ach current transformer 510, 512 and 514 is constructed to produce a
current output that is propor~ional to the primary current in a fixed ratio. This
ratio is set so that when the primary current is 100% of the rated current
WO 93/12566 2 1 0 ~i 8; ~ ` PCr/US92Jl0~0
'
transformer size (or sensor size), the current transformer is producing a fixed
output current level. For example, for a 200 amp circuit breaker, each current
transformer 510, 512 and 514 will produce the same current output signal when
operating at 100% (200 amps) as a current transformer in a 4000 amp circuit
breaker which it is operating at 100% (4000 amps). The preferred construction
yields a current transformer output current of 282.8 milliamps (RMS) when the
primary current is 100% of the rated current.
The output currents provided by the transformers 510, 512 and 514 are
routed through a ground fault sensing toroid 508, full wave rectifier bridges 516,
518 and 520 and the power supply 122 to tripping system ground. The output
currents are retumed from tripping system ground through a burden resistor
arrangement 530. Sensing toroid 508 sums the output currents from the
transformers 510, 512 and 514. In a system utilizing a neutral (~) line 16,
sensing toroid also sums the output current from a transformer 506, which is
coupled to the neutral line (N) to sense any return current. A signal representing
this current summation is produced at an output winding 509 and is carried to a
fourth rectifier bridge 522, which is used to detect short circuit or ground fault
conditions.
On the right (positive) side of the rectifier bridges 516-522, positive phase
current signals are produced and added together at lead 524. The current at lead524 is used for the power supply 122, which is discussed in a later part of thissection.
On the left (negative) side of the rectifler bridges 516-520, negative phase
current signals are carried through the burden resistor arrangement 530 and
~wo 93/12566 2 1 ~ 1 ~ 4 9 ` Pcr/uSs2/lQ2~0
21
tripping system ground, and are returned to the rectifier bridges 516-520 through
the power supply 122. This current path establishes voltage signals A', B' and
C', each referred to as a burden voltage, for measurement by the microcomputer
120 via the gain circuit 134.
S In FIG. 4, the signals A', B' and C' are presented to the respective dual
gain sections for inversion and amplification. The gain circuit 134 of FIG. 4 isshown with one of its three identical dual gain sections, generally designated as
533, in expanded form. The dual gain section 533 receives phase signal A'. Each
dual gain section includes a pair of low pass filters 532 and a pair of arnplifiers
534 and 536. The low pass filters 532 provide noise suppression, and the
amplifiers 534 and 536 reduce the signal magnitude by 0.5 and increase the signal
magnitude by a factor of 3, respectively, for the desired resolution. This
arrangement allows the microcomputer 120 to instantaneously measure these
current levels without changing any gain circuitry. Preferred component values
are, for example, 10 Kohms for resistors 541, 543, 545, 553 and 555; 4.75
Kohms for resistors 547 and 559; 60 Kohms for resistor 557; and 0.03
microfarads for capacitors 549 and 561. The amplifiers 551 and 663 are, for
example, part No. LM124.
Using the gain circuit 134, the microcomputer 120 measures the true RMS
current levels on lines 106 by sampling the burden voltages developed at signalsA', B' and C'. The RMS calculations are based on the formula:
IRMS2 =' ~ I(t)2
t=O
where:
Wo 93/12566 ~ ~ pcr/us92/1o2so
2~01~9``` ~
22
N = the number of samples;
t = time at discrete intervals
(determined by sample rate); and
I(t) = the instantaneous value of the current flowing
through the breaker.
The current flowing through the circuit breaker is sampled at fixed time
10 intervals, thereby developing I(t). The value of this instantaneous current sample
is squared and summed with other squared samples for a fixed number of samples
N. The mean of this summation is found by dividing it by N. The final RMS
current value is then found by taking the square root of the mean.
In FIG. 5, an example of a rectified sinusoidal current waveform is
lS illustrated for 1.5 cycles of a 60 hertz signal with a peak amplitude of 100 amps.
The sampled current is full wave rectified. The vertical lines represent the
discrete points in time that a current value is sampled. With a sample rate of O.S
milliseconds, over 25 milliseconds of time, 50 samples will be taken.
The other columns in TABLE 1 detail the binary equivalent data that the
microcomputer would process using the ratio that lO0 amps equals 255 binary.
The value IRMS will accurately reflect the heating effect of the current
waveforrn that existed from t = O to t = N. This current waveform is typically
an A.C. waveform with a fundamental frequency of 50 to 60 Hertz, but may
contain many upper harmonics (i.e., multiples of the fundamental frequency).
In practical implementations, several factors affect the accuracy of the IRh,.s
calculation, including the sample rate and the number of samples. In the preferred
embodiment, the sample rate is 2,000 Hertz and at least 128 samples are taken
before the current magnitude is estimated.
WO 93/12566 2 ~ O 1 8`~ 9 Pcr/US92/10250
~^ 23
Accordingly, by regularly measuring the RMS current levels numerous
calculations may be made, and RMS short circuit threshold levels may be
detected.
(2) Detecting The Presence Of A Ground Fault
And Instantaneous Short Circuit Levels
The sensing toroid 508 magnetically adds the current signals from the input
windings 540, 542, 544 and 546 to indicate whether a ground fault or an
instantaneous short circuit is present on lines 106. The toroid 508 is constructed
with four identical input windings 540, 542, 544 and 546; one for each of the
current transformas 510, 512 and 514 and one for the neutral current path
transformer 506, which is optional. The toroid 508 has a single output winding
509 which provides a summed current signal.
The ground fault sensing toroid 508 includes another winding 550 to allow
a test signal to be applied at terminals 552. Using momentary switch 554, the test
signal creates a pseudo ground fault for the tripping system. The tripping system
reacts to this pseudo ground fault in the same manner as a true ground fault. The
test winding 550 is protected by a positive coefficient resistor 556 that increases its
resistance as it heats, thereby limiting the current through it and the winding 550.
The positive coefficient resistor is, for example, a Keystone PrC Resettable Fuse,
part No. RL3510-110-120-PTF. The test winding 550 eliminates the need for a
separate test transformer, which has been utilized by systems in the prior art.
The operation of sensing toroid 508 is best understood by considering the
operation of the tripping system with a ground fault and without a ground hult.
In a balanced three phase system without a ground fault, the current magnitude in
each phase is equal but 120 degrees out of phase with the other phases, and no
WO 93/12~66 210 i 8 ~ 9 PC~/USs2/1n~o
~ 4
neutral current exists; thus, the output winding 509 produces no current. As thecurrent through any phase (A, B or C) increases, the current in the neutral path is
vectorially equal in magnitude but opposite in direction to the increase in phase
current, and the magnetic summadon is still zero. When a ground fault is present,
S current flows through an inadvertent path to an earth-grounded object, bypassing
the neutral transformer 506 and creating a current signal in the transformer 509.
Thus, the transformer 509 produces a current signal only when a ground fault is
present.
The current signal from the output transformer 509 of the ground fault
sensing toroid 508 is routed through the rectifier bridge 522, the power supply 122
and returned through the burden resistor arrangement 530. In conjunction with the
rectifier bridge 522, the burden resistor arrangement 530 converts that current
signal into an A.C. rectified signal 558 that is inverted with respect to the tripping
system ground. The voltage of this signal is proportiona1 to the current in the
15 transforrner 509.
The A.C. rectified signal 558 is filtered by filter 560 for noise suppression
and then inverted using analog invertor 562. From the analog invertor 562, a
positive-going signal is carried to an A/D input at the microcomputer 120. The
microcomputer 120 measures the peak levels at the output of the analog invertor
20 562 to detect the presence of a ground fault. A conventional voltage divider
swit~ h 564 is controlled by the microcomputer 120 to selectively reduce that signal
by two thirds, as may be required under severe ground fault conditions. Preferred
component values are, for example, 10 Kohms for resistors 565 and 567; 20
Kohms for resistor 569; 19.6 Kohms for resistor 573; 10 Kohms for resistor 575;
~0 93/12566 ~ 1 0 ~ 9 PC~r/US92/l0~50
0.033 microfarads for capacitor 577; part No. LM124 for amplifier 579; and part
No. BS170 for IGFET 581.
~3) Providin~ Svstem Power
Power for the tripping system is provided directly from the current on lines
16, and current on any one of the lines 106 can be used. This feature allows thebreaker unit to power-up on any one of the three phases and to be powered when aground fault on one or more of the phase lines 16 is present. Furthermore,
breaker unit 100 can be powered up or down from a remote location via the
programmer 20.
The output currents which are induced by the transformers 510, 512 and
514 are routed through the rectifier bridges 516, 518, 520 and 522 to provide the
current for the power supply 122. On the right side of the rectifier bridges 516-
522, at lead 524, the output currents are summed and fed directly to a Darlington
transistor 568, a 9.1 volt zener diode 570 and a bias resistor 572. Most of thiscurrent flows directly through the transistor 568 to ground, to create a constant 9.1
volt level at the base of the transistor 568. Because it has a nominal emitter to
base voltage (Veb) of about 1.0 volts, the emitter of the transistor 568 is at
approximately 10 volts. The transistor 568 will maintain 10 volts across it firom
emitter to collector, regardless of the current through it. Preferred component
values are, for example, part No. 2N6285 for Darlington transistor 568; lN4739
for zener diode 570; and 220 ohms for resistor 572.
The power signal VT ("trip voltage") is provided at the emitter of the
tIansistor 568.
W~ 93/1256~ ; , ~ PCr~US92~10250
2~01~49` `
- 26
The +Sv signal is a regulated +5v power supply output signal that is
provided using a voltage regulator 571 (part No. LP2950ACZ-5.0) and a capacitor
582 which prevents the output of the regulator 571 from oscillating. The voltageregulator takes its input from VT via a diode 576. The diode 576 charges
capacitor 584 to within one diode drop (0.6v) of VT and creates a second supply
source of approximately ~9v, which is referred to as the +9V power supply.
The energy stored in the capacitor 584 enables the electronic circuitry being
powered by the ~9V power supply to remain powered for some time after a trip
occurs. A capacitor 574, connected at the emitter of the transistor 568, aids infiltering voltage ripple. The capacitor 574 is also utilized as the energy storage
element for the solenoid 112 which is activated when a power IGFET 583 is
turned on by "trip" signals from the microcomputer (120 in FIG. lb) or from a
watchdog circuit (712 in FIG. 8). The trip signals are combined by respective
diodes 591, 593. The solenoid 112 is also activated by an over-voltage conditionsensed by a 16-volt æner diode 595, such as part No. lN5246. Preferred
component values are, for example, 220 microfarads for capacitor 574, 100
microfarads for capacitor 584, 10 microfarads for capacitor 582, 100 Kohms for
resistor 585, 10 Kohms for resistor 589, 0.1 rnicrofarads for capacitor 587, andpart No. 6660 for IGFET 583.
Diodes 576 and 578 are used to receive current from an optional external
power supply (not shown).
(~) tablishin~ The Current Ratin~
On the left side of the rectifier bridges, negative phase signals (A', B' and
C') from the bridges are provided to the burden resistor arrangement 530,
93/12s66 27 PCI/US9~/10250
including a rating plug 531, to set the current rating for the tripping system. As
previously discussed, when the prirna~y current is 100% of the rated current or
"sensor size", which can be programmed via remote programmer 20 or user select
circuit 132, the current transformer output current will be 282.8 milliamperes
5 (RMS). Thus, when the microcomputer 120 reads the burden voltages using the
gain circuit 134 (FIG. lb), the microcomputer 120 can calculate the actual current
in the lines 16.
FIG. 4 illustrates parallel connections between respective resistors 527 and
529 which are used to establish the maximum allowable continuous current passing
through the lines 16. The resistors 527 are part of the rating plug 531, and the
resistors 529 are separate from the rating plug 531. The resistors 529, for
example, are each 4.99 ohm, 1%, 5 watt resistors. This value should be
compared to a corresponding value of 12.4 ohms for the burden resistor 525 for
the ground fault signal. The resistors 527 of the rating plug are connected in
15 parallel with the resistors 529 and hence cause a decrease in the combined
resistance. Therefore, the resistors 529 set the minimum current rating for the
tripping system. In a preferred arrangement, for exarnple, the minimum current
rating corresponds to 40% of the maximum current rating. The resistors 527 in
the rating plug scale the voltages (A', B', C') read by the microcomputer. This
20 enables the resolution of the A/D converter in the microcomputer to be the same
in terms of a fraction of the rated current for both the minimum and ma~imum
current rating. Conseguently, there is not any sacrifice in converter resolution for
~he minimum current rating.
wo 93/12566 211~ ~ 8 ~ 9 `` `' ` pcr~uss2/lo~
28
In FIGS. 6a and 6b, the rating plug 531 is shown to include the resistors
527 mounted on a prin~ed circuit board 587. A connector 588 is used to
interconnect the rating plug with the remaining portion of the tApping system 100.
When the rating plug is absent from the tripping system, the system reverts to its
5 minimum rating.
The rating plug 531 further includes copper fusible printed circuit links A,
B, C and D which are selectively disconnected (opened) from a printed circuit
connection 589 to inform the microcomputer 120 of the resistor values, or the
burden voltage/current ratio, in the burden resistor arrangement 530. The pAnted
10 circuit connection 589 is connected to the +5V signal via one of the contact points
on the connector 588. This connection 589 allows the tripping system to encode
the pri~ted circuit links A, B, C and D in binary logic such that one of 16 values
of each parallel resistor arrangement is defined therefrom. In a preferred
arrangement, the binary codes "1111" and "1110" are reserved for testing
purposes, and the fourteen codes "0000" to ~1101" correspond to current rating
multipliers of 0 400 to 1 000 as follows:
Code Current Rating Multiplier
0000 0.400
0001 o.soo
0010 0.536
001 1 0.583
0100 0.600
0101 0.625
011~ 0.667
~ WO 93/12566 21 018 4 9 ~ pcrtvss2/1o2so
29
0111 0.700
1000 0.750
1001 0.800
1010 0.833
1011 0.875
1 100 0.900
1 101 1.000
The user select circuit 132 of FIG. 9 includes the interface circuit used by
10 the microcomputer 120 to read the binary coded resistor value from the rating plug
531. A tri-state buffer 820 a11Ows the microcomputer 120 to selectively read the
logic level of each of the four leads representing the status of the four fusible
printed circuit links on the rating plug 531. A logic high at the input of the buffer
820, provided by the connection between the fusible printed circuit link and +SV
15 signal, indicates that the corresponding link is closed. A logic low at the input of
the buffer 820, provided by pull-down resistors 826 at the input of the buffer 820,
indicates that the corresponding link is open.
The fusible printed circuit links A, B, C and D may be opened using a
current generator to send an excessive amount of current through the links,
20 thereby causing the copper linlcs to burn. This is preferably performed before the
rating plug 531 is ins~alled in the tripping system. Thus, once installed, the rating
plug 531 automatically informs the microcomputer 120 of its resistor values, and
there is no need to adjust any settings or otherwise inform the microcomputer of
the type of rating plug being used. The microcomputer may adjust the values read
25 from its A/D converter by a predetermined scale factor corresponding to the
binary coded resistor value to compute actual current values which are independent
of the resistor values in the rating plug 531.
C. Bi-metal Deflection Simulation
WO 93/12566 2 1 ~ ~ 8 ~ 9 ~ ~ PCr/US92/102~
The microcomputer 120 is programmed to simulate accurately the bi-metal
deflection mechanism that is commonly used in tripping systems that do not use
microprocessors. This is accomplished by accumulating the squared values of the
measured current sarnples that are sensed by the analog input circuit 108. The
5 sum of the squared values of that current is proportional to the accumulated heat in
the breaker unit lO0.
To simulate the bi-metal deflection during cooling, the microcomputer l20
is programmed to decrement logarithm;cally the accumulated square of the current.
In other words, during a sampling interval, the accumulated value A of I(t)2 is
lO decremented by an amount proportional to A to account for the fact that the rate of
heat loss is proportional to the temperature of the power system conductors above
ambient temperature. In particular, the temperature in the breaker unit 100
decreases if the current path in lines 16 is broken or intermittent. When this
occurs, the microcomputer 120 loses operating power and can no longer maintain
15 this numerical simulation.
This problem is overcome by utilizing the therrnal memory 138 of FIG. lb
to maintain a history of the accumulated current for a predetermined period of
time during which the operating power to the microcomputer 120 is lost. As
illustrated in FIG. 7, this is accomplished using an RC circuit 610 that is
20 monitored and controlled by the microcomputer 120 to maintain a voltage on the
capacitor 61 l that is proportional to the accumulated square of the current. When
the microcomputer loses power, the voltage across the RC circuit 610
logarithmically decays. (The decay is governed by the equation V = V~,exp(-
t/RC).) Should the microcomputer power-up again before the voltage reaches
~0 93/12566 ~ 1 n 1 ~ ~ 9 Pcrlusg~/.n250
zero, the microcomputer 120 reads the voltage across the RC circuit 610 using a
conventional analog buffer 612 and initializes its delay accumulator to the correct
value. The analog buffer 612, for example, includes an amplifier 627 such as part
No. LM714 and a 4.7 Kohm resistor 629.
The preferred RC circuit 610, including a 100 microfarad capacitor 611
and a 3.24 rnegohm resistor 613, provides a fixed time constant of 324 seconds, or
approximately 5.4 minutes.
Control over the voltage on the RC circuit 610 is provided using IGFET
transistors 61~ and 620, such as part Nos. VP0808 and BS170, respectively.
During normal, quiescent conditions, the microcomputer 120 will not be in an
overload condition and will drive a logic low at the gate of the transistor 620,thereby disabling transistors 620 and 622 and allowing the capacitor 611 to
discharge to tripping system ground. Transistors 618 and 620 work in connection
with resistors 621, 623 and 625, which have values, for example, of 100 Kohms,
47 Kohms, and 5.1 Kohms, respectively.
During overload conditions, the microcomputer 120 accumulates current
information in its internal RAM to simulate the heat level, and drives a logic high
at the gate of the transistor 620 to allow the capacitor 611 to charge to a selected
corresponding level. While the capacitor 611 is charging, the microcomputer 120
monitors the voltage level using the analog buffer 612. When the selected level is
reached, the microcomputer drives a logic low at the gate of the transistor 620 to
prevent fur~er charging. The voltage on the capacitor 611 is limited to five volts
using a clamping diode 622. The forward voltage drop across the clamping diode
622 is balanced by the voltage drop through a series diode 625.
wO 93/12566 2 1~ 9 ` ` Pcrtus92tlo25o
32
For example, assume that an overload condition suddenly occurs and the
rnicrocomputer 120 has been programmed to allow for a two minute delay before
generating a trip signal at this overload fault level. After one minute in this
overload condition, the microcomputer 120 will have accumulated current
information which indicates that it is 50% of the way to tripping. The
microcomputer will also have enabled the RC circuit 610 to charge to 2.5v; that
is, 50% of the maximum 5v. Assuming, for the purpose of this example, that the
overload fault condition is removed at this point and the electronic trip system or
breaker unit 100 loses operatin~ power, when the power to the microcomputer 120
drops to Ov, the internally stored current accumulation is lost. However, the
voltage across the RC circuit 610 is still present and will start to decay by
approximately 63.2% ~very 5.4 minutes (the time constant for the RC circuit 610).
Therefore, after 5.4 minutes without current, the voltage across the RC circuit 610
will be 36.8% of 2.5v, or 0.92v.
If the overload condition would occur again at this point, th
rnicrocomputer 120 would power up and measure 0.92v across the RC circuit 610.
The microcomputer 120 would then initialize its internal current accumulation toapproximately 18% (0.92v divided by the maximum of 5.0v) of the pre-
programmed full trip delay time.
The accumulation calculations performed by the microcomputer are based
on the formula:
A = ~ I(t)2
.=0
where:
wo 93/12566 PCr/US92/10250
~ 2101849 ``:
^ 33
N = the number of samples;
t = time at discrete intervals (determined by the accumulation
rate); and
I(t) = the true RMS value of current through the breaker.
During a fault, the trip unit will begin to sum the current squared value as
lO soon as the current exceeds a predetermined level for a predeterrnined period of
time, or the selected overload condition. The electronic trip system will maintain
an internal accumulation register to store a value that is proportional to the square
of the current and that is incremented periodically based on the accumulation rate.
Assuming a constant fault level of current, a fixed accumu}ation rate, and a known
lS condition of the accumulation register at t = 0, the value in the accumulation
register will increase at a determinate rate and will contain a known value at any
given time t.
For example, assume that a continuous fault is measured at 70.71 amperes
(RMS) with an accumulation period of 64 milliseconds. Further assume that the
20 accumulation register is at zero prior to the fauIt. The microcomputer 120 will
accumulate the squared value of the current every 64 milliseconds into the
register, causing it to increase at a constant rate.
With a continuous, fixed level fault, as time increases, the internal
accumulation register increases proportionally. ln order to protect the system
25 from this fault, this increasing accumulated value is compared periodically against
a predeterrnined threshold value that has been chosen to represent the maximum
allowed heat content of the system. When the accumulated value equals or
WO 93/12566 ` ~ PCr/US92/10250
21~49 34
exceeds this predetermined threshold value, the tripping system will trip the
breaker.
A valuable aspect of accumulating the current squared value is that as the
current doubles, the current squared value quadruples and the internal
S accumulation register increases at a more rapid rate, resulting in a more rapid trip.
Thus, if the delay time (the period before the detected power fault causes a trip) is
x seconds at some current level, as the current doubles, the delay time will be x/4
seconds.
The formula for calculating the delay time for any constant current is:
' 10
T = AR~
where:
AR = the accumulation rate in seconds;
K = predetermined final accumulation value; and
the true RMS value of current flowing through the
breaker.
D. Reset Circuitr~
Referring now to FIG. 8, an expanded view of the reset circuit 124 is
shown to include a power-up reset circuit 710 and a watch-dog circuit 712 to
maintain the integrity of the tripping system 100. The power-up reset circuit 710
25 performs two functions, both of which occur during power-up: it provides a reset
signal (asserted low) on line 743 to maintain the microcomputer 120 in reset
condition until the tripping system 100 develops sufficient operating power from
the current lines 106; and it provides a reset signal (asserted low) via lead 744 to
~ WO 93/12566 2 ~ O 1 ~ 4 9 PCI/U~92/10250
the watch-dog circuit 712 to prevent the watch-dog circuit from engaging the
solenoid 112 during power-up. This function prevents nuisance tripping.
Preferably the power-up reset circuit includes an under-voltage sensing
integrated circuit 745 that detects whether or not the output voltage of the ~5 volt
supply is less than a predetermined reference voltage at which the microcomputer(120 in FIG. lb) may properly function. The integrated circuit 745 is, for
example, part No. MC33064P-S, which holds the reset line 743 low until the
output voltage of the +5 volt supply rises above 4.6 volts. The microcomputer
120 may operate at 4.5 volts or above. The preferred reset circuit also includes a
pull-up resistor 741, a capacitor 739, and a diode 753 connecting the integratedcircuit 745 to the watchdog circuit 712. The resistor 741, for example, has a
value of 47 Kohms and the capacitor 739 has a value of 0.01 microfarads. The
diode 753 ensures that the reset circuit 71û affects the watchdog circuit 712 only
when the microcomputer 160 is being reset.
The watch-dog circuit 712 protects the tripping system from microcomputer
malfunctions. Thus, it is designed to engage the solenoid 112 if the
microcomputer 120 fails to reset the watch-dog circuit 712 within a predeterrnined
time period. The microcomputer 120 resets the watch-dog circuit 712 by regularlygenerating logic high pulses, preferably about every 200 milliseconds, on lead
714. These pulses are passed through a capacitor 718 to activate an IGFEI
transistor 720, which in turn discharges an RC timing circuit 724 through a circuit
limiting resistor 733. A resistor 730 and a clamping diode 732 are used to
reference the pulses from the capacitor 718 to ground.
WO 93/12~66 ~ ; Pcr/us92/10250
2 ~ $ ~
36
The pulses on lead 714 prevent the RC timing circuit 724 from charging up
past a reference voltage, Vref, at the input of a comparator 726. If the RC timing
circuit 724 charges past Vref, the comparator 726 sends a trip signal to the
solenoid 112 to interrupt the current path in lines 106. The reference voltage, for
5 example, is provided by a 4.3 volt zener diode 427 supplied with current through
a resistor 729. Preferred component values are, for example, 0.001 microfarads
for capacitor 718, 27 Kohms for resistor 730, part No. lN4148 for diode 732,
part No. BS170 for transistor 720, 10 ohms for resistor 733, 0.22 microfarads for
capacitor 735, part No. LM29031 for comparator 726, part No. lN4687 for diode
727, 100 Kohms for resistor 729, and 10 Kohms for resistor 751.
E User Select Switches
.
As introduced above, the user select circuit 132 is illustrated in FIG. 9. In
addition to the buffer 820 for the rating plug, the user select circuit 132 includes a
plurality of user mterface circuits 810 each having a pair of BCD dials 812 and a
tri-state buffer 814 which is enabled through the address and data decoder 130 of
FIG. lb. Each BCD dial 812 allows the user to select one of several tripping
system characteristics. For example, a pair of BCD switches may be used to
designate the longtime pickup and the longtime delay (overload tripping
characteristics) and another pair of BCD switches may be used to designate the
20 short time pickup and the short time delay (short circuit tripping characteristics).
Other BCD switches may be used to designate sensor and breaker sizes, an
instantaneous pickup, ground fault tripping characteristics, and phase unbalance
thresholds.
F. Ener~v Validation For Solenoid Activation
~ ~ W O 93/I2566 2101~49 ~ PC~r/U~92/l02Sn
The user select circuit 132 of FIGS~ lb and 9 also determines if there is
sufficient energy to activate the solenoid 112~ Using the address and data
decoding circuit 130, the buffer 820 is selected to read one of its input lines 830.
The VT signal from the power supply 122 of FIG. lb feeds the input line 830,
with the buffer 820 being protected from excessive voltage by a resistor 832 and a
clamping diode 834. The resistor 832, for example, has a value of 620 Kohms.
Before the microcomputer 120 engages the solenoid 112, the input line 830
is accessed to determine if VT is read as a logic high or a logic low. The buffer
820 provides a logic high at its output whenever the input is greater than 2.5v to
3v. If VT is read as a logic high, the microcomputer 120 determines that there is
sufficient power to activate the solenoid 112 and attempts to do so. If ~ is read
as a logic low, the microcomputer 120 determines that there is insufficient power
to activate the solenoid 112 and waits, while repeatedly checking VT, in
anticipation that an intermittent power fault caused VT to fall. Once VT rises
beyond the 2.5-3.0 volt level, the microcomputer 120 attempts to activate the
solenoid once again.
G. Communication For Information D;SDIaV
The microcomputer 120 sends identical tripping system status information
to the local display 150 and the display terminal 162. The information is sent
synchronously on a serial peripheral interface 191 to the local display 150 and
asynchronously on a serial communication interface 151 to the display terminal
162. The interfaces 151 and 191 may be implemented using the SCI and SPI ports
internal to the MC68HCll~
2 1 0 1 8 ~ 9 PCr/Uss2/102~
38
The history of the tripping system status information is stored in the
nonvolatile trip memory 144. That history includes the specific cause and current
level of the last trip and a running accumulation of the different trip causes.
The trip memory 144 is preferably an electrically erasable programmable
5 ROM (EEPROM), for example, a X24C04I, available from Xicor, Inc. of
Milpitas, California. In this case, the serial peripheral interface 191 is used for
bidirectional data transfer between the microcomputer 120 and the EEPROM 144.
This data transfer is implemented using one line of the serial peripheral interface
191 to transfer the data and the other line to transmit a clock signal between the
10microcomputer 120 and the EEPROM 114 for synchronization. During power up
of the tripping system 100, the microcomputer 120 transmits to the trip memory
144 a unique bit pattern which is interpreted as a data request code. The
microcomputer 120 then sets the bidirectional data line as an input and clocks the
requested data in from the trip memory 144.
15The microcomputer 120 maintains a copy of the history data in its internal
RAM and in the event of a trip, updates it and transmits it back into trip memory
144 via the interface 191, again utilizing thc unique bit pattern to set the trip
memory 144 to a receive mode. Upon receipt of the data, trip memory 144 will
reprogram its contents, overwriting the old history infonnation with the newly
20 rcceived data.
During normal operation (i.e., after power up and without a trip), the
microcomputer 120 transmits operational information over the serial peripheral
interface 191. Because this information does not contain the unique bit patterns
required to activate the trip memory 144, the trip memory 144 ignores the normal
/~r 2101~3~19 Pcr/us9~/ln~sn
39
transmissions. However, other devices which may be connected to the serial
peripheral interface 191 can receive and interpret the information correctly.
The microcomputer 120, for example, is programmed to execute a
communication procedure that permits the tripping system 100 to communicate
S with a relatively low power processor in the display processor 316. The
procedure utilizes a software interrupt mechanism to track the frequency with
which information is sent on the interfaces 151 and 191. During normal
operation, one 8-bit byte of information is sent every seven milliseconds. During
tripping conditions, information is sent continuously as fast as the microcomputer
120 can transmit. This procedure allows the display terminal 162 and the display
processor 316 to continuously display status messages from the tripping system
100 without dedicating their processors exclusively to this reception function.
Equally impor~ant, this procedure permits the microcomputer 120 to perform a
variety of tasks, including continuous analysis of the current on lines 106.
Status messages are preferably transmitted using an 8-byte per packet,
multi-packet transmission technique. The type of information included in each
packet may be categorized into eight different groups, or eight different packets,
packet 0 through packet 7. The first byte of each packet is used to identify the
byte and packet numbers and the trip status of the tripping system 100. For
20 exarnple, the first byte may contain one bit to identify the byte type, four bits to
identify the paclcet number and three bits to identify the trip status: no trip
condition, current overload trip, short circuit trip, instantaneous trip, ground fault
trip and phase unbalance trip. Bytes two through six of each packet vary
depending on the packet number. E~yte 7 is used ~o identify the tripping system
~ l Q 1 ~ ~`9 PCr/US92/l0~
sending the information (for a multiple system configuration), and byte 8 is used
as a checksum to verify the integrity of the data.
The microcomputer alternates the type of inforrnation included in each
packet, depending upon the priority type of the inforrnation. During normal (non-
5 tripping) conditions, the trip unit will transmit Packet Number 0, followed byPacket Number l, followed by one of the remaining defined Packet Numbers, 2
through 7. The sequence is graphically shown as:
1) Packet 0 - Packet 1 - Packet 2
2) Packet 0 - Packet 1 - Packet 3
3) Packet 0 - Packet 1 - Packet 4 Repeat until Trip
4) Packet 0 - Packet 1 - Packet 5 Occurs
5) Packet 0 - Packet 1 - Packet 6
6) Packet 0 - Packet 1 - Packet 7
During a trip condition, the normal operation packet transmission sequence
is interrupted and Packet number 2 is transmitted continuously until power is lost.
The transmission rate will be increased to the fastest rate possible.
The five bytes of each packet that vary according to packet number are
configured for a total of eight different packets, 0-7. The inforrnation in these
bytes is implemented for each packet number as follows:
Packet 0 - (0 0 0 0)
Data Byte 1 - Phase A Current - High Byte
Data Byte 2 - Phase A Current - Low Byte
Data Byte 3 - Phase B Current - High Byte
Data Byte 4 - Phase B Current - Low Byte
Data Byte 5 - Overload Pickups & Short Circuit Restraint In
Packet l - ~0 0 0 1)
Data Byte 1 - Phase C Current - High Byte
~VO 93/1~566 2 1 0 1 8 ~ 9 PCr/US92/10250
41
Data Byte 2 - Phase C Current - Low Byte
Data Byte 3 - Ground Fault Current - High Byte
Data Byte 4 - Ground Fault Current - Low Byte
Data Byte 5 - Short Circuit, Phase Unbalance & Ground Fault
Pickups .
Packet 2 - (0 0 1 0)
Data Byte l - Maximum Phase Current - High Byte
Data Byte 2 - Maximum Phase Current - Low Byte
10 Data Byte 3 - Maximum Phase Identification (A, B, C or N),
Breaker Identification & Ground Fault Restraint
In
Data Byte 4 - Trip Unit/Sensor Identification
Data Byte 5 - Rating Plug/Options
Packet 3 - (0 0 l l)
Data Byte l - Long Time Switches
Data Byte 2 - Short Time Switches
Data Byte 3 - Instantaneous Phase Unbalance Switches
20 Data Byte 4 - Ground Fault Switches
Data Byte 5 - Phase Unbalance Trips
Packet 4 - (0 l 0 0)
Data Byte l - Long Time Trips
25 Data Byte 2 - Short Circuit Trips
Data Byte 3 - Ground Fault Trips
Data Byte 4 - Last Maximum Phase Current - High Byte
Data Byte 5 - Last Maximum Phase Current - Low Byte
30 Packet 5 - (0 l 0 l)
Data Byte l - Software Failure Trips
Data Byte 2 - Last Phase A Current - High Byte
Data Byte 3 - Last Phase A Current - Low Byte
Data Byte 4 - Last Phase B Current - High Byte
35 Data Byte 5 - Last Phase B Current - Low Byte
Packet 6 - (01 l 0)
40 Data Byte l - Last Fault System Status Byte
Data Byte 2 - Last Phase C Current - High Byte
Data Byte 3 - Last Phase C Current - L~w Byte
Data Byte 4 - Last Ground Fault Current - High Byte
Data Byte 5 - Last Ground Fault Current - Low Byte
Packet 7 - (01 1 l~
Data Byte I - Long Time Memory Ratio
Data Byte 2 - Phase A % Unbalance
Wo 93/12566 PCr/US92/10250
~10 ~ 8ll9
42
Data Byte 3 - Phase B % Unbalance
Data Byte 4 - Phase C % Unbalance
Data Byte 5 - Software Version Identifier Byte
Accordingly, the microcomputer 120 transmits information in four
substantive classes. The first class constitutes trip status information, as set forth
in the first byte of each packet. The second and third classes involve current
measurement information; the second class including current measurement
information on each line 106, as set forth in packets 0 and 1, and the third class
10 including the maximum current status information, as set forth in packet 2. The
last class of information relates to the present configuration of the tripping system
and is contained in packets 3 through 7.
Referring to Figure lûb, a flow diagram is shown illustrated the preferred
algorithm for the configuration programming protocol described above. The
diagram begins at block 860 where the user programs via remote programmer 20,
a request to send a program sequence with new set of trip points or configuration
signals into tripping system 10. The user then may transmit the requested
prog~am to system 10 via communication channel 870. Thus, Figure lOb
illustrates a dotted line indicating activities to the left of the dotted line within
20 remote programmer 20 and activities to the right of the dotted line within tripping
system 10. Transmission of new trip points, etc. comprises optical configuration
signals 22, as shown in Figure la, to system 10, wherein system 10 temporarily
buffers the transmitted data at block 861 and cheeks the data or configuration
signals for valid transmission as shown in block 862. If the data checks good,
2~ then th~ data is transmitted back to the remote programmer 863 indicating that the
request was successfully received. If the data does not check good, error
~o 93/l2566 2 1 Q 1 8 4 9 Pcr/US92/10250
43
information is transmitted to the remote programmer and the programmer must
resend the program sequence as shown in block 864. Blocks 863, 864 and 865
look for successful transmission of program requests. Upon determining if
tripping system 10 received a valid request to change configuration trip points at
5 block 864, the remote programmer 20 transmits a store command to the tripping
system l0 to instruct the tripping system to save the new data into its non-volatile
configuration memory. The tripping system then stores the data at block 866 and
in block 867 returns to executing normal circuit breaker protection code in
transmitting the normal serial communication.
The flow diagrarn of the Figure l0b illustrates an example of the self-
checking me~hanisrn by which remote programmer 20 can insure that selective
breaker units l00 o~erate correctly. If a breaker unit l00 fails to operate upon
receiving remote programming commands, that unit l00 can be identified back to
the remote programmer 20 thereby informing the field user. As shown in block
865, specific defective breaker units l00 can be identified and inforrnation
transmitted back to the operator. If, however, the identified units correctly
receive programmed code such as, e.g., remotely programmed trip points, then the
selected unit l00 will receive configuration data within the microcomputer's non-
volatile memory, preferably EEPROM as shown in block 866. To verify accurate
20 receipt of transmitted data, the selected unit l00 sends baclc to the remote
programmer the received data stream after 250 milliseconds as shown in block
867. The programmer then waits for all paclcets of data to verify correct storage
of the configuration data, including trip points, ZSI data, etc. as shown in block
868. Once all paclcets are verified, remote programmer 20 then informs the
wo 93/t2566 2 1 0 1 8 4 9 Pcr/US9~/102~ ~
operator that correct breaker, sensor and ZSI data is received and that the
programming protocol is operating correctly as shown in block 869.
