Note: Descriptions are shown in the official language in which they were submitted.
RYN042-PCI`
~ 0~79
Fault Detection and Isolation of Fiber to the Curb Systems
Fault detection and isolation are key considerations in the design
of ~lber to the curb (~Tl C) ~nd similar systems. Deployment of fiber
s in the telephone local loop requires network availability comparable to
that of today's copper networks. To achieve this, redundancy needs to
be provided in high capacity elements of the network, but automatic
fault detection and isolation capabilities required to take advantage of
the redundancy are just as important. Automatic isolation of failures
0 significantly improves network availability and reduces maintenance
costs through accurate and timely dispatch of repair persormel.
Ellersick et al., U.S. patent application serial no. 07/697,855,
assigned to the assignee of the present invention, the disclosure of which
15 iS incorporated herein by reference, discloses a method of translating
multiple signaling nibbles contained within a signaling byte into multiple
signaling bytes for use in a ~ l l C system. This patent application
teaches using available bits in the translated FTI C signaling bytes for
data coding checking so as to achieve a degree of fault isolation and
2 o detection capability. The present invention discloses improved means
and methods ~or filrther detecting and isolating faults which preferably
are usable in conjunction with ~e aforesaid cited patent application
teachings to achieve very significant detection and isolation fault
capabilities.
An object of the invention is to provide a technique (method and
apparatus) for detecting and isolating faults, preferably in a fiber to the
curb (FlTC) system. This technique uses overhead or unused time slots
in conjunction with pattern generation and verification hardware to
30 perform bit error rate tests on digital time division multiplexed data
paths. This allows fault diagnosis without interruption of service,
especially telephone service.
Two types of time slots are preferably used to diagnose faults in
3s each half of head end multiplexer electronics, e.g. offlce interface unit
RYN042-PCI 2 ~ 0 817 9
(OIU). The first type is an unused time slot made available by running
an OIU multiplexer clock slightly faster than is necessary to provide
time slots for the full data capacity of the system(s) serviced by the
OIU. The second type is an overhead time slot normally used for
5 establishing framing information on a standard multiplexed digital
trunlc, such as the European 2.048 Mbps CCIl~ standard unterface or
the US 1.544 Mbps Tl standard interface, connected to the OIU from a
central office, or remote e~ctension thereof.
An OIU that interfaces to multiple digital trunlcs from a central
office (CO) or remote extension ~ereof and provides single line
interfaces at a suhscriber interface unit (SIU), located near customer or
subscriber premises, must synchronize all of the trunks to one OIU-S~U
frame clock to allow synchronous interconnection of single line
15 channels. This frame clock is passed through the OIU-SIU system using
separate hardware signals within the OIU and by transmitting an OIU-
SIU framing time slot over the fiber to the SIU fiber interface, the ~lber
framing time slot preferably being identified by a code violation of a
specific byte. Thus, framing information for each digital trunk need
20 not be carried past an OIU point where the digital trunks are
synchronized to the OIU-SIU system frame clock, and time slots
associated with each digital trunk can then be made available by the OIU
as overhead fault diagnosis channels.
.. .. . .
In the receive direction from the CO to the OIU, synchronization
to the system frame clock is usually accomplished in a digital framer
chip that uses a two frame deep receive first-in-first-out (FIFO)
memory that uses frame clock information to clock data in from each
digital trunk, and system frame clock information to clock data out to
the rest of the FTrC system toward the SIUs. In the opposite transmit
direction, the FIFO is not needed as data is transmitted synchronous to
the system frame clock, with the framing channel for each digital trunk
being regenerated from the system frame clock in the OIU digital
frarner.
3s
RYN042-PCr 21 ~ 8 ~ 7 ~
Digital frarners such as ones made by Base2 Systems, Inc. allow
individual 64 kbps channels to be looped back intemally. Ln the
transmit direction, this internal loop back capability is implemented
before the framing channel is generated in the transmit direction. In the
receive direction, this internal loop back is implemented after framing
inforrnation from the framing channel in the digital trunk is used to
clock data into the receive FIFO. According to a preferred embodiment
of the invention, the framing channel is looped back toward the SIUs
and used for testing without affecting the use of the framing channel on
o the digital trunk. By providing paKern generation and verification
circuitry near cross connect circuit~ of the OIU, the time division
multiplex (TDM) data path from the cross connect circuitry all the way
through most of the digital framer can be checked, without requiring
service to be interrupted as would otherwise be the case.
A preferred object of the invention is to provide a fault diagnosis
apparatus for a telecommunication system that transmits and cross-
connects telephone signals between multiple telephone exchange office
feeder lines and telephone subscriber equipment, comprising:
means for retransmitting the telephone signals in a digital time
division multiplex format from the multiple feeder lines to the
subscriber equipment and vice versa at a transmission rate in
excess of that required by a quantity of telephone voice channels
and telephone signaling channels received from the multiple
feeder lines so as to create at least one spare time slot channel in a
retransmission frame which is not necessary ~or transmitting
voice or signaling information;
pattern generation means for transmitting a predetermined bit
pattern in the at least one spare time slot channel;
pattern verification means for receiving the bit pattern in the spare
time slot channel and determining an absence or presence of a bit
error therein.
RYN042-P<`T
Page4 2108179
These and o~her obJects of the invention will be further explained
by reference to the following drawings and detailed description.
FIG 1 is a block schematic diagram of a fiber to the curb system;
FIG 2 is a block diagram of an offlce interface unit illustrated in
FIG l;
FIG 3 is a block diagram schematically illustrating system loop
backs for an office interface unit and a subscriber interface unit
illustrated in FIG l; and
FIG 4 is a further block diagram of the subscriber interface unit
illustrated in FI(i 1.
FM 1 shows a typical digital FI~C system 1~ consisting of
exchange feeders 2, an O~fice Interface Unit (OIU) 3, an Operations and
Maintenance system (O&M) system 4, distribution fibers 6, Subscriber
2 0 Interface Units (SIUs) 7 and subscriber loops 8. Fault detection and
isolation strategies for digital services and plain old telephone services
(POTS) are first discussed for such a system 1, followed by fault
detection and isolation algorithms for failures inside the FTTC system.
ISDN and other digital services have built-in cyclic redundancy
check (CRC~ checksums which provide excellent fault detection. The
exchange or subscriber equipment will detect failures of FrTC system
elements for ISDN and other digital services, using the CRC checksums
passed through the entire system. Using CCIl-r recommended
maintenance channels, the exchange is relayed failure information from
CRC checkers in the Line Interface Units (LIUs) in the SIUs as well as
in ~e subscriber equipment. With this information, and the use of loop
backs in each LIU, failures can be isolated with good confidence to the
exchange, exchange feeders, the FTI'C electronics, subscriber loop or
3s subscriber equipment. The Fl~C system is also relayed failure
RYN042-PCI
Page 5 2 1 0 8 1 7 ~
infomlation from CRC checkers in the exchange and subscriber
equipment, and can thus distinguish between FTTC system and external
failures. Isolation of intemal FlTC system failures is discussed in more
detail below.
POTS presents unique and di~icult fault detection problems, as
there is no capability for fault detection at the subscriber equipment 10
(telephone), and CRC checksums on digital feeders are generally
terminated at the OIU's line interface units 11 (LIUs), as they cannot be
10 maintained through cross-connect circuitry in the OIU. Thus, internal
fault detection on POTS is needed throughout an ~ l l C system, and the
present invention is directed to fulfilling this need.
The invention combines three fault detection techniques: CRC
checksums and coding propagated through the system, data comparisons
between redundant modules, and non-service affecting loop back tests.
After detection, emphasis is placed on fault isolation techniques that
clearly identify ~e failed module. These techniques rely on loop backs
at module and subsystem interfaces, comprehensive self tests, and on
20 utilization of shared Passive Optical Network (PON) topologies to
isolate failures to head end or remote equipment.
Digital feeders and LIUs are tested by CRC checksums and line
coding generated and verified in the LIUs at each end of the feeder. By
2 5 carrying internal data coding or checksums up to the analog POTS LIUs
in the SIUs, an Fl~C system can achieve nearly instantaneous fault
detection on all data paths carrying mor~ than one phone call.
Faults are detected on POTS LIUs and subscriber loops by
30 running tests at service turn up or on demand. LIU tests include analog
reflection and idle channel noise tests. Subscriber loop tests include
foreign voltage, impedance and leakage current tests. Failures Oll POTS
service channels can be isolated to the LIUs or subscribers loops by
running digital BER and analog reflection tests. Loop failures can be
RyNo42-pcr 2 ~ 0 81~ ~
isolated to customer premise wiring by detecting demarcation circuitry
at the end of the subscr~ber loop.
- To allow comprehensive finnware to be developed with flr~ite
resources, the fault isolation approach of the invention focuses on tests
which clearly isolate faults tO ~leld replaceable units (FRUs), such as bit
error rate (BER) tests with loop backs at F~U interfaces or
comprehensive FRU self tests.
In a preferrcd FrTC system~ service is carried digitally, mostly
in time division multiplexed (TDM) data paths. According to the
S invention, spare time slots are generated within the OIU by running an
OIU multiplexer frame clock faster than is necessary to provide time
slots for a full data capacity of systems serviced by the OIU. More
specifically, according to a preferred embodiment, an OIU internal bus
is run at a speed in excess of S megahertz, giving a capacity of 640 time
slots, or nominally 512 DS0s plus 120 ABCD signaling byte time slots
with 8 spare time slots, otherwise referred to as available overhead, as
also more fully described in the copending application cited above.
o BER tests on these spare time slots provide an lnexpensive, effective
solution for detecting faults on TDM data paths. With loop backs
implemented near FRU interfaces, these BER tests can also be used to
isolate faults.
According to the invention, each ABCD signaling byte is cross- :
connected in the OIU to its own dedicated time slot or channel so that,
in the example indicated, for transmission feeder lines which include
120 ABCD signaling nibbles, generally stacked in 60 time slots, the OIU
connects these 120 signaling nibbles into 120 signaling time slots.
Accordingly, since each signaling time slot generated within the OIU
contains 4 bits corresponding to the ABCD signaling information, 4
additional bits remain unused which can be utilized for fault detection,
for example by utilizing a binary 1 or 0 checksum algorithm.
..... .. ... . .. . .. . .
RYN042-PCT
Page 7 2 1 0 8 1 7 ~
While BER ~ests using "robbed" in service time slots are a
standard technique for fault diagnosis, the allocation and use of
overhead or spare time slots for BER testing according to the invention
is new and provides excellent fault detection and isolation capabilities
5 without service inte~uption, as occurs when time slots are robbed.
BER tests on unused or overhead time slots are an inexpensive,
effective solution for detecting faults on TDM data paths. With loop
backs implemented near FRU interfaces, ~ese BER tests can also be
10 used to isolate faults. Space division multiplexed data paths (e.g. cross-
connect memories) can be effectively checked by comparing the outputs
of redundant hardware.
Failures of clock generation hardware can take down service to
all customers served by the system, and can be dif~lcult to isolate with
BER tests. To ensure rapid fault isolation and recovery, clock
generation circuitry is perhaps most effectively checked by comparing
the outputs of redundant modules. Disagreements between redundant
hardware modules that compare their outputs can be resolved with
20 comprehensive self tests, or by checking the results of nonintrusive BER
tests with each of the disagreeing modules in service.
Faults on digital feeders or distribution fibers can be isolated by
looping back at FRU interfaces. PON-based systems can utilize
25 knowledge of their topology to isolate failures between SIUs and shared
distribution fibers, as an SIU failure will leave other SIUs error free.
Where possible, a processor's functions should be limited to
maintenance and provisioning of service, and associated service
30 carrying hardware should be designed to continue operating under
processor failures. Thus, processor or firmware failures do not add to
system downtime. In addition, redundancy is not required on non-
service affecting processors, reducing hardware costs and firmware
complexity. Fault detection on processors is provided by watchdog
35 timers and periodic polling of distributed processing elements.
; .- . . . . , ,.. ~ , . , - .
RyNo42-pcr
Page8 2~0~17~
Referring to FIG 2, the OIU comprises a shelf with plug-in
FRUs. The FRUs comprise E1 Modules 13 (ElMs) which transfer data
between 2048 Kbps lines 2~ a Global Cross-connect Module 14 (GCM),
5 and a timing generation module 17 (TGM). The GCM programmably
connects data channels between the ElMs and the Distribution Fiber
Modules 15 (DFMs), and also contains pattern generation and
verification circuitry for automated or on demand testing of the system.
Central Processing Module 16 coordinates fault isolation, provisioning
10 of service, and interfaces with the O&M system 4. An OIU backplane
which interconnects the FRUs has redundant timing and data busses to
prevent loss of service due to a driver or receiver failure and contains
no active components to minimize the chance of field backplane failures.
The TGM and GCM each compare their outputs with redundant
hardware, e.g. a redundant TGM and GCM, providing excellent fault
detection coverage, and use comprehensive self tests and redundancy
switching to isolate faults to the failed PRU. If the two GCMs' or
TGMs' outputs do not match, the offline board is self tested. If the self
20 test fails, the offline board is labelled "faulty" and the fault has been
isolated. Otherwise, the offline board is switched in and the previously
online board is self tested. If it fails self test, it is labelled "faulty". If
both boards pass self test, and there are no secondary failure indications
that point to one of the boards, they are both labelled "suspect", the
2 s previously online board is switched back online, and a manual fault
isolation procedure is necessary.
For digital services, ElM and DFM faults are detected through
CRC checks in the LIUs at the exchange, ElMs, SIUs and customer
30 equipment. Once a failure has been isolated to the F~TC system as
described above, BER tests from the Icnown good (3CM (due to
redundant GCM output comparison) on the failed time slots isolate the
failure using loop backs at FRU interfaces (see FIG 3).
:. . , : . ,~
; ~ : ' ' ' ,
'. ' ' ' '' . : '.' .. ' . . ' . .
RYN042-PCI 210 ~ ~ 7 ~
For POTS, the ElMs loop back unused time slots toward the
GCM, in their LIUs just before CRC checksums and coding are added.
The GCM performs BER tests in the background on the unused time
slots through each LIU on the ElMs to detect ElM errors up to the
LIUs. With a known good GCM, a BER test failure indicates an ElM
failure, and no further isolation is needed. The CRC checksums and
line coding on ~e 2048 Kbps lines are checked in the LIUs in the
exchange and the ElMs, detecting failures of the LIUs or exchange
feeders1 which are isolated using loop backs close to ~e line interfaces
of the LIUs.
Again for POTS, coding is added and checked on data between
, the GCM and SIUs. Failures in the DFMs will result in coding errors,
which are isolated by taking advantage of the shared optical architecture,
of the FTrC system. Coding errors on a single SIU's data indicate an
SIU failure, whereas coding errors on multiple SIUs indicate a DFM or
fiber failure, which is fur~er isolated to the DFM or fiber with good
confidence using loop backs on the DFM.
All processors are non-service affecting, eliminating the need for
redundant processors and associated hardware cost and firmware
complexity. Failures of the CPM or embedded controllers in other
boards or their firmware are detected (and isolated) by watchdog timers
, and periodic polling by the CPM.
2s
The SIU comprises a Fiber Tnterface Unit 21 (FIU) and Line
i Cards 22 for various services, as shown in FIG 4. The SIU backplane
again has no active components to minimize the chance of ~leld failures.
For digital services, FIU and Line Card faults are detected
through CRC checks in the LIUs at the exchange, ElMs~ SIUs and
customer equipment. Once a failure has been isolated ~o the FTTC
system as described above, ~3ER tests from the OIU on the failed time
, slots isolate the failure using loop backs at T:RIJ interfaces.
3s
- ~ ~ . "
.
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Page 10 210817~
For POTS, coding is checked on data between the GCM and SIUs.
Failures in an SIU FIU or POTS Line Card's digital path will result in
coding errors, which can be isolated to the SIU as described above. SIU
errors can be further isolated to the FIU or Line Card using BE~R tests
5 from the OIU and loop backs at the Line Card/E~U interface.
Sophisticated self tests of POTS Line Card analog circui~y, and analog
loop tests preferably are implemented in the SIU, and are performed on
demand through the O~M system.
Though the invention has been described by reference to a filber-
to-the-curb system whereby subscribers are connected to SIUs, the
invention is not dependent on any particular distribution architecture or
topology, e.g. bus, star, PON, etc. Also, the invention, described by
reference to an El transmission format, is not to be limited to only this
15 format and applies to any forrnat, i.e., T1. Accordingly, the invention
is not to be limited by reference to any particular preferred
embodirnent described, rather it should only be limited by the appended
clairns.
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