Note: Descriptions are shown in the official language in which they were submitted.
~ 2122637
PLL FREQUENCY ~Nl~SIZER CAPABLE OF CHANGING
AN OUTPUT FREQUENCY AT A HIGH SPEED
Backqround of the Invention:
This is a divisional application of CA~A~ ian
Application No. 2,053,748 filed October 18, 1991.
This invention relates to a frequency synthesizer
with a phase-locked loop (PLL). Such a frequency synthesizer
is called a PLL frequency synthesizer.
As well known in the art, the PLL frequency
synthesizer comprises a reference signal generator, a voltage
controlled oscillator, a variable frequency divider, a phase-
frequency comparator, and a control voltage supplying circuit.The reference signal generator generates a reference signal
with a reference frequency. Responsive to a control voltage
signal, the voltage controlled oscillator generates a voltage
controlled signal having a controllable oscillating frequency.
The PLL frequency synthesizer produces the voltage controlled
signal as an o~u~ signal. Therefore, the ou~u~ signal has
an ~u~uL frequency equal to the co--~Lollable oscillating
frequency. The
~ 2~22637
output signal is supplied to the variable frequency
divider. The variable frequency divider is also supplied
with a designated dividing number D which defines the
output frequency, where D represënts a positive integer.
S The variable frequency divider frequency divides the
output signal on the basis of the designated dividing
number D to produce a divided signal. In other words,
the variable frequency divider is for frequency dividing
the output signal by a factor l/D. The phase-frequency
comparator is supplied with the reference signal and the
divided signal. The phase-frequency comparator detects a
phase-frequency difference between the reference signal
and the divided signal to produce a phase-frequency
difference signal indicative of the phase-frequency
difference. In other words, the phase-frequency
difference signal indicates one of lag and lead phases
which the divided signal has in comparison with the
reference signal. Responsive to the phase-frequency
difference signal, the control voltage supplying circuit
supplies the control voltage signal to the voltage
controlled oscillator.
More specifically, the control voltage
supplying circuit comprises a current f low control
circuit and a loop filter. Responsive to the
phase-frequency dlfference signal, the current flow
control circuit controls f low-in and flow-out of current
supplied therefrom/to to produce a current flow control
signal. The current flow control signal indicates the
~ 2122637
flow-out of the current when the phase-frequency
difference signal indicates the lag phase. The current
flow control signal indicates the flow-in of the current
when the phase-frequency difference signal indicates the
lead phase. Supplied with the current flow control
signal, the loop filter filters the current flow control
signal into a filtered signal as the control voltage
signal. More particularly, the loop filter comprises a
filter capacitor which is selectively charged and
discharged when the current flow control signal indicates
the flow-out and the flow-in of the current,
respectively.
In a conventional PLL frequency synthesizer,
changing of the output frequency is carried out by
changing step by step the designated dividing number D.
Therefore, the PLL frequency synthesizer has a variable
delay amount on changing the output frequency. As a
result, a frequency error of the output frequency occurs
in the PLL frequency synthesizer on changing the output
frequency. Accordingly, the conventional PLL frequency
synthesizer is defective in that it is impossible to
change the output frequency at a high speed.
Summary of the Invention:
It is therefore an object of the present
invention to provide a PLL frequency synthesizer which is
capable of changing an output frequency at a high speed.
Other objects of this invention will become
clear as the description proceeds.
~-- ?1 ~3~
According to an aspect of this invention, a frequency
synthesizer comprises a reference signal generator for genera-
ting a reference eignal with a reference frequency, a voltage-
controlled oscillator responsive to a control voltage signal
for generating an output signal having an output frequency, a
variable-frequency divider supplied with the output signal and
responsive to a designated dividing number defining the output
frequency for frequency dividing the output signal on the basis
of the designated dividing nu~ber to produce a divided signal,
a phase-frequency comparator supplied with the reference signal
and the divided signal for detecting a phase-frequency differ-
ence between the reference signal and the divided ~ignal to
produce a phase-frequency difference signal indicating one of
lag and lead phases which the divided signal has in comparison
with the reference signal. A current flow control circuit is
responsive to the phase-frequency difference signal for con-
trolling flow-in and flow-out of current supplied therefrom/to
to produce a current flow control signal. The current flow
control circuit consists of a first transistor means and a
second transistor means, each having a control node controlling
current flow between a current inflow node and a current out-
flow node. The current outflow node of the first transistor
means is connected to the current inflow node of the second
transistor means at a connection point. The current flow con-
trol signal is obtA; neA from that connection point. The lag
phase signal is supplied to the control node of the first
transistor means, and the lead phase signal is supplied to the
control node of the second transistor means. The frequency
synthe~izer also has a loop filter and a current controlling
circuit. The loop filter is supplied with the current flow
control signal for filtering the current flow control signal
into a filtered signal as the control voltage signal. The
current controlling circuit is responsive to a current command
for controlling the current ~upplied from or to the current
flow control circuit. The current command compriees charge-up
and discharge indication signal~. The charge-up indication
~~
,P~
4a 2 1 2 2 6 3 7
signal i8 supplied to a charge-up subcircuit of the current
controlling circuit, and the discharge indication signal i8
supplied to a discharge subcircuit of the current controlling
circuit. The charge-up subcircuit includes a charge-up output
transistor means having a control node under the control of the
charge-up indication signal to control current flow between a
current inflow node connected to a positive source voltage and
a current outflow node connected to the current inflow node of
the first transistor means. The discharge subcircuit includes
a discharge output transistor means having a control node under
the control of the discharge indication ~ignal to control cur-
rent flow between a current inflow node connected~to the cur-
rent outflow node of the second transistor means and a current
outflow node connected to ground.
The current command may be present during a frequency
change, and the current controlling circuit controls the cur-
rent 80 as to increase the current when the current command is
present and to gradually decrease the current when the current
command is no longer present.
Brief Descri~tion of the Drawinqs
Figure 1 is a block diagram of a conventional PLL
frequency synthesizer;
Figure 2 is a block diagram of a PLL frequency
synthesizer according to a first embodiment of the instant
invention;
Figure 3 is a block diagram of a pulse-removing
circuit for use in the PLL frequency synthesizer illustrated
in Figure 2;
Figures 4(a) through (e) collectively show a time
chart for use in describing operation of the pulse-removing
circuit illustrated in Figure 3;
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~1
Fig. 5 is a block diagram of a PLL frequency
synthesizer according to a second embodiment of the
instant invention;
Fig. 6 is a block diagram of a charge pump
S circuit for use in the PLL frequency synthesizer
illustrated in Fig. 5;
Fig. 7 is a block diagram of a charge-up
control circuit of a current controlling circuit for use
in the PLL frequency synthesizer illustrated in Fig. 5;
1~ Figs. 8(a) through (c) collectively shGw a time
chart for use in describing operation of the charge-up
control circuit illustrated in Fig. 7;
Fig. 9 is a block diagram of a PLL frequency
synthesizer according to a third embodiment of the
instant invention;
Fig. 10 shows a time chart for use in
describing operation of a charge pump circuit of the PLL
frequency synthesizer illustrated in Fig. 9;
Fig. 11 is a block diagram of a PLL frequency
synthesizer according to a fourth embodiment of the
instant invention;
Fig. 12 shows a time chart for use in
describing operation of the PLL frequency synthesizer
illustrated in Figs. 1 and 11;
Fig. 13 is a block diagram of a PLL frequency
synthesizer according to a fifth embodiment of the
instant invention; and
~I226~7
Fig. 14 shows a block diagram of a PLL
frequency synthesizer which modifies the PLL frequency
synthesizer illustrated in Fig. 12.
Description of the Preferred Embodiments:
S Referring to Fig. 1, a conventional PLL
frequency synthesizer will be described at first in order
to facilitate an understanding of the present invention.
The PLL frequency synthesizer comprises a
reference signal generator 21, a voltage controlled
oscillator 22, a variable frequency divider 23, a
phase-frequency comparator 24, a charge pump circuit 25,
and a loop filter 26.
The reference signal generator 21 generates a
reference signal with a reference frequency. The voltage
controlled oscillator 22 is supplied with a control
voltage signal in the manner which will become clear as
the description proceeds. Responsive to the control
voltage signal, the voltage controlled oscillator 22
generates a voltage controlled signal having a
controllable oscillating frequency. The PLL frequency
synthesizer produces the voltage controlled signal as an
output signal. Therefore, the output signal has an
output frequency equal to the controllable oscillating
frequency.
The output signal is supplied to the variable
frequency divider 23. The variable frequency divider 23
is also supplied with a designated dividing number D
which defines the output frequency, where D represents a
21~2637
l,
positive integer. The variable frequency divider 23
frequency divides the output signal on the basis of the
designated dividing number D to produce a divided signal.
In other words, the variable frequency divider 23 is for
frequency dividing the output signal by a factor l/D.
The phase-frequency comparator 24 is supplied with the
reference signal and the divided signal. The
phase-frequency comparator 24 detects a phase-frequency
difference between the reference signal and the divided
signal to produce a phase-frequency difference signal
indicative of the phase-frequency difference. In other
words, the phase-frequency difference signal indicates
one of lag and lead phases which the divided signal has
in comparison with the reference signal.
The phase-frequency difference signal is
supplied with the charge pump circuit 25. The charge
pump circuit 25 acts as a current flow control circuit
which is for controlling flow-in and flow-out of current
supplied therefrom/to to produce a current flow control
signal. The current flow control signal indicates the
flow-out of the current when the phase-frequency
difference signal indicates the lag phase. The current
flow control signal indicates the flow-in of the current
when the phase-frequency difference signal indicates the
lead phase. The current flow control signal is supplied
with the loop filter 26. The loop filter filters the
current flow control signal into a filtered signal as the
control voltage signal. More particularly, the loop
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filter 26 comprises a filter capacitor (not shown) which
is selectively charged and discharged when the current
flow control signal indicates the flow-out and the
flow-in of the current, respectively. At any rate, a
S combination of the charge pump circuit 25 and the loop
filter 26 serves as a control voltage supplying circuit
for supplying the control voltage signal to the voltage
controlled oscillator in response to the phase-frequency
difference signal.
As apparent from the above description, the PLL
frequency synthesizer produces the output signal having
the output frequency which is equal to D times as large
as the reference frequency of the reference signal. It
is therefore possible to change the output frequency by
lS changing the designated dividing number D. In the
conventional PLL frequency synthesizer, changing of the
output frequency is carried out by changing step by step
the designated dividing number D. As a result, the
conventional PLL frequency synthesizer is defective in
that it is impossible to change the output frequency at a
high speed, as mentioned in the preamble of the instant
specification.
Referring to Fig. 2, the description will
proceed to a PLL frequency synthesizer according to a
first embodiment of this invention. The PLL frequency
synthesizer is similar in structure and operation to the
conventional PLL frequency synthesizer illustrated in
Fig. 1 except that the PLL frequency synthesizer further
21Z26'3~
~, g
comprises first and second pulse removing circuits 31 and
32.
The first pulse removing circuit 31 is
connected between the reference signal generator 21 and
the phase-frequency comparator 24. The second pulse
removing circuit 32 is connected between the variable
frequency divider 23 and the phase-frequency comparator
24.
The first pulse removing circuit 31 is supplied
with the reference signal from the reference signal
generator 21 and first removing data Al indicative of a
first pulse number. Responsive to the first removing
data Al, the first pulse removing circuit 31 removes
pulses from the reference signal that are equal in number
to the first pulse number for a first predetermined cycle
to produce a first pulse removed signal. Instead of the
reference signal, the first pulse removed signal is
supplied to the phase-frequency comparator 24.
The second pulse removing circuit 32 is
supplied with the divided signal from the variable
frequency divider 23 and second removing data A2
indicative of a second pulse number. The second pulse
removing circuit 32 removes pulses from the divided
signal that are equal in number to the second pulse
number for a second predetermined cycle to produce a
second pulse removed signal. Instead of the divided
signal, the second pulse removed signal is supplied to
the phase-frequency comparator 24.
212263~
Therefore, the phase-frequency comparator 24
detects a phase-frequency difference between the first
and the second pulse removed signals to produce a
phase-frequency difference signal indicative of the
phase-frequency difference.
Turning to Fig. 3, the first pulse removing
circuit 31 comprises a first inverter 311, a first
counter 312, and a first AND gate 313. The first
inverter 311 is supplied with the reference signal from
the reference signal generator 21 (Fig. 2) as a first
input pulse signal. The first inverter 311 inverts the
first input pulse signal to produce a first inverted
pulse signal. The first inverter 311 is connected to the
first counter 312 which is supplied with the first pulse
removing data. The first counter 312 counts up a first
count in synchronism with the first inverted pulse
signal. The first counter 312 produces a first time-up
signal when the first count increases up to the first
pulse number. The first time-up signal is supplied to
the first AND gate 313 which is supplied with the first
input pulse signal. Responsive to the first input pulse
signal and the first time-up signal, the first AND gate
313 produces a first AND'ed signal as the first pulse
removed signal.
Similarly, the second pulse removing circuit 32
comprises a second inverter 321, a second counter 322,
and a second AND gate 323. The second inverter 321 is
supplied with the divided signal from the variable
~_ 21 2~37
11
frequency divider 23 (Fig. 2) as a second input pulse
signal. The second inverter 321 inverts the second input
pulse signal to produce a second inverted pulse signal.
The second inverter 321 is connected to the second
counter 322 which is supplied with the second pulse
removing data. The second counter 322 counts up a second
count in synchronism with the second inverted pulse
signal. The second counter 322 produces a second time-up
signal when the second count increases up to the second
pulse number. The second time-up signal is supplied to
the second AND gate 323 which is supplied with the second
input pulse signal. Responsive to the second input pulse
signal and the second time-up signal, the second AND gate
323 produces a second AND'ed signal as the second pulse
removed signal.
Turning to Figs. 4~a) through (e), description
will be made as regards operation of the first pulse
removing circuit 31. The first input pulse signal is
depicted along Fig. 4(a). The first input pulse signal
is inverted by the first inverter 311 into the first
inverted pulse signal as shown in Fig. 4(b). The first
inverter 311 has an inverting delay time denoted to dl.
It will be assumed that the first counter 312
is supplied with the first pulse removing data indicative
of the first pulse number equal to four. In this event,
the first counter 312 counts up the first count at a
leading edge of each pulse in the first inverted pulse
signal. The first counter 312 produces the first time-up
12 21 22637
signal of a logical "1" level when the first count
increases up to the first pulse number, namely, four, as
shown in Fig. 4(c). The first counter 312 is reset to
produce the first time-up signal of a logical "0" level
in response to another leading edge of the next
succeeding pulse of the first inverted pulse signal. The
first counter 312 has a counting delay time denoted to
d2. Under the circumstances, the first AND gate 313
produces the first AND'ed signal as the first pulse
removed signal as shown in Fig. 4(d). That is, the first
AND gate 313 produces the first pulse ren~oved signal
having pulses which is one-fifth as large as those of the
- first input pulse signal. In other words, the first
pulse removing circuit 31 removes four pulses from the
reference signal for the first predetermined cycle which
has five pulses. The first AND gate 313 has a gate delay
time denoted to d3.
If the first pulse removing data indicates the
first pulse number equal to zero, the first counter 312
continuously produces the first time-up signal with the
logical "1~ level. In this event, the first AND gate 313
produces the first pulse removed signal to which the
first input pulse signal is delayed for the gate delay
time t3 by the first AND gate 313 as shown in Fig. 4(e).
Operation of the second pulse removing circuit
32 is similar to that of the first pulse removing circuit
31 and the description thereof is therefore omitted.
Referring to Fig. 5, the description will
2~22~637
13
proceed to a PLL frequency synthesizer according to a
second embodiment of this invention. The PLL frequency
synthesizer is similar in structure and operation to the
conventional PLL frequency synthesizer illustrated in
Fig. 1 except that the PLL frequency synthesizer further
comprises a current controlling circuit 35.
The current controlling circuit 35 is connected
to the charge pump circuit 25 and is supplied with a
current command C. Responsive to the current command C,
the current controlling circuit 35 controls the current
for the charge pump circuit 25. More specifically, the
current command C is present while the output frequency
is changed. The current controlling circuit 35 controls
the current so as to increase the current when the
current command C is present and then to gradually
decrease the current aft~r the current command C becomes
absent. A little more in detail, the current controlling
circuit 35 comprises a charge-up control circuit and a
discharge control circuit.
Turning to Fig. 6, the charge pump circuit 25
comprises a complementary-symmetry metal-oxide-
semiconductor field-effect transistor (CMOSFET) which
consists of a p-channel MOSFET 36 and an n-channel MOSFET
37. Each of the MOSFETs 36 and 37 has a gate terminal, a
drain terminal, and a source terminal. The p-channel and
the n-channel MOSFETs 36 and 37 are joined at their drain
terminals which are connected to the loop filter 26 (Fig.
5). The p-channel MOSFET 36 has the source terminal
212Z637
14
which is connected to the charge-up control circuit of
the current controlling circuit 35. The n-channel MOSFET
37 has the source terminal which is connected to the
discharge control circuit of the current controlling
circuit 35. Both of the p-channel and the n-channel
MOSFETs 36 and 37 have the gate terminals which are
connected to the phase-frequency comparator 24 (Fig. 5).
More particularly, the phase-frequency difference signal
comprises lag and lead phase signals which indicate the
lag and the lead phases, respectively. The lag phase
signal is supplied to the gate terminal of the p-channel
MOSFET 36. The lead phase signal is supplied to the gate
terminal of the n-channel MOSFET 37.
Supplied with the lag phase signal, the
lS p-channel MOSFET 36 is put into an ON state, thereby the
current flows from the charge-up control circuit to the
loop filter 26 through the p-channel MOSFET 36. Supplied
with the lead phase signal, the n-channel MOSFET 37 is
put into an ON state, thereby the current flows from the
loop filter 26 to the discharge control circuit through
the n-channel MOSFET 37.
Turning to Fig. 7, the charge-up control
circuit of the current controlling circuit 36 comprises a
switching element 41, an operational amplifier 42, an
n-channel MOSFET 43, first and second p-channel MOSFETs
44 and 45, first through third resistors 46, 47, and 48,
and a capacitor 49. The operational amplifier 42 has an
inverting input terminal, a noninverting input terminal,
21226~7
and an amplifier output terminal.
The switching element 41 has a control input
terminal supplied with the current command C. The
switching element 41 is supplied with a positive source
voltage +VDD. The switching element 41 is connected to
the noninverting input terminal of the operational
amplifier 42. When the current command C is present or
has a logic one value, the switching element 41 turns on,
thereby the positive source voltage +VDD is supplied to
the noninverting input terminal of the operational
amplifier 42. The inverting input terminal of the
operational amplifier 42 is an end of the first resistor
46 which has another end grounded. The noninverting
input terminal of the operational amplifier 42 is
connected to an end of the second resistor 47 which has
another end grounded. The second resistor 47 is
connected to the capacitor 49 in parallel. The
noninverting input terminal of the operational amplifier
42 is also connected to an end of the third resistor 47
which has another end supplied with the positive source
voltage ~VDD. The amplifier output terminal of the
operational amplifier 42 is connected to the gate
terminal of the n-channel MOSFET 43 which has the source
terminal connected to the inverting input terminal of the
operational amplifier 42.
The n-channel MOSFET 43 has the drain terminal
which is connected to the drain terminal of the first
p-channel MOSFET 44. The drain terminal of the n-channel
2~2fi~
~~ 16
MOSFET 43 is also connected to the gate terminals of the
first and the second p-channel MOSFETs 44 and 45. Both
of the first and the second p-channel MOSFETs 44 and 45
have the source terminals which are supplied with the
positive source voltage +VDD. The second p-channel
MOSFET 45 has the drain terminal which is connected to
the source terminal of the p-channel MOSFET 36 (Fig. 6).
Therefore, a combination of the first and the second
p-channel MOSFETs 44 and 45 composes a current Miller
circuit. The second p-channel MOSFET 45 has a gate width
which is N times as large as that of the first p-channel
MOSFET 44, where N represents a prede~ermined number.
When a first drain current Dl flows through the n-channel
MOSFET 43, through the second p-channel MOSFET 45 flows a
second drain current D2 which is N times as large as the
first drain current Dl.
Turning to Figs. 8(a) through (c), description
will be made as regards operation of the charge-up
control circuit of the current controlling circuit 36
illustrated in Fig. 7. It will be assumed that the first
through the third resistors 46 to 48 have first through
third resistance values, respectively, which are denoted
to R46, R47, and R48. The third resistance value R48 is
larger than the second resistance value R47. Figs. 8(a)
through (c) show the current command C, and the first and
the second drain currents Dl and D2, respectively.
When the current command C is present or
becomes the logic one value at a time instant to~ the
2122~37
17
switching element 41 turns on. Therefore, the capacitor
49 is charged up to a voltage of VDD. Through the
n-channel MOSFET 43 flows the first drain current Dl
which has a current value of VDD/R46. Therefore, through
the second p-channel MOSFET 45 flows the second drain
current D2 which has a current value of N x VDD/R46.
When the current command C becomes absent or
the logic zero value at a time instant tl, the switching
element 41 turns off. Therefore, the capacitor 49 is
exponentially discharged up to a voltage of R47/(R47 +
R48)) x VDD. As a result, the first drain current D
exponentially decreases up to a current value of
47/( 47 R48)) x VDD/R46. AccordinglY, the second
drain current D2 exponentially decreases up to a current
value of N x (R47/(R47 + R48)) x VDD/R46
The discharge control circuit of the current
controlling circuit 35 is similar in structure and
operation to the charge-up control circuit illustrated in
Fig. 7 except that the n-channel MOSFET 43 is replaced
with a p-channel MOSFET, the p-channel MOSFETs 44 and 45
are replaced with n-channel MOSFETs, and the positive
source voltage +VDD and the ground are exchanged each
other.
Referring to Fig. 9, the description will
proceed to a PLL frequency synthesizer according to a
third embodiment of this invention. The PLL frequency
synthesizer is similar in structure and operation to the
conventional PLL frequency synthesizer illustrated in
~12~637
~' 18
Fig. 1 except that the charge pump circuit is modified
from that illustrated in Fig. 1 as will later become
clear. The charge pump circuit is therefore depicted at
25a.
S The illustrated charge pump circuit 25a
comprises a control circuit 51, a constant current
circuit 52, an integrating circuit 53, and a sample and
hold circuit 54.
The control circuit 51 is connected to the
phase-frequency comparator 24. Responsive to the
phase-frequency difference signal, the control circuit 51
produces first through third control signals. The first
through the third control signals are supplied to the
constant current circuit 52, the integrating circuit 53,
and the sample and hold circuit 54, respectively.
Responsive to the first control signal, the
constant current circuit 52 produces a constant current.
The constant current is supplied to the integrating
circuit 53. The integrating circuit 53 has an initial
voltage. The integrating circuit 53 integrates the
constant current to an integrated voltage. The
integrating circuit 53 is reset from the integrated
voltage to the initial voltage in response to the second
control signal. The integrated voltage is supplied to
the sample and hold circuit 54. Responsive to the third
control signal, the sample and hold circuit 44 samples
the integrated voltage to hold a sampled voltage as a
held signal. The sample and hold circuit 44 supplies the
2~2~37
-
19
held signal to the loop filter 26 as the current flow
control signal.
Referring to Fig. 10 in addition to Fig. 9,
description will be made as regards operation of the
charge pump circuit 25a. In Fig. 10, the lag phase
signal, the constant current, the integrated voltage, and
the held signal are depicted along first through fourth
lines.
As shown in the first line in Fig. 10, the lag
phase signal is supplied from the phase-frequency
comparator 24 to the control circuit 51 during a first
time duration between a first time instant tl and a
second time instant t2. Under the circumstances, the
control circuit 51 produces the first control signal
during a second time duration between the first time
instant tl and a third time instant t3. Responsive to
the first control signal, the constant current circuit 52
produces the constant current during the second time
duration as shown in the second line in Fig. 10.
Therefore, the integrating circuit 53 integrates the
constant current to the integrated voltage during the
second time duration as shown in the third line in Fig.
10. After the third time instant t3, the integrating
circuit 53 keeps the integrated voltage. At a fourth
time instant t4, the control circuit 51 produces the
third control signal. Responsive to the third control
signal, the sample and hold circuit 44 samples the
integrated voltage to hold a sampled voltage as a held
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signal at a fifth time instant t5. The held signal is
supplied to the loop filter 26 as the current flow
control signal. At a sixth time instant t6, the control
circuit 51 produces the second control signal.
Responsive to the second control signal, the integrating
circuit 53 is reset from the integrated voltage to the
initial voltage. Therefore, the charge pump circuit 25a
increases a level of the current flow control signal in
response to the lag phase signal. In the similar
operation, the charge pump circuit 25a decreases the
level of the current flow control signal in response to
the lead phase signal.
It is understood that it is possible to set a
desired value to a gain of the charge pump circuit 25a by
changing the ratio of the first time duration to the
second time duration.
Referring to Fig. 11, the description will
proceed to a PLL frequency synthesizer according to a
fourth embodiment of this invention. The PLL frequency
synthesizer is similar in structure and operation to the
conventional PLL frequency synthesizer illustrated in
Fig. 1 except that the PLL frequency synthesizer further
comprises a control circuit 60.
The control circuit 60 is connected between the
phase-frequency comparator 24 and the charge pump circuit
25. The control circuit 60 is supplied with a control
enable signal CE. Responsive to the control enable
signal CE, the control circuit 60 acts as a modifying
21226~7
~,
21
arrangement for modifying the phase-frequency difference
signal into a modified signal. Instead of the
phase-frequency difference signal, the modified signal is
supplied to the charge pump circuit 25. Therefore, the
S charge pump circuit 25 controls, in response to the
modified signal, flow-in and flow-out of the current
supplied therefrom/to to produce the current flow control
signal. A little more in detail, the control circuit 60
is operable in one of a first mode and a second mode. At
first, the first mode will be described. The second mode
will be described later in the following.
In the first mode, the control enable signal CE
is present while the output frequency is changed. The
phase-frequency difference signal comprises a pulse
sequence having pulses for a predetermined cycle that are
equal in number to a controllable number. When the
control enable signal CE is present, the control circuit
60 gradually decreases the controllable number until at
last a predetermined final number. The predetermined
final number is, for example, one sixty-fourths as large
as the controllable number before being dec~eased.
Fig. 12 shows transient responses of the output
frequency in the conventional PLL frequency synthesizer
(Fig. 1) and the PLL frequency synthesizer according to
the fourth embodiment. In Fig. 12, a transient response
for the conventional PLL frequency synthesizer is
depicted at a solid line. Another transient response for
the PLL frequency synthesizer according to the fourth
2122637
22
embodiment is depicted at a dotted line. As apparent
from Fig. 12, it is possible to raise up the transient
response by decreasing the controllable number.
In the second mode, the control enable signal
CE is present in a steady state of the PLL frequency
synthesizer. The phase-frequency difference signal
comprises a pulse sequence having pulses each of which
has a controllable pulse width. The control circuit 60
narrows the controllable pulse width when the control
enable signal CE is present. It is possible to improve
unstableness in the PLL frequency synthesizer.
Referring to Fig. 13, the description will
proceed to a PLL frequency synthesizer according to a
fifth embodiment of this invention. The PLL frequency
synthesizer is similar in structure and operation to the
conventional PLL frequency synthesizer except that the
PLL frequency synthesizer further comprises a switch 65,
a reset circuit 66, a control circuit 70, and a
digital-analog converter 71.
The control circuit 70 is supplied with the
designated dividing number D, the divided signal, the
phase-frequency difference signal. On changing the
output frequency, the control circuit 70 produces first
and second control signals. The control circuit 70 also
produces voltage data on changing the output frequency.
The voltage data represents a control voltage which is
defined by the designated dividing number D on the basis
of the phase-frequency difference signal. The control
Zl-2~ 6 37
23
circuit 70 determines the voltage data by carrying out
binary search on the phase-frequency difference signal.
The switch 65 is inserted between the loop
filter 26 and the voltage controlled oscillator 22. The
switch 65 is supplied with the first control signal. The
switch 65 switches off in response to the first control
signal.
The loop filter 26 comprises first and second
resistors 261 and 262 and a filter capacitor 263. The
first resistor 261 has one end connected to the charge
pump circuit 25 and has another end connected to the
switch 65 and to one end of the second resistor. The
second resistor 262 has another end connected to one end
of the filter capacitor 263 which has another end
grounded.
The digital-analog converter 71 is supplied
with the voltage data from the control circuit 70. The
digital-analog converter 71 is activated only when the
output frequency is changed. The digital-analog
converter 71 converts the voltage data into the control
voltage. The control voltage is supplied to the voltage
controlled oscillator 22 and the filter capacitor 263 of
the loop filter 26.
Responsive to the second control signal, the
charge pump circuit 25 is unactivated or put into a high
impedance state.
The reset circuit 66 is inserted between the
reference signal generator 29 and the phase-frequency
2L226~7
24
comparator 24. On the basis of the divided signal, the
control circuit 70 controls the reset circuit 66 so as to
make the reset circuit 66 produce a reset signal which
has a phase equal to that of the divided signal. The
reset signal is supplied to the phase-frequency
comparator 24 instead of the reference signal.
In the PLL frequency synthesizer illustrated in
Fig. 13, the digital-analog converter 71 supplies the
control voltage to both of the voltage controlled
oscillator 22 and the filter capacitor 263 of the loop
filter 26. The digital-analog converter 71 may be
modified into first and second digital-analog converters
71 and 72 as shown in Fig. 14. Under the circumstances,
the first digital-analog converter 71 supplies the
control voltage to the voltage controlled oscillator 22.
The second digital-analog converter 72 supplies the
control voltage to the filter capacitor 263 of the loop
filter 26.
