Note: Descriptions are shown in the official language in which they were submitted.
~ WO95130316 21 ~91 5~ "
MULTIPLE SUBCHANNEL FLEXIBLE PROTOCOL
METHOD AND APPARATUS
Techn~cal Field
This invention relates generally to the field of
communication systems and protocols and in particular, to a
cornmunication system and protocol that ,~ " resources
within multiple s~L,cl,allnels.
1 5 Background
There are many data communications systems in operation
today which provide message distribution to data communication
receivers, such as pagers. Many of these systems utilize
signaling protocols which utilize time slots, or t,d,-~",;ssion
20 frames, to which the pagers are assigned, thereby providing
battery saving functions and other ~ri.,iellCies during the normal
course of message transmission. A paging terminal was provided
in such systems to encode the received messages for
Lldrl~lllis~io,~ to the intended pagers during the assigned
25 ~a"s"~ ioll frames. In signaling protocols such as the POCSAG
signaling protocol, each time slot, or I,d,1s",i~ n frame, allowed
for the ~Idlls,,,i~siull of only two code words, either both address
code words, an address and a message code word, or two
message code words. Since the Ildl~Slllissioll of even a simple
3û telephone number required as a minimum two message code
words, numeric message lldlls,lli~siolls required on the average
one and one-half frames, which p~ di~"y resulted in the
inability to transmit address code words during the assigned
I,dl1s",;ssion frames, because the ~Idll~lllis~iol1 frame was filled
35 by message code words acso~ d with address code words
l,d"~",;tIed in the previous l,d,1s",is~iun frame.
W095/30316 21 8`91 5~J r~l" - "
.
The above problem was aileviated in some signaling
protocols by increasing the number of code words which could be
Lld~ d in any tldl~:,lllissio,~ frame. However, when the
number of lldl ,~",iLIdL~le code words is selected for the
5 lldlls",i~:,ion frames, such lldllSllli:~iOI~ frames often have to be
filled with idle code words when an insuflicient number of
messages have been received for l,dll~l"i:,~ion during any
particular lldll~lllissiol~ frame. Such signaling protocols were
also limited in the number of data communication receivers, or
10 pagers, which could be assigned, or operated on any given
channel, before the channel reached its maximum capacity. By
increasing the lldlls",;ssiol~ speed, additional pagers could be
added to the system, however at the expense of a significant
amount of unused channel capacity, until the system a3ain filled
15 up. Then, other systems resolved this problem (as described in
pending:,, ' r,s assigned to the present assignee hereof
and illCo"uo,dlt:d by reference herein by S~ .ld~ll,an et al.
having the Application No. 07/891,363 entitled "Data
Communication Receiver Having Variable Length Message
20 Canry-On" and by Kuznicki et al having the Application No.
07/891,503 and entitled "Data Gommunication Terminal
Providing Variable Length Message Carry-On") by providing for a
flexible system which enabled reconfiguring the amount of
ill~Ulllldliùll which can be lldi~slll ' on the channel within the
25 available lldllslllissioll frames in order to maximize message
throughput on a channel. These ~ ls describe a flexible
system which enables reconfiguring the amount of i,lfur,,,~liu,~
which can be lldlls~llill~d on a single channel within the available
l,d,)sl"i~sion frames. As the demand for greater capacity and
30 throughput increases, there still exists a need for systems that
make full use of s~-;l ,a", l~la to provide even greater throughput
and flexibility than disclosed by the ~,, ' ns by Kuznicki et al
and S.l,~.~.,d~r"all et al. referred to herein above.
35 Summary of tha l,l~nli
A communication system L,,uadcd~li,,g over a plurality of
s~u-;l ,a""elb comprises a resource controller unit having at least
W0 95/30316 ~ ~ 8 ~ 1 5 ~ "
one of the plurality of suL,L:l,al~"els serving as a control channel
for addl~ssi,lg subscribers and directing them to receive
messages or data on a set or a subset of the plurality of the
su~il,al1l1els, input means for sending messages to the resource
5 controller unit, and a selective call receiver adJ~ssable by the
resource controller unit, capable of receiving messages as
directed by the resource controller on any of the subchannels and
time slots directed by the resource controller.
In another aspect of the present invention, a method
10 for receiving and decoding selective call "~essages
~Id"~ d in the form interleaved blocks of time divided
signals on a plurality of subchannels to a plurality of
selective call receivers, comprises the steps at one of the
selective call receivers of decoding at least a first received
15 block of i~urllldliol~ COIItdillil~g address and vector
illru~ dliu~ for at least a first add~t,ssed message, at least
a portion of the first received block being a control channel.
Then, d~,'~,,ll,i,lill~ where the first addl~ssed message will
begin and the length of the first message from the address
2û and vector ill~ulllldliol~. And finally, decoding subsequent
blocks of i"~ulnldlioll on the plurality of subchannels to
decode the first addressed message, the first add~ ~sed
message being capable of residing in contiguous sections
of blocks and portions of blocks on the plurality of
25 suu~ an"els.
Brief Desclivtioll of the Draw~ngs
FIG. 1 is an electrical block diagram of a data lldll~ iO~
3û system in acculddllce with the present invention.
FIG. 2 is an electrical block diagram of a terminal for
~J~uC~SSillg and lldll~lll ,g message illru""dLiùl. in acGul~dllce
with the present invention.
FIGS. 3-5 are timing diagrams illustrating the lld~ iO
35 format of the signaling protocol utilized in acco,ddllce with the
present invention.
WO95/30316 2 ~ 89 ~ 50
FIGS. 6 and 7 are timing diagrams illustratin~ the
syrlul"urii~dlion signals utilized in acc~,dd"ce with the present
invention.
FIG. 8 is an electrical block diagram of a data
communication receiver in accu,~d"ce with the present invention.
FIG. 9 is a more detailed electrical block diagram of the
data communication receiver of FIG. 8 in accu,ddi,ce with the
present invention.
FIG. 1 û is an electrical block diagram of an allt:, 11.. h/c
1 û ~IIILJodi,,,~"l of a data communication receiver in acc~,~Id,~ce with
the present invention.
FIG. 11 is a more detailed electrical block diagram of the
data communication receiver of FIG. 1û in acc~ d,~ce with the
present invention.
FIG. 12 is an electrical block diagram of yet another
alternative ~",L,o~iii"e"l of a data communication receiver in
acco,.la,~c~ with the present invention.
FlGs. 13-17 are diagrams illustrating the message
1, ti~ s of a system in acc~, ~a"ce with the present invention.
2û
Det~ l Desc,i~.lloll of the Preferred E,~ odl,-l~n
FIG. 1 is an electrical block diagram of a data lldl~slllibsbio
system 1ûû such as a paging system in acc~,ddllce with the
preferred ~i",L,odi",e"l of the present invention In such a data
25 Lldl~blllissio,~ system 1ûO, messages originating either from a
phone as in a system providing numeric data ~Idl~blllisbiu,, or
from a message entry device such as an alphanumeric data
terminal are routed through the public switched telephone
network (PSTN) to a paging terminal 102 which processes the
3û numeric or alphanumeric message i"~u""dlion for ~Idllblllibbion
by one or more ll~llblllilL~lb 1û4 provided within the system.
When multiple ll dllbl l lil~l:71 b are utilized the Ll dl Ibl l lill~l b 104
preferably simulcast transmit the message i~ulllld~ion to data
communication receivers 106. P~ucessillg of the numeric and
35 alphanumeric illfUlllldLi~l- by the paging terminal 102 and the
protocol utilized for the ~Idl~s",ibbiol~ of the messages is described
below.
WO g5130316 2 1 8 9 l ~ ù r~ "
FIG. 2 is an electrical block diagram of the paging terminal
102 utilized for fj,u~essi"g and ~;f l l, " ,9 the ~Idnsll)ia:~iol) of the
meâsage illru~ dliol1 in acc~" dnce with the present invention.
Short messages, such as tone-only and numeric messages which
5 can be readily entered using a Touch-Tone telephone are
coupled to the paging terminal 102 through a telephone interface
202 in a manner well known in the art. Longer messages, such
as alphanumeric messages which require the use of a data entry
device are coupled to the paging terminal 102 through a modem
10 206 using any of a number of well known modem lldl~ ion
protocols. When a call to place a message is received, a
controller 204 handles the p~ucessi~g of the message. The
controller 204 is preferably a ~ u~ uterl such as an
MC68000 or equivalent, which is manufactured by Motorola Inc.,
15 and which runs various pre-programmed routines for controlling
such terminal u,ueldliull:~ as voice prompts to direct the caller to
enter the message, or the ha,~ ahi"~J protocol to enable
reception of messages from a data entry device. When a call is
received, the controller 204 ,uf~ ces ill~ulllldliul~ stored in the
2û subscriber database 208 to determine how the message being
received is to be p~uc~sed. The subscriber data base 208
includes, but is not limited to such illfUlllld~iOII as a~ es
assigned to the data communication receiver, message type
~qso~ d with the address, and i~ulllldliUn related to the status
25 of the data communication receiver, such as active or inactive for
failure to pay the bill. A data entry terminal 240 is provided which
couples to the controller 204, and which is used for such
purposes as entry, updating and deleting of i,,fu,,,,ati.,,~ stored in
the subscriber data base 208, for "~0~ u~i"~ system pe"u""anud,
30 and for obtaining such ill~u",..,:;~,n as billing ill~ dliUI1.
The subscriber database 208 also includes such
ill~UlllldliUII as to what l,d,~:,",i~sion frame and to what
- I~dl~ lissiu11 phase the data communication receiver is assigned,
as will be described in further detail below. The received
35 message is stored in an active page file 210 which stores the
messages in queue. Alternatively, the queue is provided in the
active page file 210. The active page file 210 is preferably a dual
WO95130316 2 1 8~ 1 5~ - "
port, first in first out random access memory, although it will be
~ ,ul~id~t:d that other random access memory devices, such as
hard disk drives, can be utilized as well. Periodically the
mesgage i~u~ alioll stored in each of the queue is recovered
from the active page file 210 under control of controller 204 using
timing illfUlllldli~ll such as provided by a real time clock 214, or
other suitable timing source. The recovered message il ,ful l l Id
from the queue is sorted by frame number and is then organized
by address, message ill~UIII.~ l, and any other illfulll - 1
required for ildilsll~is~iull~ and then batched into frames based
upon message size by frame batching controller 212. The
batched frame illfUlllldlioll is coupled to frame message buffers
216 which ltnlluul~lily store the batched frame ill~u,l,ldlion until a
time for further ~JIucessi~ ,9 and lldl~5111issioll. Frames are batched
in numeric sequence, so that while a current frame is being
lldll:,lllilltld~ the next frame to be lldl~s"lill~d is in the frame
message buffer 216, and the next frame thereafter is being
retrieved and batched. At the ap~lupl idlt: time, the batched frame
i"~ull"dliùn stored in the frame message buffer 216 is lldll~ d
to the frame encoder 218. The frame encoder 218 encodes the
address and message illfulllldliol~ into address and message
code words required for l,d"~,llission, as will be described below.
The encoded address and message code words are ordered into
blocks and then coupled to a block interleaver 220 which
interleaves preferably eight code words at a time for Lldllsll,is:,i
in a manner well known in the art. The interleaved code words
from each block interleaver 220 are then serially lldll~ d on a
bit by bit basis into a serial data stream by lldll:,lllissio,l phase.
Optionally, if multiple phases are used, then the interleaved code
words form each block interleaver 220 are then serially
lldll~ d to a phase multiplexer 221 (shown in ghost lines),
which multiplexes the message ill~ulllldliull on a bit by bit basis
into a serial data stream as before. The controller 204 next
enables a frame sync generator 222 which generates the
Syl l~l II Ulli~dliOIl code which is 1, dl~511 lill~d at t~e start of each
frame lldl,~",i~iun. The s~l,.;l"u"i~dliol~ code is multiplexed with
address and message ill~ulllldLioll under the control of controller
~ W095/30316 2~ ~91 ~0 P~
204 by serial data splicer 224, and generates therefrom a
message stream which is properly formatted for l~dr,:.",issio~.
The message stream is next coupled to a Lldl~s",iLLt, controller
226, which under the control of controller 204 transmits the
5 message stream oYer a distribution channel 228. The distribution
channel 228 may be any of a number of well known distribution
channel types, such as wire line, an RF or microwave distribution
channel, or a satellite distribution link. The distributed message
stream is lld~ d to one or more L,~s",iLI~, stations 1û4,
10 depen-li"g upon the size of the communication system. The
message stream is first l.dr,~"~d into a dual port buffer 230
which l~ ord- i'y stores the message stream prior to
L.dl~s",issiol1. At an d,u~.lulJridl~ time d~L~-",;"ed by timing and
control circuit 232, the message stream is recovered from the dual
15 port buffer 230 and coupled to the input of preferably a 4
subchannel, 4-level FSK modulator 234. The modulated
message stream is then coupled to the Lldlls", " 236 for
L,dns,niss;~n via antenna 238.
FIGS. 3, 4 and 5 are timing diagrams illustrating the
20 Lldllb,n;,~;ol1 format of the signaling protocol utilized in
a~col~dllce with the preferred er"L,o.li"le"l of the present
invention. As shown in FIG. 3, the signaling protocol enables
message l,d"s",is~ion to data communication receivers, such as
pagers, assigned to one or more of 128 frames which are labeled
25 frame û through frame 127. It then will be a~ cidl~d that the
actual number of frames provided within the signaling protocol
can be greater or less than described above. The greater the
number of frames utilized, the greater the battery life that may be
provided to the data communication receivers operating within
3û the system. The fewer the number of frames utilized, the more
often messages can be queued and delivered to the data
communication receivers assigned to any particular frame,
thereby reducing the latency, or time required to deliver
messages.
3~ As shown in FIG. 4, the frames comprise a s~ l " u, li~dliUI,
code (sync) followed preferably by eleven blocks of message
ill~Ulllldliol1 which are labeled block 0 through block 10. As
WO95/30316 21 ~q 1 ~ "
shown in FIG. 5. each block of message illfUlllld~iull comprises
preferably eight address, control or data code words which are
labeled word û through word 31 for each phase. Consequently,
each phase in a frame allows the lldl-s",issi~"- of up to thirty-two
5 (32) address, control and data code words. (In the case of 4
subchannel ad.l,~si"~, each phase in a frame allows the
lldl)s",i ~iOi1 of up to 4 times 32 words or 128 address, control
and data code words. The address, control and data code words
are preferably 31,21 BCH code words with an added thirty-
10 second even parity bit which provides an extra bit of distance tothe code word set. It will be ap,u,~cidL~d that other code words,
such as a 23,12 Golay code word could be utilized as well.
Unlike the well known POCSAG signaling protocol which
provides address and data code words which utilize the flrst code
15 word bit to define tlle code word type, as either address or data,
no such distinction is provided for the address and data code
words in the signaling protocol utilized with the prefenred
embodiment of the present invention. Rather, address and data
code words are defined by their position within the individual
20 frames.
FIGS. 6 and 7 are timing diagrams illustrating the
s~,~ul"u"i~lio,~ code utilized in accu"~d"ce with the present
invention. In particular, as shown in FIG. 6, the s~n~ul~u~ liu~
code comprises preferably three parts, a first s)ll IUI IIUI~i~dliUI~
25 code (sync 1), a frame i"" Illdt;OI1 code word (frame info) and a
second sy"ul " ul1i~dliol~ code (sync 2). As shown in FIG. 7, the
first syl1ul"ulli~dLiù" code comprises first and third portions,
labeled bit sync 1 and BS1, which are alL~",dli"g 1,û bit patterns
which provides bit sy,~cl,,u,,i~lion, and second and fourth
30 portions, labeled "A" and its c~lllpl~llltllll "A bar", which provide
frame sy,,.il,,u,,i~lioll. The second and fourth portions are
preferably single 32,21 BCH code words which are p,~d~i"ed to
provide high code word c~ ldliol~ reliability, and which are also
used to indicate the data bit rate at which ad.l,~,ses and
35 messages are lldl~ lliLlt:d. The table below defines the data bit
rates which are used in conjunction with the signaling protocol.
~ WO9~130316 21 ~9 1~ ,. "
~a~ "A" Value
1600 bps A1 and A1 bar
3200 bps A2 and A2 bar
6400 bps A3 and A3 bar
5 Not defined A4 and A4 bar
As shown in the table above, three data bit rates are
~"edt,~ ed for address and message lldl~lllissio" although it will
be app, t:~idl~d that more or less data bit rates can be predefined
as well depending upon the system requirements. A fourth "A"
value is also predefined for future use.
The frame i,l~o""dt;on code word is preferably a single
32,21 BCH code word which includes within the data portion a
p,t,Ll~tt~""i"ed number of bits reserved to identify the frame
number such as 7 bits encoded to define frame number 0 to
frame number 127.
The structure of the second syl,cl"ur,i~dliù" code is
preferably similar to that of the first s~ l ,ru, li~dlio,~ code
described above. However unlike the first s~",cl"u"i~d~ code
which is preferably l,a"~",ilL~d at a fixed data symbol rate such
as 16ûû bps ~bits per second) the second s~",c~"ul,i~dlion code
is lldl Is,,,illed at the data symbol rate at which the address and
messages are to be lldl~s,,,i~l~d in any given frame.
Consequently the second sy,,.:l,,oni~dliun code allows the data
communication receiver to obtain "fine" bit and frame
s~,~.;l,,u,,i~liull attheframe lldll,lllis~iù,~ databitrate.
In summary the signaling protocol utilized in acco~ddr~ce
with an en,bo.li",e"l of the present invention comprises 128
frames which include a p,ed~L~""i"ed syl~cl~lul~i~d~ioll code
3û followed by eleven data blocks which comprise eight address,
control or message code words per phase. The syl,ul"ur,i~dlio,~
code enables ide"li~i~dliùn of the data l,d,~s,l,i~iun rate and
- insures s~ull~u~ iull by the data communication receiver with
the data code words ~Idllslllill~d at the various lldl~sllli:,siol1 rates.
- 35 The protocols described in the . " - ~s by Kuznicki et
al and S~ del"an et al. are becoming known in the paging
industry as the FLEX protocol. FLEX allows a communication
WO 95/30316
system to address and vector messages within a single channel
whereas the present invention allows a communication system to
address and vector messages to one of N other subchannels in
one ~ odi",e"l or in another ~",bo~i",e"l the communication
system allows for the ad~ s:,i"~ and vectoring of messages to up
to N s~bulldllllt:ls simultaneously where N can almost be any
integer number . The following examples for simplicity illustrate
~",~odi",~"~ where N=4 but of course the scope of the claimed
invention ~IlLt,lll~ s the ~",~oui",~"l where N can be any
integer. For future reference, an t " l~odi" ,~ :"~ where one of four
sul,ul,a",)els can be adci,t,ssed and vectored shall be called a
1 X4 system protocol or receiver and an embodiment where four
of four sul,.l,a~ , can be add,~:,sed and vectored
simultaneously shall be called a 4X4 system protocol or
1 5 receiver.
FIG. 8 is a block diagram of an ~",~o.li"~e"~ of data
communication receiver 106 in acco,ddnce with the present
invention. The receiver 106 comprises of an antenna 802
coupled to a receiver module 804 which is coupled to a controller
816 via a 1 X4 Decoder module 895 and a via synthesizer 899.
The receiver 106 ~urther includes memory 890 and input and
output devices (885 & 880) as known in the art.
FIG. 9 is a more detailed electrical block diagram of the
data communication receiver 106 shown in FIG. 8 in acco,dal1ce
with the present invention. The heart of the data communication
receiver 106 is a controller 816 which is preferably implemented
using an MC68HC11 microcomputer such as manufactured by
Motorola Inc. The~ uCO~uutercontroller,hereinaftercalled
the controller 816 receives and processes inputs from a number
of peripheral circuits as shown in FIG. 9 and controls the
operation and i~ liul l of the peripheral circuits using software
subroutines. The use of a ,,,;~ ,ucu,,,uuter controller for
plUC~ g and control functions is well known to one of ordinary
skill in the art.
The data communication receiver ~06 is capable of
receiving address control and message ill~u""~ n hereafter
called "data" whi~h is modulated using preferably 2-level and 4-
WO 95/30316 ;~ ~ 8 9 1 ~ 0 ~ "
level frequency modulation techniques. The lld~ d data is
il ltt~ ,u'~,d by an antenna 802 which couples to the input of a
receiver section 804. Receiver section 804 p,ocesses the
received data in a manner well known in the art, providing at the
5 output an analos 4-level recovered data si3nal, hereafter called a
recovered data signal. The recovered data signal is coupled to
one input of a threshold level extraction circuit 808, and to an
input of a 4-level decoder 810. The threshold level extraction
preferably comprises two clocked level detector circuits (not
10 shown) which have as inputs the recovered data signal. A level
detector could detect the peak signal amplitude value and
provide a high peak threshold signal which is ,u,upo,li~nal to the
detected peak signal amplitude value, while another level
detector detects the valley signal amplitude value and provides a
15 valley threshold signal which is p,upu,~iù,,al to the detected valley
signal amplitude value of the recovered data signal. Resistors
are then utilized to enable decoding the 4-level data signals as
will be described below
When power is initially applied to the receiver portion, as
20 when the data communication receiver is first turned on, a clock
rate is preset to select a 128X clock, i.e. a clock having a
frequency equivalent to 128 times the slowest data bit rate, which
as described above is 1600 bps. The 128X clock is generated by
128X clock generator 844, as shown in FIG. 8, which is preferably
25 a crystal controlled oscillator operating at 2û4.8 KHz (kilohertz).
The output of the 128X clock generator 844 couples to an input of
frequency divider 846 which divides the output frequency by two
to generate a 64X clock at 102.4 KHz. The 128X clock allows the
level detectors in the threshold level extraction circuit 808 to
30 asynchronously detect in a very short period of time the peak and
valley signal amplitude values, and to therefore generate the low
(Lo), average (Avg) and high (Hi) threshold output signal values
required for modulation decoding. After symbol s~ u"i~dlion
is achieved with the sy,n;l,,u,,i~dlio,l signal, the controller 816
35 generates a second control signal to enable selection of a 1X
symbol clock which is generated by symbol sy~ l"o~ r 812 as
shown in FIG. 9. 11
WO 9!i130316 2 1 ~. q l; 5 ~
The most si3nificant bit (MSB) output from the ~level
decoder 810 is coupled to an input of the symbol sy"-:l"uni~r
812 and provides a recovered data input generated by detecting
the zero crossings in the 4-level recovered data signal. The
5 symbol sy"~l"u"i~, 812 preferably uses the 64X clock at 102.4
KHz which is generated by frequency divider 846. A contrûl
signal (1600/3200) is provided to the symbol s~ l,,ur,i~r 812
and is used to select the sample clock rate for symbol
l,~"s",i~iol1 rates of 1600 and 3200 symbols per second.
10 The 1 X and 2X symbol clocks are generated with 1600 3200 and
6400 bits per second and are s~",.;l,tu"i~d with the recûvered
data signal.
The 4-level binary converter 814 uses a 1 X symbol clock
and a 2X symbol clock along with the symbol output signals
15 (MSB LSB) and a selector signal (2WL) from the controller to
select and provide control of the conversion of the symbol output
signals as either 2-level FSK data or 4-level FSK data. When the
2-level FSK data conversion (2L) is selected, only the MSB output
is selected which is coupled to the input of a parallel to serial
20 converter (not shown). When the 4-level FSK data conversion
(4L) is selected both the LSB and MSB outputs are selected
which are coupled to the inputs of the parallel to serial converter.
Returning to FIG. 8 a serial binary data stream generated
by the 4-level to binary converter 814 is coupled to inputs of a
25 syl~clllulli~d~iol1 word correlator 818 and a demultiplexer 820.
The s~ l"u~ iu,~ word correlator has plt:dtl~ d "A" word
syn~l,,u,,i~d~iun patterns that are recovered by the controller 816
from a code memory 822 and are coupled to an "A" word
correlator (not shown). When the syllul~u~ iun pattern
30 received matches one of the ul~ led "A" word
sy,~cl~ dliùn patterns within an a~cept~hle margin of error an
~A" or "A-bar" output is generated and is coupled to controller 816.
The particular "A" or "A-bar" word syl,ul,~ulli~Lion pattern
correlated provides frame sy,~cl,,ur,i~iùn to the start of the frame
35 ID word and also defines the data bit rate of the message to
follow.
12
WO 95/30316 2 1 8 ~ 1 5 ~ g! ~ "
.
The serial binary data stream is also coupled to an input of
the frame word decoder (not shown) which decodes the ftame
word and provides an indication of the frame number currently
being received by the controller 816. During sync acquisition,
5 such as following initial receiver turn-on power is supplied to the
receiver portion by battery saver circuit 848 which enables the
reception of the "A" syn~l,,,o~ dLiull word, as described above
and which continues to be supplied to enable ~uc~ssillg of the
,t""ai,~de~ of the syr,.:l"~ diiol~ code. The controller 816
10 compares the frame number currently being received with a list of
assigned frame numbers stored in code memory 822. Should the
currently received frame number differ from an assigned frame
numbers the controller 816 generates a battery saving signal
which is coupled to an input of battery saver circuit 848,
15 suspending the supply of power to the receiver portion. The
supply of power will be suspended until the next frame assigned
to the receiver, at which time a battery saver signal is generated
by the controller 816 which is coupled to the battery saving circuit
848 to enable the supply of power to the receiver portion to
20 enable reception of the assigned frame.
Returnin~q to the operation of the sy"ul~,u"i~ oll
correlator a p,t~ ""i,~ed "C" word sy"cl"o"i~atio,~ pattern is
recovered by the controller 816 from a code memory 822 and is
coupled to a "C" word correlator (not shown). When the
25 sy~ u~ lioll pattern received matches the ,u,t,d~L~""i"ed "C"
word synul"u"i~d~iu,l pattern with an ~:c~rt~hle margin of error
a "C" or "C-bar" output is generated which is coupled to controller
816. The particular "C" or "C-bar" syll, I,,u,,i~d~ion word
correlated provides "fine" frame s~,l,.;l"u"i~ ,l to the start of the
3û data portion of the frame. (See FlGs. 6 and 7).
The start of the actual data portion is e~d~li.,l ,ed by the
controller 816 ~U,t~lleld~ill9 a block start signal (Blk Start) which is
coupled to inputs of a word de-interleaver 824.
Optionally if multiple phases are used then the block start
35 si3nal is coupled to the inputs of a word de-interleaver 824 and a
data recovery timing circuit 826. The block start signal is used to
generate clocked phase signals which are s~"~cl"ur,i~t:d with the
W095/30316 21 ~91`5f) ~ "
incoming message symbols. The clocked phase signal outputs of
the phase timing generator 826 are coupled to inputs of a phase
selector 828. During operation, the controller 816 recovers from
the code memory 822, the L,dl~s",ission phase number to which
5 the data communication receiver is assigned. The phase number
is Ll dl l~tll I Hd to the phase select output (0 Select) of the
controller 816 and is coupled to an input of phase selector 828. A
phase clock, cOIltla,uùl)dilly to the Lldlls",issioll phase assigned,
is provided at the output of the phase se!ector 828 and is coupled
10 to clock inputs of the demultiplexer 820, block de-interleaver 824,
and address and data decoders 830 and 832" H~,e.";,/cly. The
demultiplexer 820 is used to select the binary bits ~cso~ d with
the assigned L,dl~s",i~ion phase which are then coupled to the
input of block de-interleaver 824, and clocked into the de-
15 interleaver array on each COII-HSPOI~djII9 phase clock.
The de-interleaver array is preferably a 32x32 bit array
which de-interleaves thirty-two interleaved address, control or
message code words, corresponding to one Lldl~slllissioll block.
The de-interleaved address code words are coupled to the input
20 of address correlator 830. The controller 816 recovers the
address patterns assigned to the data communication receiver,
and couples the patterns to a second input of the address
correlator. When any of the de-interleaved address code words
matches any of the address patterns assigned to the data
25 communication receiver within an ~-~cHrtAhle margin of error, the
message ill~UlllldLio~ o~i~lHd with the address is then
decoded by the data decoder 832 and stored in a message
memory 850 in a manner well known to one of ordinary skill in the
art. Following the storage of the message information, a sensible
30 alert signal is generated by ~he controller 816. The sensible alert
signal is preferably an audible alert signal, although it will be
".~plHci~,lHd that other sensible alert signals, such as tactile alert
signals, and visual alert signals can be generated as well. The
audible alert signal is coupled by the controller 816 to an alert
35 driver 834 which is used to drive an audible aierting device, such
as a speaker or a transducer 836. The user can override the alert
14
~ W0951303~6 ~1 ~9~ L ~ 11
sisnal ge"e,dLio,1 through the use of user input controls 838 in a
manner well known in the art.
Following the detection of an address ~4~40~ Hd with the
data communication receiver, the message information is coupled
to the input of data decoder 832 which decodes the encoded
message illfUrrl~dlioll into preferably a BCD or ASCII format
suitable for storage and subsequent display. The stored
message illfulllldliol1 can be recalled by the user using the user
input controls 838 whereupon the controller 816 recovers the
message illfUlllld~iùll from memory, and provides the message
i~ru~ dliol) to a display driver 840 for plHsH"Idliù" on a display
842, such as an LCD display.
Referring to FIG. 10, another block diagram of an
~Illbodi~ of the data communication receiver 106 in
acc~,dd"c~ with the present invention is shown. The receiver
106 comprises of an antenna 802 coupled to a receiver module
804 which is coupled to a controller 875 via a 4X4 Decoder
module 897 and a via synthesizer 899. The receiver 106 further
includes memory 890 and input and output devices (885 & 880)
as known in the art. In one embodiment of the block diagram of
FIG. 10, the receiver 106 would appear very much like the
receiver of FIG. 9, except that the front end and decoder for the
4X4 FLEX receiver can appear as the block diagram shown in
FIG. 1 1.
As before, the receiver 106 in FIG. 11 includes a receiver
module 804 having an antenna 802. The receiver is coupled to a
more sopl1i~icdldd sy"t,,esi~, 900 via a bank of mixers 310,
312, 314, and 316. The mixed signals from the bank of mixers is
provided to the 4X4 decoder module 897. The module preferably
comprises a bank of bandpass filters, detectors and decoders
along with the a,u~up~id~ a"",lili-id~iol~ as is known in the art.
Each bandpass filter (320, 322, 324 and 326 respectively) should
- be ideally designed to pass an aup,u~ ridl~ subchannel on to their
respective detectors (330, 332, 334, and 336) and their respective
- 35 decoders (340, 342, 344, and 346). The signals from the decoder
module 897 are then manipulated by the .i~r,~ ' 1ddld combiner
in much the same manner as the controller 816 of FIG. 9. Of
_, . .
WO 95/30316 2 ~ 3 ~ " ~
course, the receiver 106 includes memory 890, and user input
and output devices 885 and 880 respectively.
Referring to FIG. 12, another alternative e",L o.li",elll is
shown for the receiver 106 in FIG. 10 using a Digital Signal
5 Processor (DSP) such as the Motorola DSP56001 or its
functional equivalent. The receiver 106 of FIG. 12 preferably
includes a linear receiver 404 having an antenna 402.
Depending on the speed of the DSP, memory mana~",t",l and
other houseke~ui"g routines can be handled by the DSP.
10 Otherwise, an optional controller 408, such as the co"L" "~ ~
described in previous el"bodi",e"~. could be used. Ideally, in a
4X4 FLEX receiver, the DSP 406 will handle for four subchannels
each: threshold level extraction, level syl,.:l,,u,,i~d~i~n, level
s~ ul,,u,,i~dLiol~ COlltlldliOn, data decoding, and data combining.
15 Additionally, the DSP will also serve the functions of battery
savin~, de-multiplexing, de-interleaving, address co,,~ldLiu,,,
phase selecting, and phase timing. Optionally, some of these
tasks, and other tasks if needed, can be handled or shared by the
controller 408. Finally, as usual, the receiver 106 includes
20 memory 410, and user input and output devices 412 and 414
respectively.
FlGs. 13-17 illustrate typical timing diagrams A.~so~ d
with several e",bo~i",e"t~ in acco,dd"ce with the present
invention. FIG. 13 illustrates the timing diagram for a 1 X4 FLEX
25 receiver. The vector and addressing i"~ur",dLi~l1 will usually be
found in the in the first subchannel, desiu,,dL~d here as
subchannel #0. Subchannel #0 or a portion of subchannel #0
will also be know as the control channel or the addressing
channel. The vectoring information will usually designate what
30 type of i"~u""dLion will be received (suchas Hexideui",dl or
alphanumeric and whether the i,,~u, ",d~iun will be provided on a
single subchannel or on a multiple subchannel). The ad.l,~asi"~
ill~ulllldliùl~ will designate what particular Word Number the
message will start within the particular subchannel. In the case of
35 a multiple subchannel message, the add,_ssi"g information will
designate what particular subchannel, block, and Word to begin
providing the message. Additionally, the ad~,~s~i"g can
16
-
W0 951303~6 2 1 8 9 1 ~ "
designate corners in messages to provide further efficiency in
messaging. Some of these features will become more apparent
in the following discussions with regards to FIGS. 18-21.
Thus in FIG. 13, the vectoring and add,~s~i"g i~ulnldL
in subchannel #û directs the 1X4 Flex receiver to decode
message #1 in subchannel 2 at a particular block and word. It
should be ulld~r~tuOd that the 1X4 Flex receiver could have been
directed to decode message #1 in any one of the available (four
in this instance) sub.;l Idl 11 lel~, not just the subchannel shown. In
1û FIG. 14 the vectoring and addl~s~i,)g i,,Fu,,,,atio,~ in subchannel
#1 directs a 4X4 Flex receiver to decode the repeated message
#1 in each of the su~ al~"els at different blocks and words.
Further note as illustrated in FlGs. 13 and 14 that it is within
cu"lt:",!,ld~iùn of the present invention that the control channel
can reside on any of the sub~;lldllll~l~ (the i"~""e~ialy
subchannels and the highest or last subchannel) not just
subchannel #û (the lowest or first subchannel) as shown in FIG.
13.
In FIG. 15 the vectoring and addressing ill~Olllld~iUi~ in this
2û case directs a Flex 4X4 receiver to decode three different sized
messages (message #1 #2 and #3) at different subchannels. In
the case of message #1 the message is decoded at a later time
frame portion within subchannel #û. Message #2 is decoded in
portions of contiguous "areas" within suL,-:l,a",~ #1 and #2
while message #3 is decoded in portions of subchannel 3.
FIG. 16 is the same illustration as FIG. 15 but further
illustrating the blocks and block boundaries preferably ~.so~ Pd
with the present invention. As shown there are preferably 8
blocks within the block boundaries which are decoded at a time.
3û The addressing and vectoring ill~ dliùl1 in subchannel #û first
decoded by the 4X4 Flex receiver will direct the receiver to
decode message #1 at the beginning at block 8 of subchannel
- #û message #2 at the beginning of block 6 of subchannel #1
(and ending at block 1û of subchannel #2) and message #3 at
- 35 the beginning of block 4 of subchannel 3.
Of course the present invention maintains the flexibility
found in the embodiments of Kuznicki et al and Sclll~e.~d~",a,~ et
WO 95/30316 ;~ 5 ~ " ~
al in terms of bein3 able to send and receive messages at
variable speeds, but a~ iùl.al'y, the present invention allows the
receiver to send both 1X4 Flex messages and 4X4 Flex
messages and further pack them within a 4 subchannel format
5 that provides great efficiency as shown in FIG. 17. In this case,
the receiver is shown as decoding messages in blocks of 5,
where there are 11 blocks to a frame as previously described with
regard to FlGs. 3-7. (Please note these are not the only formats
available cu~ ,ld~t:d for use with the claimed invention.) When
10 the receiver decodes the first five biocks (probably the last block
of Frame N-1 and the first four blocks of Frame N), the receiver
decodes the vectoring and acl~,~s~i"g il~fulllldtk)l~ first, found
here in this case in the first block and portion of the second block
of the second block of Frame N of subchannel #0. The vectoring
15 illful~ would indicate that the first four messages are 1X4
messages found in a single subchannel (subchannel #0), while
the messages #5-#8 are 4X4 Flex messages decoded throughout
portions of the four s~ d,~"els.
Oue,dliol ,~I'y, a 1X4 FLEX receiver receiving message #4
20 (MSG4) as shown in FIG. 17, would decode block #0 and detect
the ~lessage'~ address from the portion 2 of the block #0 and
perhaps the ",essa~e'~ vector from portion 3. Additionally, the
receiver might decode block #1 and retrieve further vector
ill~u", - ~ from portion 3. (Portion 1 of block #0 preferably
25 contains ~lock Illfurllldlioll Words). The 1X4 FLEX receiver would
then decode blocks #2, #3 and #4 in sequence to extract its
message.
Again referring to FIG. 17, a 4X4 FLEX receiver, receiving
messages MSG5, MSG6, MSG7, and MSG8, would decode block
30 #0 and block #1 to extract the address and vectors and then
would decode the blocks from the start to end of the message
based upon the vector i"~ull"d~i,.n. This device would
demodulate and decode data from multiple su~lldllll~ls
simultaneously as required based upon the subchannels used in
35 lldll~lllissio,~ of the message.
A single device could decode all the messages in FIG. 17
in a variety of sized segments (for example, 5 blocks). The device
1 8
WO95/30316 2 ~ 8 9 ~ 50 r~
preferably has a receiver that decodes the ad~,~s~i"g and
vectoring ill~Ur",dliu,) in blocks l and 2 in subchannel #0, then the
message #3, alûng with portiûns of message #4 and portions of
message #5, then message #1 along with more portiûns ûf
message #4 and #5 and the be0inning portions of message #6,
then the remainder of message #2, with portions of message #4
and message #6 along with the remainder of message of #5. As
the next segment of blocks are decoded, the Itllldilld~l of
messages #4 and #6 are decoded, and the entire message #7 is
decoded. Additionally, a portion of message #8 is decoded.
Finally, after the next segment of blocks are decoded, the
remainder of message #8 is decoded by the receiver.
The 8 messages can be so efficiently packed together
because of the flexibility of the protocol which allows for mixing of
protocols and "corner" COIllllld~ i to make room for single
subchannel messages (pages) among multiple subchannel
messages or pages. These ~ 5 and advantages will
become further apparent in the e,~la,~dtion of the format of the 32
(or more, actually 64 in the examples to follow) bit words used for
vectoring and ad~,~ssi"g the incoming messages at a receiver
as shown in the tables below.
TABLE 1
HEX / Binary Vector (S~ngle Subcarrier)
1 2 3 4 5 6 7 .. .............. 21 .. .. 31 32
Information Parlty C3c
xO xl x2 X3 V0 Vl V2 v3 bo bl b2 b3 b4 b5 b6 b7 b8 Yo Yl mO 80 P P P P P P P P P P P
xO xl x2 X3 nO nl n2 n3 n4 nS n6 n7 ng s~ 86 85 54 83 52 sl 80 P P P P P P P P P P P
3û V - Vector Type v3v2vlvO - OllO - HEX Vector Single Subcarrier
b - Word Number of message start b3b~b6b5b4b3b2blbo (1 - 511 Decimal )
y - Subchannel assigned
m - 0 implies message is in this frame
1 implies message in future frame. s7- S1 contains the frame num.
- 35 n - Number of message words n8n7n6n5n4n3n2nlnO (1 to 511 Decimal )
s - Spares
x - Std 4 bit Check Character
19
SU8STITUTE SHEET (RULE 26)
WO 95/30316 2 ~ 8 9 1 5 ~ P~
Table 1 shows the formatting for a HEX/Binary message
usinq a 1X4 Flex format, which requires the desiy"dl;oll of a
vector type (HEX vector, single subchannel), the Word number
where the message will start, the number of message words in
the particular frame, and the subchannel assigned.
TABLE 2
HEX / Binary Vector (Multiple Subcarr~er)
û l 2 3 4 5 6 7 .. ......... 21 .. ~ .31 32
In~ormation Parity Ck
Xo Xl X2 X3 V0 Vl V2 V3 bo bl b2 b3 b4 bs b6 b7 bg bg b~o do~l P P P P P P P P P P P
xO xl x2 X3 nO nl n2 n3 mO cO cl c2 c3 C4 C5 eO el e2 e3 e4 eS P P P P P P P P P P P
V - Vector Type v3v2vlvO = 111o - HEX Vector Multiple Subcarrier
b - Word of message start = blob9-subchannell b8b7b6b5-Blor~k~ b4b3b2blbo-WOrd
d - Number of addition~l corners in message field (6 bits/corner)
n - Number of message words = nlOn9n8n7n6nsn4n3n2nlno (1 to 511 Decimal )
n10 - n4 are in message field.
2û m - 0 implies message is in this frame
1 implies message is in future frame. c;~-eO represent the frame num.
The first corner ill~u~ lioll is in message field.
c - first Corner = c5c4-Subchannel, c3c2clcO- Biock
e - second Corner = e~e4-Subchannel, e3e2eleO- Block
x - Std 4 bit Check Character
Table 2 illustrates the formatting for a HEX/Binary messa3e
using the 4X4 Flex format, which requires the designation of a
vector type (HEX/Binary, multiple subchannel), the location where
the first Word of the message will begin including ill~Ulllld~iO,
detailing the subchannel, block, and specific Word within the
block where the message will begin, the number of message
words, and cornering i"~or",alio,l which further defines within a
frame and block of i~ru~ liull where a particular message will
reside when it is decoded by the receiver. The cornering
ill~UlllldliOIl, as in the message start ill~.~lllldliOIl, should include
the subchannel location, block location, and in some cases the
Word location. Note that there may be other more precise or
more flexible methods within the scope and spirit of the present
SUaSTlTUTE SHEET ~RULE 26
WO 9~/30316 2 1 8 q l ~ "
invention than using "corner" C~lllllldll~, but "corner" Colllllldll~S
are an efficient compromise
TABLE 3
Alphanumeric Vector (Single Subclla-,ilel)
1 2 3 4 S 6 7 . . . . . . . . . . . . . . . . 21 . . . . . . . . 31 32
In~ormation Parlty Ck
xO xl x2 X3 vO vl v2 v3 bo bl b2 b3 b4 b5 b6 b7 b8 Yo Yl mO s( p p p p p P P P P P P
xO xl x2 X3 nO nl n2 n3 n4 nS n6 n7 n8 57 ~36 55 s4 83 82 51 5C P P P P P P P P P P P
V - Vector Type V3V2VlVO = 0101 - Alpha Vector Single Subcarrier
b - Word Number of message start b8b7b6b5b4b3b2blbo (1 - ~11 Decimal )
y - Subchannel assigned
m - 0 implies message is in this frame
1 implies message in future frame. S7- S1 contains the frame number.
n - Num. of message words in this frame np7nSnSn4n3n2nlno (1 to 511 Decimal)
s - Spares
x - Std 4 bit Check Character
Table 3 shows the formatting for a alphanumeric message
using a 1 X4 Flex format, which requires the d~siylldlion of a
vector type (alphanumeric, single subchannel), the Word number
where the message will start, the number of message words in
the particular frame, and the subchannel assigned.
TABLE 4
Alphanumeric Vector (Multiple Subc~lal)n~l)
1 2 3 4 5 6 7 . . . . . . . . . . . . . . . . 21 . . . . . . . . 31 32
Inforr2~tlon Parity Ck
xO xl x2 x3 vO vl v2 v3 bo bl b2 b3 b4 b5 b6 b7 b8 bg blo dodl P P P P P P P P P F P
xOXlx2x3nonln2n3mococlc2c3c4cseoqe2e3e4e5p P P P P P P P P P P
21
SUBSTITUTE SHEET (RULE 26)
WO9!i/30316 ;~ 1 89 1 5~
V - Vector Type V3V2vlvO = 1101 - HEX Vector Multiple Subcarrier
b - Word of messa3e st~art = b~ Sub.,hannel, b~7b6bs-BIock, b4b3b2blbo- Word
d - Number of additional corners in message field (6 bits/corner)
n - Number of message words = n~n3n7n6nSn4n3n2n1nO (1 to 511 Decimal )
n10 - n4 are in message field.
m - 0 implies message is in this frame
1 implies message is in future frame. cO eO represent the frame num.
The first corner illfulllldliol1 is in message field.
c - 1 st Corner = c5c4-Su~bchannel, c3c2c~cO~ Blo~k
e - 2nd Corner = e5e4-Subchannel, e3e2e1eO- Blo~k
x - Std 4 bit Check Character
Table 4 illustrates the formatting for an alphanumeric
message using the 4X4 Flex format, which requires the
d~siu,, IdliOIl of a vector type (alphanumeric, multiple subchannel),
the location where the first Word of the message will begin
including i~l~ur~dlioll detailing the subchannel, block, and
specific Word within the block where the message will begin, the
number of message words, and cornering ill~ulllldliul~ which as
before, further defines within a frame and block of il~u""d~ion
where a particular message will reside when it is decoded by the
receiver.
The presen~ invention has been described in detail in
connection with the disclosed embodiments. These
embodiments, however, are merely examples and the invention is
not restricted thereto. It will be ullcltll~Luod by those skilled in the
art that variations and mo.li~icdlions can be made within the
scope and spirit of the present invention as defined by the
appended claims.
What is claimed is:
22
SLlB~iT~TUTE Sl iEET (RULE 26
