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(12) Patent: | (11) CA 2234493 |
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(54) English Title: | STATE MACHINE ARCHITECTURE WITH MULTIPLEXED RANDOM ACCESS MEMORY |
(54) French Title: | ARCHITECTURE D'AUTOMATE FINI AVEC MEMOIRE A LIBRE ACCES MULTIPLEX |
Status: | Expired and beyond the Period of Reversal |
(51) International Patent Classification (IPC): |
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(72) Inventors : |
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(73) Owners : |
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(71) Applicants : |
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(74) Agent: | OYEN WIGGS GREEN & MUTALA LLP |
(74) Associate agent: | |
(45) Issued: | 2002-12-31 |
(22) Filed Date: | 1998-04-09 |
(41) Open to Public Inspection: | 1999-10-09 |
Examination requested: | 1998-04-09 |
Availability of licence: | N/A |
Dedicated to the Public: | N/A |
(25) Language of filing: | English |
Patent Cooperation Treaty (PCT): | No |
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(30) Application Priority Data: | None |
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A plurality of time-division multiplexed data streams which are merged into a single data stream containing a plurality of data words and which are characterized by state vectors, are concurrently processed. The state vectors are stored in a read-write memory having a plurality of addressable memory locations. During an initial clock cycle, a pipeline receives an input data word from one of the data streams, an input state vector characterizing that data stream, and the memory location address of the input state vector. During one or more intermediate clock cycles, the pipeline processes the input data word and the input state vector to yield an output data word and an output state vector. During a final clock cycle, the pipeline transfers the output data word to an outgoing data stream, and transfers the output state vector into the aforementioned memory location address. A controller coupled to the memory and to the pipeline synchronizes operation thereof. A null cycle generator coupled to the pipeline and to the controller inserts null cycles into the concurrently processed data streams at regular time intervals and outputs a NULL signal to the controller during each null cycle. A multiplexer coupled between the controller and the memory multiplexes access to the memory between the controller/pipeline, and an alternate controller. Read access to the memory by the controller or pipeline is inhibited while the NULL signal is output, and write access to the memory by the pipeline is inhibited while an OUTGOING NULL replica of the NULL signal is being output by the pipeline during the final clock cycle. Accordingly, the alternate controller may gain read access to the memory while the NULL signal is output, and may gain write access to the memory while the OUTGOING NULL signal is output.
Pluralité de flux de données multiplexés dans le temps qui sont fusionnés en un seul flux de données contenant une pluralité de mots de données et qui sont caractérisés par des vecteurs d'état, traités de manière concurrentielle. Les vecteurs d'état sont stockés dans une mémoire de lecture et d'écriture ayant une pluralité d'emplacements de mémoire adressables. Pendant un cycle d'horloge initial, un pipeline reçoit un mot de données d'entrée de l'un des flux de données, un vecteur d'état caractérisant le flux de données, et l'adresse d'emplacement de mémoire du vecteur d'état d'entrée. Pendant un ou plusieurs cycles d'horloge intermédiaires, le pipeline traite le mot de données d'entrée et le vecteur d'état d'entrée pour donner un mot de données de sortie et un vecteur d'état de sortie. Pendant un cycle d'horloge final, le pipeline transfère le mot de données de sortie vers un flux de données sortant, et transfère le vecteur d'état de sortie dans l'adresse d'emplacement de mémoire précitée. Une unité de commande couplée à la mémoire et au pipeline synchronise leur fonctionnement. Un générateur de cycle zéro couplé au pipeline et à l'unité de commande insère des cycles zéro dans les flux de données traités de manière concurrentielle à intervalles de temps réguliers et sort un signal ZERO à l'unité de commande pendant chaque cycle zéro. Un multiplexeur couplé entre l'unité de commande et la mémoire multiplexe l'accès à la mémoire entre l'unité de commande/le pipeline, et une unité de commande alternée. L'accès en lecture à la mémoire par l'unité de commande ou le pipeline est empêché pendant que le signal ZERO est sorti, et l'accès en écriture à la mémoire par le pipeline est empêché pendant qu'une réplique ZERO SORTANT du signal ZERO est sortie par le pipeline pendant le cycle d'horloge final. En conséquence, l'unité de commande alternée peut obtenir l'accès à la mémoire pendant que le signal ZERO est sorti, et peut obtenir l'accès à la mémoire pendant le signal ZERO SORTANT est sortie.
Note: Claims are shown in the official language in which they were submitted.
Note: Descriptions are shown in the official language in which they were submitted.
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Description | Date |
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Time Limit for Reversal Expired | 2014-04-09 |
Letter Sent | 2013-04-09 |
Grant by Issuance | 2002-12-31 |
Inactive: Cover page published | 2002-12-30 |
Inactive: Final fee received | 2002-09-27 |
Pre-grant | 2002-09-27 |
Notice of Allowance is Issued | 2002-09-19 |
Letter Sent | 2002-09-19 |
4 | 2002-09-19 |
Notice of Allowance is Issued | 2002-09-19 |
Inactive: Approved for allowance (AFA) | 2002-07-30 |
Amendment Received - Voluntary Amendment | 2002-06-19 |
Inactive: S.30(2) Rules - Examiner requisition | 2002-05-24 |
Application Published (Open to Public Inspection) | 1999-10-09 |
Inactive: Cover page published | 1999-10-08 |
Classification Modified | 1998-07-13 |
Inactive: First IPC assigned | 1998-07-13 |
Inactive: IPC assigned | 1998-07-13 |
Inactive: Filing certificate - RFE (English) | 1998-06-19 |
Application Received - Regular National | 1998-06-18 |
Request for Examination Requirements Determined Compliant | 1998-04-09 |
All Requirements for Examination Determined Compliant | 1998-04-09 |
There is no abandonment history.
The last payment was received on 2002-01-21
Note : If the full payment has not been received on or before the date indicated, a further fee may be required which may be one of the following
Patent fees are adjusted on the 1st of January every year. The amounts above are the current amounts if received by December 31 of the current year.
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Fee Type | Anniversary Year | Due Date | Paid Date |
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Application fee - standard | 1998-04-09 | ||
Request for examination - standard | 1998-04-09 | ||
Registration of a document | 1998-04-09 | ||
MF (application, 2nd anniv.) - standard | 02 | 2000-04-10 | 1999-10-22 |
MF (application, 3rd anniv.) - standard | 03 | 2001-04-09 | 2000-11-01 |
MF (application, 4th anniv.) - standard | 04 | 2002-04-09 | 2002-01-21 |
Final fee - standard | 2002-09-27 | ||
MF (patent, 5th anniv.) - standard | 2003-04-09 | 2003-01-06 | |
MF (patent, 6th anniv.) - standard | 2004-04-13 | 2004-03-17 | |
MF (patent, 7th anniv.) - standard | 2005-04-11 | 2005-03-18 | |
MF (patent, 8th anniv.) - standard | 2006-04-10 | 2006-03-20 | |
MF (patent, 9th anniv.) - standard | 2007-04-10 | 2007-03-21 | |
MF (patent, 10th anniv.) - standard | 2008-04-09 | 2008-03-25 | |
MF (patent, 11th anniv.) - standard | 2009-04-09 | 2009-03-23 | |
MF (patent, 12th anniv.) - standard | 2010-04-09 | 2010-03-23 | |
MF (patent, 13th anniv.) - standard | 2011-04-11 | 2011-03-22 | |
MF (patent, 14th anniv.) - standard | 2012-04-09 | 2012-03-21 |
Note: Records showing the ownership history in alphabetical order.
Current Owners on Record |
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PMC-SIERRA LTD. |
Past Owners on Record |
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LARRIE S. CARR |
WINSTON KI-CHEONG MOK |