Note: Descriptions are shown in the official language in which they were submitted.
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IMAGE PROCESSlNG SYSTEM CONVER'llNG ~t~ V~ VIDEO DATA AI~D ADl.K~i~
DATA
Technicai Field
The present invention relates to image data processing, wherein video
circuits are arranged to convey sequential video signals and data circuits are
arranged to convey l~n-lo",ly address~hie image data.
~ack~round Art
Systems for image data processing are known in which video data is
0 transmitted as a digital stream clocked with reference to sy~ Ichrunization
signals representing the start of frames or the start of interlaced fields within
said frames. In bro~ t envi-u~ e,ll~ and within facilities houses the D1
standald for the l.dl.~r,l;ssion of digital video is popular wherein the video
signal is Lld~ iLLed as a luminance signal (Y) plus color difference signals
15 (UV) to r~ l* conversion to convenLiul,al bro~r~-st sLa"ddnls such as
NTSC and PAL. The digital signals are clocke~l in real-time at video rate to
f~cflit~te conversion in real time to anaiog siylldls for lldnsl~.;ssion purposes
Thus within such f~ ';es the L dl.S~.;SsiO" of ~igi~i~ed video signals is
similar to the lldl~lll;s5iOIl of their analog equivalents where the rate of
20 ~ans~;ssio~l remd--~s con:,ldnl and all lldns...;ssiol-s are sy.-cl..o.li~ed to the
field and frame L~ldllkil~y intervals.
Image data ,~rucessi--g systems are also known in which image data
is Ll dl -s-, lilled in a way s~ s~ Lially similar to the L. dl -~- - ~;ssior, of any other
type of data within a computer envi~u- ~.-.el -l. W thin computer env;.-~n. . ,e~ it
25 is unusual for L~ru~lcasl quality video siy..als to be produced, therefore,
conve.-Liu,-ally signals have been transmitted as red, green and blue (RGB)
color cc,."~,u..e"ts so as to be cG...~JclLiLJle with CRT l..o.~iLu,ing devices. Data
signals within a a~mputing env;.-,nl)-ent are also tra"~",;;Led relatively
asy,-ul-ru--ously and relatively rdn~o,-,ly, given that each data L d.,:jr~r usually
30 takes place by issuing add,ess signals. wherein said add~ess signals may
resenl h~iu,-s within solid state Ine,..o,y devices or lo~Lio..s within
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mass storage devices sa~ch as magnetic disks etc. Simiiarly, asynchronous
protocols have been developed for the transmission of signals between such
devices, such as the small computer systems interface (SCSI).
In systems developed forthe l,~nsil,ission and pr~cessing of YUV D1
5 signals, reliance has been made significantly upon purpose built hardware.
However, post-production and broadcast facilities are tending to move
towards software intensive solutions on relatively low cost general purpose
workstations. This allows software applications (defining a system's
functionalit~) to be developed independently of hardware plafforms,
10 facilitating modi~ication and upgrading when compared to hard-wired
hardware solutions. However, although workstations are becoming more
powerful, many relatively simple tasks nay piace unprecedented burdens
upon central processing units and a high perforrrance so~ware package may
become significantiy downgraded b,v processing time being occ-lpied by
15 relatively low Icvcl housekeeping procedures.
SL~ lldr~ of the Inv~
According to a first aspect of the present invention, there is provided
image data processing apparatus for converting betvveen sequential video
20 data and addressed image data to effect transfers between video circuits and
data circuits, said apparatus co, ~ l isi~ Ig processing means arranged to
transfer data between said circuits at a rate e4ual to or greater than video
rate; and ~Il.wLlil ,9 means operable to rearrange the order of components of
said data representing color samples i~eing l-dll,r~iled by said processing
25 means~
Preferably, said formatting means inciudes packing rneans, arranged
to pack color components together into data words so as to remove
redundant regions of said words.
Accor iillg to a second aspect of the present invention, there is
30 provided a metnod of processing image data for converting between
sequential video data and addr~ssed image data to effect l-dn .rt:,;j between
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video circuits and data circuits, said method co,l,p~isi"g steps of transferringdata between said circuits at a rate equal to or greater than video rate; and
rearranging the order of components of said data representing color samples
being transferred.
Preferably, a color-space conversion process converts data between
luminance plus color di~Ference representations and primary color
represenlaliGns.
According to a third aspect of the present invention, there is provided
image data processing apparatus for converting be~Neen sequential video
data and addressed image data to effect transfers between video circuits and
data circuits, said apparatus co" ,~u(ising processing means arranged to
transfer data between said circuits at a rate equal to or greater than video
rate; and buffering means arranged to buffer transfers between said video
circuits and said addressed circuits, said buffering means including a first
buffering unit to provide access to a L,~ns",ission environment and a second
buffering unit to provide ~ccess to a storage envi,c,n",ent.
Brief Descr.,~io.- o~ the Drawings
Figure 1 shows a post-production video artist using an application for
modifying image frames, including an applicalio"s piafform, a video tape
recorder and an image processing system providing real-time communication
between the appli~tions ~uldLrul 11 1 and the tape recorder;
Figure 2 identifies a schematic represenl~liul, of the environment
illustrated in Figure 1, in which an image processing system conver~s
between sequential line-based video signals and randomly addressable
image data;
Figure 3 illustrates differences between line-based video signals and
~ address-based image data;
Figure 4 details the image processing system shown in Figure 2,
including a video buffer, a router, a color space converter, a proxy generator,
a re-ru""~ll3r, a disc buffer, a network buffer, a parity generator and a PCI
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bus;
Figure ~ details the video buffer identified in Figure 4;
Figure 6 details the router identified in Figure 4;
Figure 7 illustrates the configuration of PCI devices, including the PCI
bridges shown in Figure 4;
Figure 8 detaiis the color-space converter shown in Figure 4;
Figure 9 details the proxy generator identified in Figure 4;
Figure 10 details the re-rul " l~lLil ,g circuit identified in Figure 4,
including a packing circuit; and
Figure 11 details the packing circuit identified in Figure 10.
Detailed Description of the Preferred EmLodi,~i.t
The invention will now be described by way of example only with
reference to the previously identified drawings. A post-production facility is
1~ illustrated in Figure 1, in which a video artist 101 is seated at a processing
station 102. Images are displayed to the artist via a visual display unit 103
and manual selections and " ,odiricalions to the displayed images are
effected in response to manual operation of a stylus 104 upon a touch tablet
105. In addition, a conventional keyboard 106 is provided to allow
alphanumeric values to be entered directly The monitor 103, tablet 105 and
keyboard 106 are interfaced to an image manipulating wc,rhsL~lion 107, such
as an Indigo Max Impact, manufactured by Silicon Glc"~l~ics Inc., nunning
compositing applic~liGns, such as "FLlNr' or "FLINT RT" licensed by the
present applicant.
Image data may be supplied to the wc-l~ldlion 107 from a D1 digital
video tape recorder 108 via an image processing system 109. The video tape
recorder 108 and the processing system 109 are both controlled directly in
response to cG~ a~ lds issued by the artist 101, thereby effectively
embedding the operation of these machlnes within the ap~licalio, Is
environment. Processing system 109 is arranged to receive video data from
the video ,-:corder 108 at video rate and is alld"~aed to write said data to its
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own internai storage devices at thls rate. The processing system 109 is then
in a position to make this recorded data available to the workstation 107, or tosimilar devices via a high bandwidth networ~ such as "HiPPI", via a network
cable 110.
The environment shown in Figure 1 is illustrated schematically in
Figure 2. The workstation 107, its interfaces and its associated applications
may be considered as a loeal applications platform 201. The processing
system 109 may be considered as comprising an image processing system
202 having associated circuitry which may be considered as belonging to an
addressed data environment 203 or to a video environment 204. The local
applications plafform 201 communicates with the image processing system
202 via the addressed environment 203. The addressed environment 203
also communicates with a local array of discs 205, which may be configured
in accorllallce with RAID protocols. Thus, the local array 20~ may include a
15 conventional SSA adapter, such as the type supplied by P~Lhliyl-l
Technology Inc. of 767 Warren Road, Ithaca, New York, 14850 and the
addressed environment 203 includes circuitry for translllilli,lg and receiving
data from the SSA ~d~rt~r in accordance with conventionai protocols. The
addressed environment 203 also includes interface cards for connection to a
20 HiPPI ne~Nork 206.
A D1 serial digital input 207 supplies synchronised D1 video to the
video environment 204. Similarly, output video from the video environment
204 is supplied to an output cable 208. Interfaces 207 and 208 may be
c.,r,r,ected to a video t::lpeu reGorrleri su5h as tape recorder 108 shown in
2~ Figure 1. The video environment 204 also s~lpplies analog video signals to a
video monitor 209, allowing an operator to view video images as they are
being l~ liLled through the image prucess;"g system.
The add,~ssed envi,ol""enl 203 and the video envilull''lent 204 have
two distinct differences in temms of the way in which data is processe~l within
30 these environments. Within the video environment 204, pixel data is
tral,srl,ilL~:d sequentially starting from the top left position of an image frame
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and then scanning from left to right along a scan line, with lines being
transmitted sequentially from top to bottom. Thus, the location of a particular
pixel within an image frame is deterrnined by its temporal location within a
transmltted frame's worth of data. In this way, it is not necessary to provide
5 addressing channels given that the order of the pixels within a frame always
follows the same predetermined scanning pattern, usually consisting of
interlaced frames. However, within the addressed environment 203 data
need not be l.~"sl "ill~:d in a sequential way. Each data transfer is
accomplished by identifying its address within storage space, therefore a
10 complete frame's worth of data may be transmitted in any order provided that
each pixel data is accompanied by addressing information. This mechanism
for transfernng data is particularly advantageous when using disk arrays
which, due to mechanical differences between the drives, will result in data
being transmitted in a substantially random way. However, provided that
15 each unit of data is accompanied by its co"t:sponding address illr~nll~lion,
simple buffering techniques allow the full frame to be re-established in its
original pixel order.
A second significant difference between the addressed environment
203 and the video environment 204 is that the trans"~.ssion of data within the
20 video en\~irulln'ent is synchronized such that data is transmitted at 13.5
megahertz or integer multiples thereof. Thus, data may be l,ansl,lillecl within
the video env;lur".lent 204 at 27 megahertz such that each channel is
capable of conveying two real-time video ~ ams. In this way, after a
predetei"l;.,ed period of time, the amount of data transferred will be known
25 and will remain fixed. This differs from the addressed environment 203 in
which, although provided with a notional transfer bandwidth, such as 33
megahert~ in a typical PCI system, the actual av..ila~ilily of buses for a
specific data transfer will depend upon other consl,~i"ls placed upon the
environment. Thus, if the bus is required to effect other transfers within the
30 environment or if a bus mastering processor is tied up with other activities,;;,sion wiil cease until the process can again obtain access to the bus.
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Thus, transfers are not synchronized to speci~ic events but are interrupt
driven, with priority given to the hlghest priority interrupt.
These hvo differences create problems wh~n attempting to e~fect real-
time data transfers between a video environment and a typicai addressed
5 environment. In known systems, transfers often take piace at less than real-
time, with a block of data being transferred in the first protocol, whereafter
processing routines are required to convert the data into a diflerent protocol.
Under such circumstances, the video environment must be mcdified and
inter upted so as to allow it to transrer data to tha addressed environment. in
10 the arrangement shown in Figure 2, the video environment is arranged to
transfer data transparently to an environment it sees as being vfdeo
compaiible. Similariy, the addressed environment 2û3 may transfer data with
the image processing system 202 in a way which it perceives as being
addressed-co~ Iihle These transfers occur at a rate which is at least equal
1~ to video rate and possible higher, such that the operdl,u"s of a lldll~"ilLing
device are not limited by the c~r~hilities of a receiving devics. Consequentiy,
the transfer of data from a D1 digital video environment to an RG8
addressed environment occurs with no more difficulty than a similar transfer
from a D1 digital environment to a similariy configured processing
20 environment, arranged to process D1 digital signals directiy.
Dirrere"ces between the tra"s-";ssion of digital video and addressed
data are illustrated in Figure 3. An analog video picture is illustrated at 301
and is made up of a first field of scan lines 302, shown as solid lines, which
are interlaced with a second field of scan lines, illustrated by broken iines
2~ 303. A first field scan consists of the first field of lines 302 being s~n.. ed
~rom the top left of the picture to the bottom right of the picture. A field
blanhil ,g interval then occurs as ele~ ,nics are reset to f~ t~t~ the
~ ope.dlion of the next scan. The s~ ~hse~ ent fieid conhi"s the interlaced lines
3û3 and again a scan..i.,~ ope,~liGn is pe,ru,--led frorn the top left to the
30 bottom right of the picture. The scanning of two interlaced fields in this way
cons~h Ites a whole frame and after a frame of two fields have been scanned,
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the process is repeated at a frame rate of 2~ or 30 frames per second.
D~ serial digital signais may be generated in real-time by receiving a
scanning analog signal which is supplied to an analog to digital converter
304. The analog video signal is conveyed as a luminance signal Y plus two
color difference signals U and V and each of these samples are digitized and
multiplexed to produce a serial stream at 13.5 megahertz. These serial digits
are illustrated at 305 and represent a stream of data corresponding to the
luminance and color of the original analcg signal.
The disital stream 305 is synchronously clocked in response to
10 clocking signals 306, generated in synchronism with the field blanking
intervals. Thus, although the video information, originally in analog form, has
been digitized into a data strearn, this data stream still synchronously followsthe field intervals of the original source video. Simila~y, these digital samples
represent color components which are similar to those used in analog video
15 environments, defining luminance plus color difference components. In this
way, real-time conversion is f~c;lif~t~srl between digital and analog
environments with the video signal having many characteristics in common
with conventional anatog Ll c,, Isl, lission.
An analog picture dispiay within a computing environment is illustrated
20 at 308. A computer CRT receives analog signals for it's red, green and blue
components, which are generated in response to digital input signals. The
storage of data within such env;,unl~e~lL~ is therefore carried out entirely
within RG~ color space, with no requirement being present for conversion
into YUV color space. Consequently, when receiving conventional video
25 data, although in ~i~iti~Pd form, it is necessary to perform this conversion
from YUV color space to RGB color space.
A visual display is generated by scanning a frame buffer 309 at an
appropriate frame display rate. A computer system may refresh it's screen at
whatever rate is considered appropriate and, in order to enhance the quality
30 of CRT displays, computer images tend to be refreshed at a higher rate than
that of television broadcasts, with frames tending to be non-i,lLe,laced. Thus,
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a computer image tends not to consist of non-interlaced frames and the
refresh rate tends to be higher than that occurring in conventional broadcast
television systems.
Ir. cor.ve..tior.c.l ~elevisio.. ar.d video systems, new d~t2 is !eceived for
each displayed frame and the system is described as operating in real-time
or at video rate. In computer systems this is often not the case and aithough
a screen may be refreshed at a higher rate than video systems, the rate at
which new data is used may be less than that occurring within video systems.
Thus, a computer system has the option to display the same source data
many times by reading the data from it's frame buffer 309.
Frame buffers are known within video environments and usually
involve the writing of data to the buffer in sequential order with the data thenbeing read from the buffer in sequential order, unless the buffer is being used
to perform a video effect. in computer based systems, the transfer of data
does not necessa,ily take place in a sequential way. In the system shown in
Figure 3, the data is read sequentially from frame buffer 309 in order to
generate display 308. However, data may be written to the frame buffer 309
in any random order and at a rate which may depend upon the processing
capabilities of the central processing unit itself. Thus, data may be written toframe buffer 309 by placing an address on address bus 310 so as to identify
a particular location within the frame buffer. Thereafter data is supplied to
data bus 311 so as to allow the data to be written to the location defined by
the address bus. In this way, it is possi'~le to write data to the frame buffer
309 in a completely random way bec~use each item of data is identified by
2~ it's own speci~ic address supplied to the address bus 310.
The rate at which data is cloclced on address and data buses 310, 311
will depend upon the system employed but essentially it may be considered
~ as being sub~ ,lially asynchronous compared to the clocking of video data
through, say, analog to digital converter 304. Furthemmore, in more powerful
machines, the data rate at which data is clocked through the intemal buses
will i"c, ease with system power and complexity. Thus, within the data
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environment, the rate of trans~er will tend to depend upon the system's
capabiiities and data will be transmitted at a maximum possible rate. This
compares with the video environment in which the rate of transfer is
dependant upon ~he nature of the data itself, with data usually being
5 transferred at conventional video rate or, in more sophisticated systems, at
integer-multiples thereof.
image processing system 202 is detaiied in Figure 4. The processing
system includes a video buffer 401 which communicates with a
synchronously clocked router 402. The router 402 is arranged to direct data
to a color-space converter 4~3, a proxy generator 404 and a digital to analog
converter 405, suppiying analog RGB signals to video monitor 209. The
router 402 also communicates with re~ormatting circuits 406 and 407, which
in turn communicate with their respective buffers 408 and 409. Disk buffer
408 facilitates communication between the router 402 and local disks 20~;
and as such it may be identified as the disk buffer. The local RAID 205
includes redundant parity inforrnation, therefore parity circuit 410 is
associated with disk buffer 408 in order to generate parity as data is being
written to the disk array 205 and, where necessary, to reconstitute lost data
from said parity information. Parity circuit 410 and disk buffer 408
communicate with the local RAID 205 via an SSA interface card 411.
Commul,ic~Lions with network 206 are effected via a HiPPI network
card 412, while communications with the local ~.r.plic~ s pldlru~ 201
takes place via a SCSI interface card 413, ,u,~fer~bly provided with two SCSI
channels in the preferred embodiment.
The processing system 202 is controlled by a programmable
processing unit 414, which is responsible for co-ordinating activities within the
processing system and for downloading instructions to specific components
within the processing system. In the ;,r~r,ed embodiment, p,ucessing unit
414 is i"~plel"enled as an Intel Illic,u,urucessor communicating with a primary
thirty-two bit PCI bus 415 clociced at 33 megahertz. The primary PCI bus 415
allows processi"g unit 414 to suppiy memory mapped control signals to
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associated processing sub-systems. However, the primary bus 415 is not
used for the transmission of image data. The mechanism for trar,:jre"i"g
image data within the image processing system 202 Is the router 402, wi~h
transfers also taking place via one or both of buffers 408 and 409.
Network buffer 409, netNork card 412 and interface card 413
communicate via a secondary PCI bus 416, which may be considered as a
network bus. Secondary bus 416 is connected to primary bus 415 via a PCI
bridge 417. Bridge 417 is configured to allow controi information to be
transmitted from primary bus 41~ to secondary bus 416 as if the ~rldge 417
effectively did not exist. However, data Iying outside a specified address
range will be treated as data and as such bridge 417 will be perceived as
being closed. Consequently, any image data supplied to seconda~ bus 416
can communicate between network card 412, interface card 413 and network
buffer 409 but cannot be conveyed to the primary bus 415 via the bridge 417,
which will be seen as open.
A simiiar arrangement is provided for communication between the disk
buffer 408 and the disk interface 411. ~ secondary PCI bus, which may be
considered as the disk bus 418 is connected to the primary PCI bus 415 via a
second PCI bridge 419. Bridge 419 allows control information to be
transferred from the processing unit 414 to the interface card 411, its
associated SSA adapter and to disk buffer 408. However, the bridge 419 is
effectively closed for the transn.;ssion of image data, such that image data
supplied to the network bus 418 is blocked from reaching the primary bus
41~. Consequently, no major burdens are placed upon the processing unit
414 and its associated primary bus. Processing unit 414 is only concerned
with configuring other subsystems and is not itself directly responsible for
co~ .I,.,lling the transfer of image data via bus mastering or other techniques.Data transfers within the image processing system 202 preferably take
place within RGB color space. Consequently, D1 video signals supplied to
the video environment 204 are color-space converted within said
environment using conventional de~ic~t~d circ~lits employed in digital video
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systems. However, signals supplied to the processi.l!J systern 202 from the
video environment are sequentiaily clocked, consist of interlaced fields and
include field blanking and would normally be perceived as video signals. The
addressed environment 203 includes the SSA adapter for supplying data to
the local raid 20~. Data supplied to the raid 205 is effectively data like any
other type of data and, as such, the fact that it represents image frames is
i,ll"lalerial to the operation of the SSA environment.
Typical operations of the processing system shown in Figure 4 may be
considered as follows. In a first mode, a local application running on plafform
201 may reguest a search and preview of information stored on a video tape
recorder, such as recorder 108. The video information will be read from the
video tape recorder and supplied to the video buffer 401. The video buffer
401 is responsible for converting the serial data into a parallel stream and as
such may be considered as a serial to digital interface.
In addition, the video buffer 401 removes field blanking such that the natur~
of the data supplied to the router 402 from the video buffer 401 ceases to be
"video" in the accepted sense. The router 402 routes the incon,;ny signal to
digital to analog converter 405, allowing the incoming video clip to be viewed
on monitor 209. In parallel to this, the incoming video stream is supplied to
proxy generator 404 configured to produce a re~iuce~ bandwidth version of
the incoming video (with a resolution reduced ~y half in both dimensions)
which is in tum routed to the network buffer 409 where it is written
sequentially to said buffer so as to buiid up a complete frame of a r~duced
bandwidth image.
Network buffer 409 is configured as a double frame buffer therefore as
one frame buffer receives data from router 402, the other frame buffer is
available to supply image data to the SCSI interface card 403 via the network
bus 416.
After a particular clip has been identified by the above search
procedure, the clip itself may now be written to the local RAID 205. In parallelwith the procedures identifed above. resulting in the incc~l,,;,,y c3ip being
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monitored on video monitor 209 and also previewed in proxy forrn on display
103, router 402 also routes the full bandwidth version of the incoming video
to the disk buffer 408. Disk buffer 408 includes two frame buffers, to effect
double buffering at the frame level, allowing the first frames-worth of data to
be written to the buffer while a second frames worth of data is read from said
buffer. Data in disk bufler 408 is striped and an additional parity stripe is
generated by parity circuit 410, wherea~ter all of the stripe data is written tothe RAID 20~ via the SSA adapter and interface card 411.
A third mode involves clip output, where image data is read frorn the
local RAID 205 and supplied to a video store, such as a video tape recorder.
From the disks and the SSA adapter, data is written to the disk buffer 408.
This transfer will take place randomly, due to the way in which the SSA
adapter will package data received from the array. The data is there~ore
assembled within the disk buffer 408 and read from said buffer sequentially to
provide a stream to the router 402. The clip will have been stored in RGB
format therefore it is necessary to direct the signal to the color-space
converter 403, arranged to reconvert said signal back to YUV format for
application to the video bu~fer 401. In parallel with this, the RGB signal is
supplied to the video ~I,oniLor via converter 405 and the transfer is viewed on
display 1 Q3 by directing the RGB signal to the proxy generator 404, again via
router 402, whereafter said reduced band-width signal is supplied to the
network buffer 4û9.
A fourth mode consists of clip playback; s~b~ lly similar to clip
output but without the need to direct a color-space converted signal to the
video buffer401.
As an altemative to supplying reduced bandwidth signals to interface
card 413, router 402 may be arranged to direct full bandwidth RGB signals to
~ network buffer 409, whereafter image data read from said buffer is di~e.;led to
the network card 41Z for application to the high band-width network.
Unlike the video environment, the addressed environment is equally
c~p~hlQ of Lld~ llillillg individual frames in ~d~:lio" to l-d.l~lll..Lillg video
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clips. This involves a transfer between interFace card 411 and interFace cards
412 or 413. As previously stated, a transfer of this type does not take place
via the primary PCI bus 415. During a frame read, individual frame data from
interface card 411 is written to disk buffer 408, read from said buffer, appiiedto router 402, routed to network buffer 409 and read from said buffer 409.1f
the frames are to be supplied to interface card 413 at reduced bandwidth, the
signal is routed via the proxy generator 404 and then routed to the network
buffer 409.
Sirr.ila~y with a frame write, an incoming frame may be received by
10 interface card 413 and written to network buffer 409. The frame is therl readfrom network buffer 409 and written to disk buffer ~08 via the router 402. The
frame data is then read from disk buffer 408 , parity is generated and the
resulting stripes are supplied to interface card 411.
Video buffer 401 effectively consi~l~ of two buffers each arranged to
15 convey two real-time video streams to router 402 at 27 megahertz. Each of
these individual buffer circuits may therefore simultaneously receive a D1
video stream at 13.5 megaher~z while L,dnsl"ilLi.,g a simDar stream at 13.5
megahertz.
The video buffer 401 is detailed in Figure 5, consisting of a first buffer
20 circuit 501 and a substantially similar seco,)d buffer circuit 502. The firstbuffer circuit 501 will be described and it should be u, ,der~Luod that
subsL~"Iially similar operations are effected by the second buffer circuit 502.
An inco,.,i"g D1 video stream, color converted to RGB, is received on
an input serial line 503. The incoming data may include an audio embedded
25 stream and includes field blanking. The audio inbedded stream is separated
by audio embedding circuit 504 and supplied to an audio buffer 505. A switch
506 directs incoming video data to a first field store 507 or to a second field
store 508. Each field store is arranged to store only video data and does not
store field bldl)killg. Thus, the process of writing the serial stream to one of30 said stores effectively removes the field blanking from the video stream suchthat, ther~r, the data is tran.ci,lliLIed as s~hst~r~tially conti~lo~s blocks.
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The field buffers 507 and 508 provide double buffering such that as
data is written to the second field buffer 508, in acco~.~al~ce with the
configuration shown in Figure 5, data previously written to the first field buffer
507 may be read as parallel thirty-two bit words at twenty-seven megahertz
for application to the router 402 over bus 509. The reading process wili also
access audio buffer 505, thereby adding audio data to the twenty-seven
megahertz data stream.
Within a field period, it is also possible for data to be received from bus
509 for application to output serial digital 1ink 5~ 0. The field period is divided
into two sub-periods, within the twenty-seven rnegahertz domain, and in said
second sub-period audio data may be written to audio buffer 511, with a field
of video data being written to field store 512 or field store 513. Under the
configuration shown in Figure 5, incoming data is written to the second field
store 513, allowing the first field store 512 to be read serially at 13.5
megahertz to provide a serial stream to the audio embedding circuit 514. At
circuit 514 audio data is embedded in accordance with the AES protocol by
reading audio data from audio buffer 511. Interlaced RGB video with field
blanking at 13.5 megahertz is then sllprlied to output channel 510. Thus, the
reading of field buffers 512 or 513 is appropriately delayed in order to
introduce the required field blanking intervals.
The router 402 is detailed in Figure 6 and is fabricated around six
thirty-two bit buses clocked at twentv-seven megahertz. The transfer of
image data in this mode represents the preferred transr"ission protocol within
the processing system. It is conveyed along the ~,a~dllcl bus, similar to data
l,~i~s.";ssion but this bus is synchronised at twenty-seven megahertz and
~ does not require an associated address bus. A first thirty-two bit bus 601
receives networked data from the refol III~ILil l~J device 407. The second thirty-
two bit bus 602 receives disk i, ~rO~ lion from the storage devices via
reformatting circuit 406. The third bus 603 receives a first video stream from
video buffer 401, while the thirty-two bit bus 604 receives the second video
stream from data buffer 401. The fifth thirty-two bit bus 605 receives the
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output from the coior-space converter 403, with the sixth bus 606 receiving a
simDar output from the proxy generator 404.
I~outing is affected via the buses because in addition to the six input
sources, seven output destinations are connected to the bus. The first
selector 607 receives input from the disk bus 602, the first video bus 603, the
second video bus 604, and the proxy bus 606. Selector 607 receives
instructions from the processing unit 414 to select one of these sources
thereafter the selected source is applied to the network reformatting circuit
407.
A second selector 608 receives input from the network bus 601, the
first video bus 603, the second video bus 604 and the proxy bus 606. Again,
in response $o control signals from the processing unit 414, selector 608 is
arranged to select one of these input signals by application to the disk
reformatting circuit 406.
Communication paths between the router 402 and the video buffer
401 are bi-directional and are configured so as to lldns",il two real-time videosources over a tNenty-seven megahertz lldl,s"~;ssion channel. To achieve
this, one of the sources wiil be supplied to the router with the second
rnultiplPxed signal being supplied from the router back to the video buffer
20 401. The router therefore includes a first multiplexor 614 and a second
multiplexor 615 each arranged to connect ml~ltirlexed channels to respective
input or output ports within the router. A third selector 609 receives inputs
from the network bus 601, the disk bus 602, color space converter bus 605
and the proxy bus 606. A selection is made by seie~tor 609, in response to
25 control instnuctions from the processing unit 414, resulting in a selected input
signal being supplied to the multirleYor 614. Similarly, fourth selector 610
receives inputs from the ne~vork bus 601, the disk bus 602, the coil~r space
converter bus 605 and the proxy bus 606. Again, in response to control
signals issued by the processing unit 414, a sele~ted signal is supplied to
30 multiplexor 615.
A fr~th selector receives inputs from the network bus 601 and the disk
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bus 602. Again control signals are received from the processing unit 414 so
as to select one of these input signals which is in tum supplied to the color-
space converter403.
Inputs from the first video bus 603 the se~ond video bus 604 and the
proxy bus 606 are supplied to a sixth selecf~r 612. In response to control
signals from the processing unit 414 the sixth selector 612 supplies a
selected signal to the proxy generator 414. The seventh selector 613
receives inputs from the hrst video bus 603 and the second video bus 604.
An output is selected in response to control s.gnals from the processing unit
10 414 resulting in the selected signal being supplied to the digital to anaiog
converter 40~.
It can be appreciated that the router achieves a routing function by
allowing a signal to be selected from its tra~,sll-ission bus. In this way a
swi.ch is ef.fe~.ively r.or.=b!ockiny because the transmisslon of one signa!
15 along its respective bus cannot effect the trans~llissio" of other signals along
their respective buses. The router does not provide for all possible
interconnections and is tailored to meet the requirements of the system s
overall functionality. However additional routing paths may be introduced by
allowing signals to bypass through the proxy generator andfor the color-
20 space converter.
Data is L,ansr"ilLed to interface cards 412 413 and 411 in accordancewith PCI protocols. The PCI envi,u"-"enl consists of a primary PCI bus 41~
with seco"daly PCI buses 416 and 418 connected to said primary bus by
respective PCI bridges 417 and 419. The ,~ rucessi"g unit 414 provldes the
25 primary bus master for the PCI envi, ul ll l ~ent, although other devices such as
the SSA adapter ~ssoci~ted with the disk drives may be allowed to bus
master in ,ur~:r~r~nce to this processing unit. When operating power is initially
supplied to processing unit 414 configuration instructions are automatically
retrieved from ~ssoci -'ed read-only mer"GI y and these instructions will
30 determine which PCI devices are connected to the primary bus along with an
ide"liri~liQ" of their configuration requi,~ ellls. This process is known in
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the art as sca~"~ g or probing the bus and in order ~o facilitate this process
PCI devices irnplement a base set of configuration registers in additions to
device-specific configl Iration registers.
The configuration instn~ctions read a sub-set of the devices
configuration registers in order to d~le""i.,e the presence of the device and
it's type. Having determined the presence of the device other configuration
registers for the device are accessed to determine how many blocks of
memory and the degree of inpuVoutput space is required in order to effect
satisfactory operation. Memory associated with the device is then
10 programmed along with interface and address decoders in order to respond
to memory and inpuVoutput address ranges that are guaranteed to be
mutually exclusive to other devices forming part of the system. PCI
configuration is implemented using address space 0800H to 08FFH thereby
insuring that compatibility is retained with other environments of this type. PCI
15 bridges 416 and 417 also require the i"".le",er,l~lion of two hundred and fifty
six configuration registers utilising two thirty ~vo bit registers located at
addresses OCF8H and OCFCH within the address space of processor 412.
These registers may be identified as the configuration address register and
the configuration data register.
The configuration r eyisl~r:j are ~ccessed ~y writing bus number
physical device number function number and register number to the address
register. Thereafter an inpuVoutput read or write is perru~,,,ed to the data
register. The configuration address register oniy latches data when the host
processor 313 perfiorrns a full thirty two bit write to the register. Any eight or
25 sixteen bit access within this double word wiii be passed directly on to the
PCI bus as an eight or sixteen bit PCI inpuVoutput ~cces.s
Each bridge 4~7 419 includes a set of configuration ~e-JisLe~ si~l~"g
with it s assigned range of two hundred and fifty six configuration lo~lions to
perrnit tailoring of the bridge s functionality. The first sixty four configuration
30 registers are set aside for a predefined configuration header 701 including adevice ide.,li~ic~lion a vendor idenliric~li~ a status register and a co."",a,ld
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register. Bit one o~ the co,~",.and register is set to enable memory access
such that the PCI bridge will respond to PCI memo~y accesses. An eight bit
register 702 contains a number for the respective secondary PCi bus
assigned by the configuration instructions. A system re-set clears this
register whereafter reconfiguration by the configuration instructions is
required in order to re-esphlish functionality.
Commandlstatus register 703 provides for selection of operational
chara~ lics. With bit two of this byte set the bridge is unable to respond
as memory on it s second bus. I~/lemory base address 707 and memory limit
10 address 705 are specified to define a range o~ memory addresses which
when generated on the primary bus 413, will result in a response being made
by the respective PCI bridge. Thus, this range of addresses identifies a non-
addressable range which allows the control processor to command
instructions to the disc array 203. Similarly ",el"ory ~ccesses outside this
15 specified range are ignored by the bridge thereby providing the required
isolation between the primary and secondary buses.
The PCi bridges are configured to aliow processing unit 414 to issue
co",n,and instructions to the network card 412 the application card 413 and
the disc card 411 within a limited range of memory space. Consequently the
20 PCI bridges are not avaiiable for the transfer of image data between the
secondary buses and the primary bus and a transfer of this type must take
place via the router 4û2.
Color-space converter 403 is detaiied in Figure 8 and includes a
conventional digital converter matrix 801. The converter matrix 801 receives
25 each input sample multiplies samples by stored co~rl~cienls and then adds
appropriate components in order to effect a color-space conversion. Thus in
typical a~ lic~lions conversions are effected between YUV represe.,L~lions
of color and similar RGB represe, ll~lions.
The conversion process is col,~lic~L~d by the fact that U and V color
30 difference signals are often conveyed at a lower sampiing rate and their
associated Y component while RGB samples are prod- Iced at a rate
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compatible with said Y samples. Digital video signais having reduced
bandwidth color components are often designated 4:2:2 to distinguish them
from equally sampted components, represented as 4:4:4. The converter
matrix 801 is configured to receive and produce samples in accordance with
the 4:4:4 standard, therefore it is necessary to effect up-sampling or down-
sampling of the color difference signals either on the input to the converter
matrix or the output of the converter matrix, depending on the direction of
conversion taking place. To avoid the need to dll,r~lic~t~d converter circuitry,the color-space converter 403 is provided with a programable gate array,
10 such as the 3K device manufactured by Xilinx of San Jose, Califomia, USA.
The converter 403 includes a sample converter 803 arranged to up-
sample U and V components to produce RGB samples or to down-sample
RGB components to produce Y, U and V output samples. Y samples do not
require down-conversion therefore the sample converter 803 also includes a
15 delay device configured so as to n~ai"l~il, the Y samples in phase with down-sampled U and V components. An input from the router 402 is supplied to
gate array 802 over an input bus 804. If the input saio~-les are in RGB forrnat,the gate array 802 is instructed, over a control channel 805, to direct said
samples to the converter matrix 801. The converter matrix 801 converts the
20 RG8 samples to YUV samples which are in tum retumed to the gate array
802 via bus 806. Upon receiving these sa,l ,:1 s over bus 806, the gate array
directs said samples to the sample converter 803 which re~ ces the rate of
the U and V sa"l~,les to produce sa.~ s falling within the accepted 4:2:2
protocol on an input bus 807. The gate array receives input samples on bus
25 807 and directs these to an output bus 808 which is in tum di~ected to the
router 402.
Alternatively, the color-space converter 403 may be config~red to
convert YUV samples to RGB samples. The ~ate array 802 is instructed, via
control channel 805, to the effect that it will be receiving YUV sal"rlos The
30 incoming YUV samples on bus 804 are firstly directed to the sample
converter 803 which up-samples the U and V col"l~ooenl~ to produce 4:4:4
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YUV samples which are retumed to the gate array 802 on input bus 807.
Within the gate array 802, said input samples are directed to the converter
~ matrix 801, arranged to generate RGB representations of these samples
which are in turn returned to the gate array 802 by input bus 806. Within gate
5 array 802, the samples received on bus 80~ are directed to the output bus
808. Thus, it can be appreciated that the gate array 802 allows samples to be
directed to both the converter matrix 801 and the sample converter 803 in
either order.
Proxy generator 404 is detailed in Figure 9. Data is supplied from the
10 router 402 to the proxy generator 404 over thirty-~No bit bus 901, consistingof eight bits allocated for the red component, eight bits ~lloc~ted for the green
component, eight bits allocated to the blue component and eight bits
allocated to a control channel also known as a keying channel or an alpha
channel. Bandwidth reduction of the control channel does not have meaning,
15 therefore the eight bit red, green and blue components are supplied to
respective pre-filters 902, 903, 904 and the control bus is effectively
terrninated at 905.
The pre-filters provide bandwidth reduction for relatively large images,
such as those derived from cinematographic film. When broadcast video
20 signals are received, no pre-filtering is neces~ry and bandwidth reduction ispel ru, l l ,ed exclusively by a re-sizing device 905 which, in the preferred
embodiment, is a GM 833X3 acuit,v re-sizing engine manufactured by
Genesis Micluulli~, Inc. of Ontario Canada.
The re-sizir.y device 905 reccives data over lir,es ;,06 and 907
25 specifying source image size and target image size respectively. Outputs
from pre-filters 902, 903 and 904 are supplied to respective buffering devices
908, 909 and 910. Each buffering device includes a pair of synchronised field
buffers, such that a first field buffer 911 is arranged to receive a fieid of data
from pre-filter 902 while a second field buffer 912 supplies the previous field
30 to the ba ndvJidll . reliuction device 905.
Bandwidth reduction device 905 receives outr-t~ from each of the
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buffering devices 908, 909, 910 and effects bandwidth reduction upon each
of the red, green and blue components in response to the programed
reduction size. In this way, the bandwidth reduction device has access to the
data stored in one of the field buffers, representing the source buffer
throughout a field period. Similarly, throughout this period output values for
red, green and blue components are supplied to respective output buffering
devices 913, 914 and 915. Again, each output buffering device includes a
pair of co-ope~ating field buffers 916 and 917.
The outputs from the buffering devices 913, 914 and 915 are
reassembled into a thirty-two bit output bus 916, with its eight bit control
bytes effectively set to nil.
The re-formatters 406 and 40~ are implemented primarily using log;c
cell arrays, such as the Xilinx XE3000. The devices are field programmable
gate arrays configured to replace conventional TTL Logic's devices and
1~ sirnilar devices which integrate complete subsystems into a single
integrated package. In this way, a plurality of packing and unpacking
configurations may be programmed within the device which are then
selectable, in response to commands issued by the control processor 412,
for a particular packing or unpacking application.
User logic functions and interconnections are deterrrlined by
configuration ,~ruy,~m data stored in internal static l~el~GI~/ cells. This
program data is itself loaded in any of several available modes, thereby
accommodating various system requirements. Thus, programs re~uired to
drive the devices may permanentiy reside in ROM, on an ~prlic~tiQn circuit
board or on a disk drive. On chip initiAli7~tion logic provides for automatic
loading of program data at power-up. Alternatively, the circuit may be
associated with an XC17X>( chip available from the. same soi~rce, to
provide serial configuration storage in a one-time ,uru~dr,,,,,able pac~age.
Within the device, block logic functions are implemented by
programmed look-up tables and functional options are imple" ,e, lled by
pruyldl~, controlled multiplsxes. Interconnecting networks between blocks
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are implemented with metal segments joined by program controlled pass
transistors.
Functions are established via a configuration program which is
loaded into an internal distributed array of configuration memory cells. The
configuration program is loaded into the device at power-up and may be re-
loaded on command. The loglc cell array includes logic and control signals
to implement automatic or passive configuration and program data may be
either bit serial or byte parallel.
The static memory cell used for the configuration memory and the
logic cell array provides high reliability and noise immunity. The integrity of
the device configuration is assured even under adverse condition. Static
memory provides a good combination of high density, high performance,
high reliability and comprehensive testability. The basic memory cell
consists of two CMOS inverters plus a pass transistor used for writing and
1~ reading cell data. The cell is only written during configuration and only read
during read-back. During normal operation the celi provides continuous
control and the pass transistor is off and does not affect cell stability. This is
quite different from the operation of conventional memory devices, in which
the cells are frequently read and rewritten.
An array of configurable logic blocks provide the functional elements
from which the packing and unpacking logic is constructed. The logic blocks
are arranged in a matrix so that 64 blocks are arranged in 8 rows and 8
columns. Development software available from the manufacturer facilitates
a compilation of configuration data which is then downloaded to the internal
configuration memory to define the operation and interconnection of each
block. Thus, user definition of the configurable logic blocks and their
interconnecting networks may be done by automatic translation from a
schematic logic diay,~l" or optionally by installing a library of user callable
" ,a~,us.
Eacn configurable logic block has a combinational logic section, two
bistables and an internal control section. There are five logic inputs, a
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24
common clock input, an asychronus reset input and an enable clock. All of
these may be driven from the interconnect resources adjacent to the blocks
and each configura~le iogic block also has two outputs which may drive
interconnected networks.
Data input from either bistable within a togic block is supplied from
function outputs of the combinational logic or from a block input. Both
bistables in each logic block share asynchronus inputs which, when
enabled and high, are dominant over clocked inputs.
The combinational logic portion of the logic block uses a 32 by 1 bit
10 lookup table to implement Boolean functions. Variables selected from the
five logic inputs and two internal clock bistables are used as table address
inputs. The combinational propagation delay through the networ~ is
independent of the logic function generated and is spi~e free for single
input variable changes. This technique can generate two independent logic
15 functions of up to four variables.
Proyr~ ,abie interconnection resources in the logic cell array
provide routing paths to connect inputs and outputs into logic networks.
Interconnections between blocks are composed of a two layer grid of metal
segments. Pass transistors, each controlled by a configuration bit, form
20 programmable interconnection points and switching matrix's used to
implement the necessary connections between selected metal segments
and block pins.
The re-~,luy,dlllable nature of the device as used within the
,~r~ llil,g circuit 406 results in the actual functionality of these devices
2~ being re-configurable in response to down-loaded instructions. The devices
essentially cGIlsi~l of many It:yi:iL~ and as such provide an environment in
which the . ~rul 1 . Idl.lil 19 links may be effectively "hard-wired" in ~ f~ . Ice to
being asselllbled from the plurality of m~lfirleYi~lg devices.
An example of the functionality within ~~foll-,dlli.lg device 406 is
30 illu:jl,dLad in Figure 10. Input signals from router 402 are supplied to a width
selec~or 1001, arranged to separdle RGB sub-words into eight bit
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representations, ten bit representations or twelve bit representations. Eight bit
representations are supplied to a packing circuit 1002, ten bit sub-words are
- supplied to a packing circuit 1003 and twelve bit sub-words are supplied to a
packing circuit 1004. Packing consists of removing redundant data from a
5 thirty-two bit input word so as to optimise the available storage. In par~icular,
video data usually includes a control or alpha channel whereas computer
data is usually stored in ~Gr~ format without such an alpha channel.
Twelve bit representations of RGE3 supplied to packer 1004 may be
packf~d as ten or eight bit representations. Ten bit words supplied to packer
10 1003 may be packed as eight bit representations and eight bit RGB alpha
words supplied to paclcer 1002 may be packed as eight bit RGB, with the
alpha inrul",~lion removed.
A particular packer output, from packer 1002, 1003 or 1004 is selected
by a multiplex 1005 and supplied to bi-directional bus 1006, which in tum
15 communicates with the dislc buffer 408.
Input signals from disk buffer 408 are surplied to a width-modifying
circuit 1007, which in turn supplies eight bit represe"L~liG"s to unpacking
circuit 1008. Circuit 1008 effectively provides a reverse process to that
effected by packing circuit 1002, re-spacing the eight bit representations such
20 that each thirty-two bit word conlaios a single sample with eight bits allocated
for the alpha ch~ lel. This unpacked i~ru~ lion is then supplied to the
router 402.
An example of the fun.;liu"alil~/ provided by packing circuit 1002 is
illustrated in Figure 11. All configurable outputs are predefined within the
25 prtJy~ dl 1111 ,abla array and are then selected by means and mulitplexing
means. The array is reconfigurable and if new rollnaLs are required for a
particular ~ ,lic;,Lion, suitable reconfiguring procedures may be
implemented.
The paclcing ,u~cedure illustrated in Figure 11 consisl~ of receiving
30 thirty-two bit words cons;;jli"g ûf eight bit sub-words for the red, green, blue
and alpha components. These are paclced such that only the red, green and
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blue information is retained, with the alpha information being disregarded.
The packing process makes use of two thirty-two bit registers 1101
and 1102. Three registers 1103, 1104 and 1105 are provided to produce
output words in RG~R format, this being an arrangement which is
implemented within the open GL environment of siiicon graphics. A further
three registers 1106, 1107 and 1108 pack the data in GBRG forrnat, which
represents a preferred arrangement for applications operating within the GL
environment.
Input data words from circuit 1001 are clocked through registers 1101
10 and 1102, such that a first word, represented by components R1, G1, B1 and
A1 is loaded to register 11 01 , with the second word, represented by
components R2, G2, B2 and A~2 being loaded to register 1 102. The
prograi"able array is configured such that the first location of register 11a1,
representing component R1, is transferred to the first location of register
15 1103. Similarly, the data within the second location of 1101 is transferred to
the second location of register 1103 and data within the third locaLio" of
register 1101 is transferred to the third location of register 1103. C)ata in the
fourth location of register 1101 is ignored and the fourth location of register
1103 is received from the first location of register 1102. The first location of20 re~,sler 1 104 receives data from the second location of register 1 102.
Similarly, data is read from the third iocation of register 1102 to provide an
input to the second location of register 1104. The fourth location of register
1102 is ignored, therefore all of the data retained within registers 1101 and
1102 has been processed. Consequently, new data Is loaded such that
25 register 1101 now contains components R3, (;3, B3 and A3, while register
1 102 contains col"yo"ents R4, G4, B4 and A4. Output registers 1103, 1104
and 1105 are half full and the output from the first location of registe~ 1101 is
transferred to the third loc~lioll of register 1104. The output from th~3 secondlocation of register 1101 is transferred to the fourth loc~Lion of register 110430 and the 1irst localio" of r~yi-~1~r 1105 receives data from the third location of
register 1101. Data from the first IGc~lioll of r~yi~ler 1102 is transferred to the
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second location of register 110~, data from the second location of re~ister
1102 is transferred to the third location of register 1105 and the fourth
location of register 1 105 receives data from the third location of register 1 102.
The output registers are now full, all of the data has been read from the input
registers 1101, 1102 and the transfer cycle is therefore complete.
A simiiar procedure is performed in order to simultaneously write data
to output registers 1106, 1107 and 1108. On this occasion, the first location
of register 110~ receives data from the second location of register 1101.
Similariy, the second location of register 1106 receives data from the third
iocation of register 1101 and the firstlocation of register 1101 supplies data
to the third location of register 11û6. This procedure continues in a similar
fashion to that described previously, so as to fill registers 11û6, 1107 and
1108 with data following the GBRG format.
Outputs from register 1103 are supplied to a m~litpl~cor 1109, which
1~ also receives outputs from register 1106. A selection signal is supplied to the
multiplexor on line 1112, resulting in the RGBR data from register 1103 or the
Gi3RG data from register 1106 being supplied to multiplexor 100~. Similariy,
outputs from register 1104 and outputs from register 1107 are supplied to a
multiplexor 1 1 10 which again supplies a particular output to multiplexor 1005
in response to a selection signal su~Piied on line 1113. Finally, the outputs
from register 1105 and register 1108 are suppli~cl to a third multiplexor 1111
which again receives a selection signa~ on a line 1114 so as to provide one of
said outputs to m~ ir lexor 1005.
~acked data from r~ru~ lg circuit 4û6 is supplied sequentially to
dis~ buffer 4û8. The disk buffer 4Q8 includes two complete frame buffers to
provide conversion between field based ll dl ISI I ~-55io~, and frame based
trans",.ssioll. Furtherrnore, when receiving data from interface card 411, said
data may be addressed randomly to one of said frame buffers while the other
of said buffers is read sequentially tosupply data to the refor",dlli"g circuit
4û6.
Each frame within the disk buffer 408 is striped with each disk within
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the disk array receiving one of said stripes. Preferably, a broadcast video
frame is divided into eleven stripes and the twelfth drive of the array receivesparity illru~ dLiol' from the parity circuit 410. The SSA adapter will provide
data to the effect that a disk drive within the array has failed, whereafter
5 parit,v data received from the disk array is used to reconstitute the "lissinginforrnation by XORing the said parity inforrnation with the XORed ~otal of the
remaining stripes.
Network buffer 409 also includes two complete frame buffers, again
enabling the network side of the bu~er to transfer data in complete frames
10 while allowing field based transmission on the other side of said buffer. Full
transmissions through network buffer 409 occur se~uentially and there is no
need to inc!ude parity c~c~ tin9 circuits.
~ he nature of the network buffer 409 and the disk buffer 408 allows
data to be l,ans~liLLed in a randomly addressed mode of operation using
conventional PCI protocols operating over buses 416, 415 and 418 in
combination with bridges 417 and 419. Similarly, the buffers also allow
synchronous field by field tra.,sn~.ssion to be eKected through the router 402
and its associated circuits. In this way, the processing system 202 provides
compatible interfaces to both the addressed environment 203 and the video
20 environment 204, with llan:jrt:r:j between these envi,our"el,Ls occurring at
video rate or at a rate higher than video rate.
SUBSTITUTE SHEET (RULE 26)
