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Patent 2244126 Summary

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Claims and Abstract availability

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(12) Patent: (11) CA 2244126
(54) English Title: PROCEDURE AND DEVICE FOR LOADING INPUT DATA INTO AN ALGORITHM DURING AUTHENTICATION
(54) French Title: PROCEDE ET DISPOSITIF POUR CHARGER DES DONNEES D'ENTREE DANS UN ALGORITHME LORS D'UNE PROCEDURE D'AUTHENTIFICATION
Status: Term Expired - Post Grant Beyond Limit
Bibliographic Data
(51) International Patent Classification (IPC):
  • G06K 19/07 (2006.01)
  • G06Q 20/34 (2012.01)
  • G07F 07/10 (2006.01)
  • H04L 09/32 (2006.01)
(72) Inventors :
  • SCHAEFER-LORINSER, FRANK (Germany)
  • SCHEERHORN, ALFRED (Germany)
(73) Owners :
  • DEUTSCHE TELEKOM AG
(71) Applicants :
  • DEUTSCHE TELEKOM AG (Germany)
(74) Agent: SMART & BIGGAR LP
(74) Associate agent:
(45) Issued: 2006-10-10
(86) PCT Filing Date: 1997-06-04
(87) Open to Public Inspection: 1997-12-11
Examination requested: 2002-02-08
Availability of licence: N/A
Dedicated to the Public: N/A
(25) Language of filing: English

Patent Cooperation Treaty (PCT): Yes
(86) PCT Filing Number: PCT/EP1997/002894
(87) International Publication Number: EP1997002894
(85) National Entry: 1998-07-23

(30) Application Priority Data:
Application No. Country/Territory Date
196 22 533.7 (Germany) 1996-06-05

Abstracts

English Abstract


2.1 The problem with security in paying with chip cards is the loading of
input data into an
algorithm during authentication.
2.2 Separating the data blocks and switching; an additional feedback after the
post-connected
counters on and off at preselected times (number of clock pulses) helps to
improve the security
of debited and credited data.
2.3 The invention can be used for all authentication procedures where chip
cards are used.


French Abstract

La question de la sécurité des données dans les opérations de paiement à l'aide de cartes à puce est inhérente aux processus intervenant lors du chargement de données d'entrée dans un algorithme pendant la procédure d'authentification. Pour améliorer la sécurité des données de débit et de crédit, il est prévu une répartition des blocs de données et la connexion et la déconnexion d'une rétroaction après les compteurs intercalés à la suite à des périodes (cycles) prédéfinis. Cette invention peut s'utiliser dans toutes les procédures d'utilisation impliquant l'emploi de cartes à puce.

Claims

Note: Claims are shown in the official language in which they were submitted.


6
CLAIMS:
1. Process for loading input data into an algorithm
during the authentication between chip cards with purse
function and a security module, in which the card user has
access to a stored credit balance and in which, at each
transaction, the required cash amount or the cash amount
entered by the card user is deducted from the chip card of
the card user with the aid of a security function and the
cash amounts are summated and stored in a summator for cash
amounts of the security module, and in which a linear
feedback shift register is used for the authentication
algorithm, the nonlinear function of said shift register
being cryptographically reinforced in conjunction with
downstream counters, and in which input data, comprising a
random number, a secret key and non-secret card data, are
included in said algorithm, characterized in that the input
data are divided into a plurality of blocks of data and in
that, during the loading of the blocks into the linear
feedback shift register, an additional further feedback
circuit after the downstream counters is introduced into the
shift register and is disconnected after a given number of
clock pulse steps.
2. Process according to claim 1, characterized in
that the card data with the secret key are introduced as a
first block and the random number is introduced as a further
block.
3. Process according to claims 1 and 2, characterized
in that, during the loading phase of the input data,
different counts are used than in the following phase after
loading in of the input data for calculation of the
authentication token.

7
4. Process according to claims 1 and 2, characterized
in that the first downstream counter counts to 1.
5. Process according to claims 1 and 2, characterized
in that the counters and the number of clock pulses to be
executed are selected precisely such that the authentication
token is calculated after a number of clock pulses fixed by
other system conditions.
6. Process according to any one of claims 1 to 5,
characterized in that the output of bits begins after all
the input data have been loaded in.
7. Process according to any one of claims 1 to 6,
characterized in that, between the loading in of the blocks
from claim 1 and with the additional feedback being
maintained, the entire circuit arrangement is clocked a few
steps further without input data being loaded and before
bits are output.
8. Process according to any one of claims 1 to 6,
characterized in that, between the loading in of the blocks
from claim 1 and after the additional feedback has been
disconnected, the entire circuit arrangement is clocked a
certain number of steps further without input data being
loaded and before bits are output.
9. Device for loading input data into an algorithm
during authentication using a cryptographic MAC function,
consisting of a linear feedback shift register with a
nonlinear feed forward function which picks off the shift
register and, via a counter, influences the output of the
shift register which is followed by a further counter,
characterized in that, for use for the authentication
algorithm, the circuit arrangement composed of the linear
feedback shift register with downstream counters is

8
cryptographically reinforced by an additional disconnectable
nonlinear feedback circuit.
10. Device according to claim 9, characterized in that
the additional feedback is picked off after the first
downstream counter before a latch.
11. Device according to claim 9, characterized in that
the additional feedback is picked off from a latch after the
first downstream counter.
12. Device according to claim 9, characterized in that
the additional feedback is picked off after the second
downstream counter.
13. Device according to claim 9, characterized in that
the additional feedback is in the form of an XOR sum of the
pick-offs after the first downstream counter before a latch,
from the latch after the first stream downstream counter and
after the second downstream counter.
14. Device according to claim 9, characterized in that
the counters are divided or reduced in size.

Description

Note: Descriptions are shown in the official language in which they were submitted.


CA 02244126 2005-O1-05
28.030-19
1
Procedure and device used to load input data during
authentication into an algorithm
Description:
The invention relates to a procedure as described
in detail in claim 1, and to a device of the kind defined in
claim 9. Several procedures of this kind are known and are
used for various kinds of electronic cash cards, while the
devices are digital circuits for chips according to
EP 0 616 429 A1.
Procedures of the kind referred to here are, for
example, known from ETSI D/EN/TE 090114, Terminal Equipment
(TE) Requirements for IC cards and terminals for
telecommunication use, Part 4 - Payment methods, version 4,
of 7 February 1992, and from the European patent
application 0 605 070.
In addition to telephone cards with a defined
value (starting credit), which are used for card phones,
there are also electronic cash cards with similar
functionality used for paying small amounts; these cash
cards are of increasing importance. For the "pay with chip
card" event, a card reader module and security module (SM)
for verifying the card and the credit amount are integrated
in the equipment.
EP 0 605 070 A2 also describes a procedure to
transfer (credit and debit) money amounts to and from chip
cards whereby overridable memory locations of a chip card
are divided into at least two memory locations, one of which
is used for debiting amounts (i.e. electronic cash card),
similar to telephone cards, and the other one is used for
crediting amounts, similar to a credit card. With the

CA 02244126 2005-O1-05
28.030-19
2
normal security conditions applied, it is planned to
transfer amounts between these two areas in order to refill
the electronic cash card.
In order to avoid that unauthorized persons access
a card reader and its built-in security module, and that
specially protected, and consequently expensive (for the
operator) dedicated lines have to be installed, a procedure
(P95114) has been suggested whereby the operator of the card
reader inserts a security module with chip card function
into the card reader before any pay event. Tnlhen a
cardholder inserts his or her electronic cash card into the
card reader, data areas of the chip card are read out so
that the card can be verified and the remaining credit
amount be checked. Next, authentication with the security
module, and one or several acceptance checks are carried
out. Finally, the due amount or entered amount is debited
to the cardholder's chip card using a security function, and
added to the sum counter for money amounts in the security
module. After such pay events, the counter setting of the
security module is transmitted to a billing center.
The purpose of the invention is to increase the
security of card readers for electronic cash cards with
regard to manipulation and defects.
In accordance with one aspect of this invention,
there is provided a process for loading input data into an
algorithm during the authentication between chip cards with
purse function and a security module, in which the card user
has access to a stored credit balance and in which, at each
transaction, the required cash amount or the cash amount
entered by the card user is deducted from the chip card of

CA 02244126 2005-O1-05
28030-19
3
the card user with the aid of a security function and the
cash amounts are summated and stored in a summator for cash
amounts of the security module, and in which a linear
feedback shift register is used for the authentication
algorithm, the nonlinear function of said shift register
being cryptographically reinforced in conjunction with
downstream counters, and in which input data, comprising a
random number, a secret key and non-secret card data, are
included in said algorithm, characterized in that the input
data are divided into a plurality of blocks of data and in
that, during the loading of the blocks into the linear
feedback shift register, an additional further feedback
circuit after the downstream counters is introduced into the
shift register and is disconnected after a given number of
clock pulse steps.
In accordance with another aspect of this
invention, there is provided a device for loading input data
into an algorithm during authentication using a
cryptographic MAC function, consisting of a linear feedback
shift register with a nonlinear feed forward function which
picks off the shift register and, via a counter, influences
the output of the shift register which is followed by a
further counter, characterized in that, for use for the
authentication algorithm, the circuit arrangement composed
of the linear feedback shift register with downstream
counters is cryptographically reinforced by an additional
disconnectable nonlinear feedback circuit.
The invention, including its effects, advantages
and fields of application, is described in detail by the
following examples.
Authentication algorithms are typically used for
identification security. In authentication procedures,

CA 02244126 2005-O1-05
28030-19
4
however, other data plays a role in addition to the identity
of chip cards and persons and possibly a security module
(SM); the correctness of this other data must be ensured.
An authentication procedure can be used, for example, with
non-secret card data (D) with a secret key (K) and a random
number (R). For electronic cash cards, separate security
functions are used for debits and credits, each of which is
checked with a cryptographic checksum.
The invented procedure can be used to carry out
debit and credit transactions using a cryptographic token,
provided that authentication and cryptographic checksum are
carried out via the counter setting and using a
challenge/response procedure. In this case, a single
challenge/response procedure, whereby only one random number
is provided by the security module (SM) and only one
response is calculated by the chip card, can prove both the
identity (authentication) and the internal counter setting
to the security module.
To achieve this, the variable input data, such as
the counter setting and the random number, are initially
processed internally with "keyed hash functions" - MAC
functions, whereby the card-specific secret key of the chip
card is used as key. The tokens resulting from counter
setting and random number can then be associated, for
example, (in a perhaps cryptographically unsecure way) by
XOR or a linear-feedback shift register, and subsequently be
output, with protected data integrity, with a sufficient
cryptographic function.
This procedure is of practical use insofar as the
keyed hash functions, which are only used internally, do not
have to meet particularly high requirements with regard to

CA 02244126 2005-O1-05
28030-19
their security; also, relatively simple functions can be
used since the results of these functions do not "leave" the
chip card. Data manipulation, however, is effectively
prevented.
5 The example for the invention assumes that a
linear-feedback shift register (LFSR) with additional
nonlinear function and post-connected counters is used:
0. Additional feedback circuits are applied after the post-
connected counters in the LFSR.
1. Input data, consisting of the non-secret card data (D)
and the secret key (K) is read into the LFSR while both the
feedback of the LFSR and the additional feedback(s) are
active.
2. A certain number of clock pulses occurs without input
data being read in.
3. Input data consisting of the random number (R) is read
in while both the feedback of the LFSR and the additional
feedback(s) are active.
4. The additional feedback circuits are switched off, and
the counters are reset, if necessary.
5. A certain number of clock pulses occurs, and during
these pulses, output bits are generated according to the
current counter settings.

Representative Drawing

Sorry, the representative drawing for patent document number 2244126 was not found.

Administrative Status

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Event History

Description Date
Inactive: Expired (new Act pat) 2017-06-04
Inactive: IPC deactivated 2012-01-07
Inactive: IPC from PCS 2012-01-01
Inactive: IPC expired 2012-01-01
Inactive: IPC removed 2011-08-09
Inactive: IPC assigned 2011-08-09
Inactive: IPC removed 2011-08-09
Inactive: IPC assigned 2011-08-09
Inactive: IPC removed 2011-08-09
Inactive: First IPC assigned 2011-08-09
Inactive: Late MF processed 2008-08-25
Letter Sent 2008-06-04
Inactive: Late MF processed 2007-06-14
Letter Sent 2007-06-04
Grant by Issuance 2006-10-10
Inactive: Cover page published 2006-10-09
Pre-grant 2006-07-18
Inactive: Final fee received 2006-07-18
Notice of Allowance is Issued 2006-06-28
Letter Sent 2006-06-28
Notice of Allowance is Issued 2006-06-28
Inactive: Approved for allowance (AFA) 2006-06-01
Inactive: IPC from MCD 2006-03-12
Inactive: IPC from MCD 2006-03-12
Amendment Received - Voluntary Amendment 2005-10-06
Inactive: S.30(2) Rules - Examiner requisition 2005-07-18
Amendment Received - Voluntary Amendment 2005-01-05
Inactive: S.30(2) Rules - Examiner requisition 2004-07-05
Amendment Received - Voluntary Amendment 2002-03-20
Letter Sent 2002-03-18
Request for Examination Received 2002-02-08
Request for Examination Requirements Determined Compliant 2002-02-08
All Requirements for Examination Determined Compliant 2002-02-08
Inactive: Correspondence - Transfer 1998-10-29
Classification Modified 1998-10-19
Inactive: First IPC assigned 1998-10-19
Inactive: IPC assigned 1998-10-19
Inactive: IPC assigned 1998-10-19
Inactive: IPC assigned 1998-10-19
Inactive: Courtesy letter - Evidence 1998-10-06
Inactive: Notice - National entry - No RFE 1998-10-02
Application Received - PCT 1998-09-28
Inactive: Single transfer 1998-09-28
Application Published (Open to Public Inspection) 1997-12-11

Abandonment History

There is no abandonment history.

Maintenance Fee

The last payment was received on 2006-05-23

Note : If the full payment has not been received on or before the date indicated, a further fee may be required which may be one of the following

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  • the late payment fee; or
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Owners on Record

Note: Records showing the ownership history in alphabetical order.

Current Owners on Record
DEUTSCHE TELEKOM AG
Past Owners on Record
ALFRED SCHEERHORN
FRANK SCHAEFER-LORINSER
Past Owners that do not appear in the "Owners on Record" listing will appear in other documentation within the application.
Documents

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Document
Description 
Date
(yyyy-mm-dd) 
Number of pages   Size of Image (KB) 
Abstract 1998-07-22 1 14
Description 1998-07-22 2 141
Claims 1998-07-22 2 91
Description 2005-01-04 5 194
Claims 2005-01-04 3 106
Claims 2005-10-05 3 107
Notice of National Entry 1998-10-01 1 192
Reminder of maintenance fee due 1999-02-07 1 110
Courtesy - Certificate of registration (related document(s)) 1998-12-03 1 114
Courtesy - Certificate of registration (related document(s)) 1998-12-03 1 114
Reminder - Request for Examination 2002-02-04 1 117
Acknowledgement of Request for Examination 2002-03-17 1 180
Commissioner's Notice - Application Found Allowable 2006-06-27 1 162
Maintenance Fee Notice 2007-07-02 1 173
Late Payment Acknowledgement 2007-07-02 1 166
Late Payment Acknowledgement 2007-07-02 1 166
Maintenance Fee Notice 2008-07-15 1 171
Late Payment Acknowledgement 2008-09-09 1 164
Correspondence 1998-10-05 1 31
PCT 1998-07-15 9 447
PCT 1998-07-22 19 621
PCT 1998-11-15 6 180
Correspondence 2006-07-17 1 38