Note: Descriptions are shown in the official language in which they were submitted.
- ' CA 02250554 1998-10-29 ~ ~f~ 7~tl 1 1 ~ 1
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3 ~; 'J ~
TFUUNSCEI~nER ALPPAJU~TUS E~P~DYING WIDEEAIND FFT CHP~ T-TZER AIID
INnnERSE FFT COhoBINER FOR M ~ TICH~U~-~T~ CO~DM ~ ICATION NE ~ ORK
FIELD OF THE INVENTION
The present invention relates in general to wireless (e.g.
cellular and personal communication systems (PCS))
communication networks and is particularly directed to a new
and improved transceiver apparatus, a receiver section of which
contains a wideband, Fast Fourier transform based (FFT)
channelizer to extract multiple channels from a digitized
intermediate frequency (IF) signal, and a transmitter section
of which contains a wideband inverse FFT based combiner to
combine multiple digitized baseband channels into a single IF
signal for transmission.
BACRGROUND OF THE INVENTION
In order to provide multi-channel voice and data
communications over a broad geographical area, wireless (e.g.
cellular) communication service providers currently install
transceiver base-stations in protected and maintainable
facilities (e.g. buildings). Because of the substantial amount
of hardware currently employed to implement the signal
processing equipment for a single cellular channel, each base-
! station is typically configured to provide multichannel
communication capability for only a limited portion of the
frequency spectrum that is available to the service provider.
A typical base-station may contain three to five racks of
equipment which house multiple sets of discrete receiver and
transmitter signal processing components in order to service a
prescribed portion (e.g. 48) of the total number (e.g. 400-
30KHz) channels within an available (e.g. 12 MHz) bandwidth.
The receiver section of a typical one of a base-station's
plurality (e.g. 48) of narrowband ~30KHz) channel units is
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diagrammatically illustrated in Fig. 1 as comprising a
dedicated set of signal processing components, including a
~- front end, down-conversion section 10, an intermediate
frequency (IF) section 20 and a baseband section 30.
~ Front end section 10 is comprised of a low noise amplifier
11 to which the antenna at the transceiver site is coupled, a
radio frequency-to-intermediate frequency (RF-IF) down-
converting mixer 13 and an associated IF local oscillator 15,
while IF section 20 is comprised of a bandpass filter 21 to
o which the output of mixer 13 is coupled, an amplifier 23, an
IF-baseband mixer 25 and an associated baseband local
oscillator 27. Bandpass filter 21 may have a bandwidth of 100
KHz centered at a respective one of the 400-30KHz sub-portions
of a 10 MHz wide cellular voice/data communication band,
diagrammatically illustrated in the multi-channel spectral
distribution plot of Fig. 2.
Baseband section 30 contains a lowpass (anti-aliasing)
filter 31, an analog-to-digital (A-D) converter 33, a digital
signal processing unit 35 which functions as a demodulator and
error corrector, and an associated telephony (e.g Tl carrier)
unit 37 through which the processed channel signals are coupled
to attendant telephony system equipment. The sampling rate of
the A-D converter 33 is typically on the order of 75
kilosamples/sec. The narrowband channel signal as digitized by
s A-D converter 33 is demodulated by digital signal processing
unit 35 to recover the embedded voice/data signal for
application to telephony carrier unit 37. (A similar dedicated
signal processing transmitter section, complementary to the
receiver section, is coupled to receive a digital feed from the
telephony system equipment and output an up-converted RF signal
to the transceiver site's antenna.)
For a typical urban service area, in order to optimize
service coverage within the entire bandwidth (e.g. 10 - 12 MHz)
available to the service provider and to ensure non-interfering
coverage among dispersed transceiver sites at which the base-
stations are located, cellular transceiver sites are
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customarily geographically distributed in mutually contiguous
hex-cells (arranged in a seven cell set). Thus, each cell has
its own limited capacity multi-rack base-station that serves a
respectively different subset of the available (400) channels,
s whereby, over a broad geographical area, the frequency
allocation within respective cells-and the separation between
adjacent cell set~ may be prescribed to effectively prevent
mutual interference among any of the channels of the network.
It will be readily appreciated that, since every channel
has components spread over multiple equipment racks, such as
those that make up a typical channel receiver section described
above with reference to Fig. 1, and thus the cost and labor in
geographically situating, installing and maintaining such
equipment are not insubstantial. Indeed, the service provider
15 would prefer to employ equipment that would be more flexible
both in terms of where it can be located and the extent of
available bandwidth coverage that a respective transceiver site
can provide. This is particularly true in non-urban areas,
where desired cellular coverage may be concentrated along a
20 highway, for which the limited capacity of a conventional 48
channel transceiver site would be inadequate, and where a
relatively large, secure and protective structure for the
multiple racks of equipment required is not necessarily readily
available.
SU~lMARY OF THE INVENTION
In accordance with the present invention, the limited
channel capacity and substantial hardware requirements
associated with signal processing architectures currently
30 employed by multichannel wireless communication service
providers, as described above, are effectively obviated by a
new and improved, relatively compact multichannel transceiver
apparatus that makes it possible to significantly reduce the
size and hardware complexity of a wireless (voice and data)
35 communication network transceiver site, so that the transcevier
may be readily physically accommodated at a variety of
CA 0 2 2 ~ 0 ~ ~ 4 l 9 9 8 - l O - 2 9~S
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installation sites, such as above the drop ceiling in an office
building or on an electric utility pole, while having the
~ capability of providing multichannel communication service
(e.g. greater than one hundred channels) that spans the entire
channel capacity offered by the service provider, rather than
only a subset of the available channels.
For this purpose, the transceiver apparatus of the present
invention contains a receiver section having a wideband
Discrete Fourier Transform (DFT) channelizer for processing
multiple channels of digitized received signals, and a
transmitter section which contains a wideband inverse DFT
combiner for processing multiple digitized transmit channel
signals. Pursuant to the preferred embodiment of the DFT
channelizer and DFT combiner, the discrete Fourier transform
may be implemented as, but is not restricted to, a Fast Fourier
transform (FFT), whereas the fast Fourier transform is an
efficient algorithm for computing the discrete Fourier
transform when the size of the transform is a power of two.
The multichannel receiver unit is operative to receive a
plurality of multiple frequency communication channels and
output digital signals representative of the contents of the
plurality of multiple frequency communication channels. A DFT-
based channelizer unit is coupled to receive the digital
signals output by the multichannel receiver unit and outputs
respective digital channel signals representative of the
contents of respective ones of the communication channels
received by the multichannel receiver unit. The respective
digital channel outputs are supplied to a first plurality of
digital signal processor units, respectively associated with
digital channel signals output by the channelizer unit, which
process (e.g. demodulate) respective ones of the digital
channel signals and supply processed ones of the digital
channel signals at respective output ports for distribution to
an attendant voice/data network.
On the transmit side, the transceiver includes a second
plurality of digital signal processor units, respectively
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associated with respective ones of a plurality of incoming
(voice/data) communication signals to be transmitted over
; respectively different frequency channels, and being operative
to process respective ones of the plurality of incoming
s communication signals and to supply processed ones of the
communication channel signals at respective output ports for
application of an inverse DFT processing combiner. The inverse
discrete Fourier transform-based combiner unit is coupled to
receive communication channel signals processed by the second
o plurality of digital signal processor units and outputs a
combined signal representative of the contents of the
communication channel signals processed by the second plurality
of digital signal processor units. A multichannel transmitter
unit is operative to transmit a multiple frequency
15 communication channel signal in accordance with the combined
signal output by the discrete Fourier transform-based combiner
unit.
In accordance with the invention the filter structures
employed in the transmit and receive paths are implemented as
20 overlap and add filter units or as polyphase filter units.
Pursuant to a first embodiment of the invention, the wideband
channelizer employs an overlap and add filter structure, to
which digitized data samples output by a high speed A-D
converter in the wideband receiver are applied. As received
5 data samples are fed to an input rate buffer, the data is
monitored by an amplitude monitor unit for the purpose of
providing gain control for the input signals and ensuring full
utilization of the dynamic range of the A-D converter. (For
this purpose, the output of the amplitude monitor unit is fed
30 back to the wideband receiver to control an attenuator that is
upstream of the A-D converter.)
When the rate buffer contains a block, of M samples, it
signals a control unit to begin processing a 'block, of M
samples of data. A ~block' of M samples of data is equal to
35 the decimation rate of the channelizer, which is given by the
nearest integer of the input sample rate divided by two times
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the complex channel sample rate. When the input sample rate is
large (on the order of 30MHz), a half band-filter may be
employed to reduce the clock rate of the data. The half band
filter performs a real-to-complex conversion of the data and
5 also decimates the data and clock rate by two. The clock
reduction is necessary to implement the filtering structure
with present day integrated circuits. If the input clock rate
were signifcantly lower or, as the processing capability of
future technologies increases, the half band filter may not be
o necessary. The M sample~ are clocked out of the rate buffer
into to a half band filter in bur~ts at a rate higher than the
input sample clock rate, in order to accommodate the size of
the FFT processor, which requires N samples, where N is greater
than M, which implies that the overlap and add filter must
operate at a clock rate faster than one-half the input sample
rate.
The complex data values from the half band filter are
clocked to a shift register employed within an overlap and add
filter. The overlap and add filter is a real valued low pass
20 filter with a cutoff frequency of one-half of the channel
bandwidth. The basic architecture of an overlap and add filter
is similar to that of a finite impulse response (FIR) filter.
However, the filter of the invention differs from a
conventional FIR filter by the use of feedback multiplexers and
5 long delay line elements between filter taps.
More particularly, the filter's shift register is
preferably implemented by cascading sets of delay memory units
with interleaved 'feedback' multiplexers. A respective tap
stage of the filter is formed of a pair of serially coupled
30 memory sections, a feedback multiplexer, a coefficient memory
and a coefficient multiplier. Each coefficient memory stores a
respective set of filter coefficients, the number of which
corresponds to the size of the FFT processor.
In an exemplary embodiment of the channelizer filter
35 structure, four filter tap stages may be employed. The outputs
of the multlpliers of the respective tap stages are summed
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together. Within a memory section, the length of an input
memory stage is equal to the decimation rate M; the length of
_- an output memory stage represents the filter 'overlap' and is
equal to N-M, where N is the size of the FFT processor.
~ In order to process each block of M input samples, N clock
signals are required to supply the FFT processor with a
sufficient number of data samples for FFT processing. During
the first M of the N clock signals, M samples are clocked
through a rate buffer and a half band filter and through the
o filter~s memory stages that effectively for a shift register.
During this time frame, data is shifted from left to right
through each of the memory sections of the shift register. For
the remaining N-M ones of the N data samples, data is not
clocked out of the rate buffer memory and there is no shifting
of data through the input memories of each tap stage. Namely,
data is not shifted through the shift register, as only the
output memories are clocked. This clocking of the output
memories is the mechanism used to effect the intended overlap
and add operation.
As respective sets of coefficient-weighted data samples
generated by the filter's tap stages are summed, they produce
an N-sample, aliased, convolved output data sequence, which is
stored in a RAM in preparation for application to an FFT
processor. In order to maintain throughput for high processing
rates, the FFT processor contains a plurality of FFT engines
that have been programmed with the proper FFT size associated
with the signal processing parameters of interest.
Implementing the FFT processor with plural engines maintains
data throughput as the processing time for a single engine is
typically longer than the time required to collect N samples
required for processing.
In accordance with a practical embodiment, the FFT engines
may employ a radix-4 (block floating point) algorithm having
FFT sizes that are a power of four. For a 512 point FFT
processor, production of all 512 frequency bins is carried out
by using two 256-point FFTs that are preceded by a decimation-
in-frequency radix-2 butterfly.
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For a 512-point FFT, the samples are read out of the RAM
_- and supplied to an arithmetic logic unit (ALU), which sums
successive pairs of even data samples and subtracts
~uccessive pairs of odd data samples. For even data sample
s processing, the ALU's output sum value is supplied directly to
FFT processor engines. For generating odd bins of a 512-point
FFT, as odd bin data samples are read out of the RAM, the
difference between data ~amples provided by the ALU is
multiplied by WN by a numerically controlled oscillator,
o modulator and clocked into the FFT processor.
Since the FFT engines employ a block floating point
algorithm (outputting a four bit scaling factor with the
complex FFT data), a scaling logic circuit is used to control a
barrel shift circuit, to which the output of the FFT'engine is
coupled. The barrel shift circuit ad~usts the data as it is
read out from the FFT engines in accordance w~th the scaling
factor, so as to ensure that consecutive FFTs are aligned to
the same scale. The output of barrel shift circuit is coupled
to an output RAM.
The output of the FFT processor must be multiplied by a
complex exponential WN , where M is the decimation rate, k is
the FFT bin number, and m is the FFT (block) number. To
execute an equivalent operation, the overlap and add
channelizer uses the identity xt(n-r)N] = FFT(WN *X[k]), where
x[n] i~ the FFT input sequence, and x[(n-r)N] is the circular
shift of xtn] by r modulo N, and causes the dual port output
RAM to be addressed in a manner that accesses processed data
values in an order that effects a circular shifting of the
FFT's input data sequence.
When FFT-processed data for each channel (frequency bin)
has been written into the output RAM, an attendant time
division multiplexed (TDM) bus interface circuit asserts the
data onto a TDM bus, so that it may be applied to digital
signal processors on the bus, which are operative to demodulate
and extract voice or data from the channel data. Data on the
TDM bus is preferably divided into a plurality of time slots.
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The bus connected processors are synchronized to the TDM bus by
a conventional framing signal, so that the processors will know
~ the correct time slot from which to read data.
The signal processing architecture of a multichannel
combiner, which is complementary to the wideband channelizer
having the overlap and add filter structure described above,
employs a custom TDM bus for collecting data for a large number
of channels at relatively high data rates, since the aggregate
data rate from all channels typically exceeds the bus bandwidth
o of standard bus protocols, (e.g. VMEbus).
The sources of the channelized (voice/data) signals that
are asserted onto the TDM bus are DSP processors that format
(e.g. to a cellular standard) and modulate incoming voice or
data ~ignals from an attendant telephone network, thereby
providing a baseband analytic signal. Each data source is
assigned one or more time slots during which it will transfer a
single complex sample when requested by the combiner. No two
sources can be allocated the same time slot. Time slots are
assigned by a system controller (a separate central processing
unit (CPU) on a VME bus) during system initialization. The
system controller also programs the combiner to specify all
times ~lots that contain valid data.
A sample from each DSP processor is requested via control
signals applied to the TDM bus from a TDM bus controller and
5 associated buffer/drivers. This sample is written into an
~~ input (RAM) buffer. The TDM bus controller synchronizes the
addressing of the RAM buffer to framing signals of the TDM bUS,
thereby insuring that each channel is written to the proper
address in t~e dual port RAM. When the combiner has collected
30 data from all operative channels, the TDM bus controller
couples control signals to an FFT control logic unit, causing
the FFT control logic unit to initiate FFT processing.
Complementary to the forward FFT processor functionality
of the overlap and add channelizer, the overlap and add
combiner causes an inverse FFT to be performed. In terms of a
practical implementation, generation of an inverse FFT is
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effected using a forward FFT. The FFT processor is configured
to have a size equal to the next 'power of two~ greater than
the number of channels to be combined. To maintain throughput,
the FFT processor contains a plurality of FFT engines that have
5 been programmed with the proper FFT size associated with the
signal processing parameters of interest. Implementing the FFT
processor with a plurality of engines maintains data throughput
as the processing time for a single engine is typically longer
than the time required to collect N samples required for
proces~ing.
Zeros are written sequentially into an FFT engine for a
prescribed (relatively limited) number of frequency bins. For
a subsequent plurality of bins, data may be read from an input
dual port RAM for the active channels. If the channel is not
an active channel, the control logic unit writes a zero into
that bin. The identities of those channels that are active are
programmed into the control logic unit during system
initialization. For the remaining (relatively limited) number
of bins, zeros are written into those bins.
In order to generate an inverse FFT using a forward FFT,
the following identity is used
x[n] = K~FFT(X[((-k))~],
where x[n] is the inverse FFT of X[k], n is the sample number,
k is the FFT bin number, X is the FFT size, and X[((-k) )R] iS
the reverse order of sequence X[k], by modulo K. By generating
a mirror of the input data to the FFT about bin 0, the forward
FFT becomes an inverse FFT scaled by the FFT size. The FFT
control logic unit addresses the input RAM in a reverse order
when writing data into the FFT engines.
As in the overlap and add channelizer, in order to
generate a 512-point FFT in the combiner architecture, the FFT
engines employ a radix-4 (block floating point) algorithm
having FFT sizes that are a power of four. Using a radix-2
decimation time butterfly, N~2-point FFTs are generated from
even and odd samples of the 512-point input sequence.
Multiplication of odd sample FFT data values is performed by a
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numerically controlled oscillator, modulator (NCOM). To
process the first 256 bins of a 512-point FFT, the output of a
first half of the dual port RAM is summed with the output of a
second half of the RAM by means of an ALU. For the second 256
s bins, the output of the two RAM halves are subtracted from each
other. To accommodate the propagation delay through the NCOM
and ensure that the proper pair of samples are processed by the
ALU, a set of delay registers are coupled in the output path
from the RAM to the ALU.
o The combiner algorithm requires that the input sequence of
the inverse FFT be multiplied by a complex exponential,
W kmR
where k is the input frequency bin, K is the inverse FFT size,
m is the inverse FFT number, R is the combiner's interpolation
rate, and
W e - j ~ 2 ~ n/R
Using a mathematical identity, this multiplication operation
can be effected by a circular rotation of the output samples of
the inverse FFT, i.e.:
x[(( n-r)) k ] = inverse FFT ( W~rk*x [ k]),
where r is equal to -mR. By rotating the inverse FFT output
samples by -mR, the phase shift of the complex exponential is
generated. This rotation is performed by the FFT output
addressing logic.
Since the FFT engines generate FFTs using a block-floating
point algorithm, which provides a scaling factor dependent upon
the characteristics of the input data, barrel shifting circuits
are coupled in the signal flow input paths to the ALU, in order
to adjust the FFT data to the same scale to properly align the
data for subsequent processing.
Like the channelizer, the overlap and add filter of the
combiner comprises a plurality of filter tap stages. The FFT
size and the number of stages set the overall length of the
filter. The filter is designed as a real low pass filter with
a cutoff frequency equal to one half the channel bandwidth. A
respective stage of the filter is formed of one or both of a
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pair of delay memory elements of a shift register, a feedback
multiplexer, a coefficient memory, a multiplier and an internal
adder. Each coefficient memory stores a respective set of N
filter (weighting) coefficients, the number of which
corresponds to the size of the FFT processor. The output of
the FFT processor from the ALU is distributed to multipliers of
all filter stages and multiplied by the coefficients of each
stage simultaneously. The outputs of a tap stage multiplier is
summed with data being accumulated and shifted through the
o delay memories in the tap stage adder for application to the
next stage of the filter.
The first filter tap stage of the filter does not require
an input delay memory section since zeros are shifted into the
first filter stage. The length of each delay memory is
determined by the filter interpolation rate, which is defined
in accordance with the channel and output sample rates. The
filter interpolation rate, R, is the nearest integer of the
quotient of the output and channel sample rates:
R = round (output sample rate/channel sample rate).
The length of each of the output delay memory sections is
R, while the length of each input delay memory section, also
known as the filter overlap, is given by:
overlap = (N-R).
The interpolation rate R also specifies the required
signal processing rate of the overlap and add filter. The
~~ minimum clock rate that the filter must process data to
maintain throughput is given by:
filter processing rate = output rate~N/R.
For every N samples output by the inverse FFT processor,
the overlap and add filter outputs R samples. For the first R
samples of each inverse FFT, a first input port through the
multiplexers is selected. During this time, all data is
clocked and summation values produced by an adder in the last
stage of the filter are input to a half band filter. For the
remaining N-R samples, a second port of each multiplexer is
selected, and the outputs of the internal adders of the
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respective stage are fed back to their delay memory sections.
During this time input memory sections are not shifted and the
- data from the adder in the last stage is not clocked into the
half band filter. Again, as in the overlap and add filter of
' the channelizer, the feedback of the last N-R samples provides
the filter overlap.
The half band filter is configured as an integrated
circuit that provides complex to real data conversion, which
doubles the output sample rate. Although the entirety of the
combiner could be implemented as a completely real system, this
would require all sample rates, processing rates and FFT sizes
to be doubled, increasing complexity and cost. A rate buffer
is coupled to the output of half band filter to allow a
continuous flow of data from the combiner. Data stored in the
rate buffer i8 coupled via an output driver unit to an output
data link for application to a D-A converter of the transmit
side of the transceiver site. A half full flag from the rate
buffer is supplied over a control signal line to a control
logic circuit, to indicate to the TDM bus interface unit when
to request data. When the quantity of data stored in the rate
buffer falls to less than half its capacity, the flag becomes
inactive, which signals the TDM bus interface to request
channel data from its active channels to maintain a continuous
flow of output data.
As in the overlap and channelizer architecture, respective
oscillators are provided for each output sample rate required.
A further set of logic circuits is included to generate
additional clock signals employed by the combiner. The clock
output of a high rate oscillator is divided down by counters to
generate the necessary filter processing clock, TDM bus clock,
and FFT engine system clock.
A second embodiment of the wideband channelizer of the
present invention is configured as a polyphase filter
structure. As in the overlap and add channelizer embodiment,
the architecture of an FFT-based polyphase filter bank analysis
(channelizer) system accepts real-time wide band IF
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(intermediate frequency) signals and performs frequency
translation and channelization to a number of individual narrow
baseband analytic signals. The polyphase filter channelizer
provides full programmable control of the system parameters via
5 a standard VmEbus interface (as defined by the Institute of
Electrical and Electronics Engineers (IEEE) standard Std 1014-
1987) and channelized data distribution over a custom, time
division multiplexed (TDM) data bus.
In the polyphase channelizer architecture, the input
sample rate is an integral multiple of the channel sample rate,
which implies that the channel sample rate must be a multiple
of the channel bandwidth. Channelized data is distributed by
the channelizer as analytic baseband signals. The
channelizer's input interfaces to the digital data output link
lS from an A-D converter of an upstream wide band digital
receiver. The input sample clock rate is determined by the
number of channels being received and the bandwidth of those
channels. As in the overlap and add embodiment, an amplitude
monitoring logic circuit monitors the input data, in order to
20 provide automatic gain control of the input signal, and insure
that the full dynamic range of the A-D converter in the
receiver is being utilized.
Input samples are clocked into a half band filter that
performs a real-to-complex conversion of the input data. The
5 half band filter also decimates the data by two, reducing the
clock rate of the data by half. The complex data samples are
then fed into a shift register of a polyphase filter,
specifically, clocked into a delay memory that forms a portion
of a shift register within a first filter stage. The length of
30 each delay memory is equal to the FFT size in the channelizer.
The output of each delay memory is applied to coefficient
multipliers which operate at a rate that is I times the clock
rate of shift register, where I is an oversampling factor of
two. This implies that each sample at the output of the delay
35 memories is multiplied to two (I=2) filter coefficients, prior
to being clocked into the next delay memory.
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In an exemplary embodiment of the polyphase filter
architecture, four filter stages are employed. The FFT size,
~ oversampling factor, and the number of stages establish the
overall length of the filter. N filter coefficients are stored
' in coefficient RAMs of each filter tap stage. The filter
coefficients are decimated by the number of taps (e.g. four)
when loading coefficient RAMS. The outputs of respective
coefficient, data multipliers are summed and written into a
dual port RAM, in preparation for application to the polyphase
o channelizer's FFT processor.
The FFT processor of the polyphase channelizer has
effectively the same configuration and operates in
substantially the same manner as the FFT processor of the
overlap and add channelizer described above. Once FFT-
processed data for each channel (frequency bin) has been
written into an output RAM, an FFT control logic unit signals
an attendant TDM bus interface circuit to assert the data onto
a TDM bus, so that it may be applied to attendant digital
signal processors on the bus, which are operative to demodulate
and extract voice or data from the channel data. The polyphase
channelizer may also be configured to write one or more
channels of data into a test memory, which allows a CPU on the
VMEbus to collect and analyze channel data without interfacing
to custom TDM bus.
The signal processing architecture of the polyphase
combiner, which is complementary to the wideband channelizer
having the polyphase filter structure described above, also
allows real-time processing of multiple digital voice or data
signals, and performs frequency translation and signal
combining to an IF ( intermediate frequency) output sample rate,
again providing fully programmable control of the system
parameters via a VmEbus interface and channelized data
collection over a custom, time division multiplexed (TDM) data
bus.
3s The front end (FFT processor) of the polyphase combiner is
the same as that of the overlap and add architecture described
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CA 022~0~4 1998-10-29
above, but employs a different filter structure, in which
adders are not internally cascaded with respective delay
memories as in the overlap and add combiner filter. Instead
the polyphase combiner filter structure corresponds to that
employed in the polyphase channelizer. The output of the
polyphase filter is coupled to a half band filter, which
provides complex to real data conversion, which doubles the
output sample rate. The output of the half band filter is
sent to an output data link for application to D-A converter
of the transmit side of the transceiver site.
In accordance with the invention, there is provided an
overlap and add filter architecture, comprising: a plurality
of cascaded filter tap stages which each comprises a plurality
of delay memories switchably coupled in series with one
another to selectively enable the delay memories of successive
filter tap stages to be controllably coupled in series, each
filter tap stage including (i) a coefficient memory which
stores a plurality of N weighting coefficients, (ii) a
multiplier which is operative to multiply respective weighting
coefficients stored in said coefficient memory by data samples
to be filtered, and (iii) an adder to which the output of
said multiplier and one of said plurality of delay memories is
coupled, said adder having an output coupled to a second of
said plurality of delay memories of a successive filter tap
stage.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 diagrammatically illustrates the receiver section
of a conventional cellular communication basestation channel
unit;
Fig. 2 is a multi-channel spectral distribution plot of
400-30KHz sub-portions of a 12MHz wide voice/data
communication band;
Fig. 3 diagrammatically illustrates a wideband
multichannel transceiver apparatus in accordance with the
present invention;
Figs. 4, 4A, 4B and 4C diagrammatically illustrate the
77088-lD
CA 022~0~4 1998-10-29
-16a-
configuration of an overlap and add channelizer that may be
employed in the transceiver apparatus of Fig. 3 in accordance
with a first embodiment of the present invention;
Fig. 5 is a functional diagram associated with the signal
processing mechanism executed by the overlap and add
channelizer of Figs. 4 through 4C;
Figs. 6, 6A, 6B and 6C diagrammatically illustrate the
signal processing architecture of a multichannel overlap and
add combiner, which is functionally complementary to the
wideband channelizer having the overlap and add filter
structure of Figs. 4 through 4C;
Figs. 7, 7A, 7B and 7C diagrammatically illustrate the
configuration of a channelizer employing a polyphase filter in
accordance with a second embodiment of the invention;
77088-lD
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--1 7--
Figs. 8, 8A, 8B and 8C diagrammatically illustrate the
configuration of a combiner employing a polyphase filter in
accordance with the second embodiment of the invention; and
Fig. 9 is a functional diagram associated with the signal
processing mechanism executed by the overlap and add combiner
of Figs. 6 through 6C.
DETAILED DESCRIPTION
Before describing in detail the particular improved
wideband multi-channel transceiver apparatus in accordance with
the present invention, it should be observed that the present
invention resides primarily in a novel structural combination
of commercially available communication and signal processing
circuits and components, and not in the particular detailed
configurations thereof. Accordingly, the structure, control
and arrangement of these conventional circuits and components
have been illustrated in the drawings by readily understandable
block diagrams which show only those specific details that are
pertinent to the present invention, so as not to obscure the
disclosure with structural details which will be readily
apparent to those skilled in the art having the benefit of the
description herein. Thus, the block diagram illustrations of
the Figures do not necessarily represent the mechanical
structural arrangement of the exemplary system, but are
primarily intended to illustrate the major structural
components of the system in a convenient functional grouping,
whereby the present invention may be more readily understood.
Referring now to Fig. 3, the transceiver apparatus of the
present invention is diagrammatically illustrated as comprising
a receiver section 100 and a transmitter section 200. Receiver
section 100 is coupled to an antenna 38 to a wideband receiver
101 capable of receiving any of the channels offered by a
communications service provider. As a non-limitative example,
wideband receiver 101 may comprise a WJ-9104 receiver,
manufactured by Watkins-Johnson Company, 700 Quince Orchard
Road, Gaithersburg Maryland 20878-1794.
AME~DS~E~
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CA 022~0~4 1998-10-29
~PEA/~I~ 08 NOV 1995
--1 8 _
The spectrum of interest may be that described previously
- e.g. a 10 - 12 MHz band comprised of four hundred (400)
channels, each of which are 30 KHz wide. It should be observed
however, that the present invention is not limited to use with
thi~ or any other set of communication system parameters. The
values given here are merely for purposes of providing an
illustrative example. Also, while the term 'wideband' is not
limited to any particular spectral range, it is to be
understood to imply a spectral coverage of at least the
entirety of the useful range of the communication range over
which the system may operate (e.g. 10 - 12 MHz). Narrowband,
on the other hand, implies only a portion of the spectrum, for
example, the width of an individual channel (e.g. 30KHz).
The output of wideband receiver 101 is a down-converted,
multi-channel (baseband) signal containing the contents of all
of the (30KHz) voice/data channels currently operative in the
communication system or network of interest. This multichannel
baseband signal is coupled to a high speed A-D converter 103,
~uch as a Model AD9032 A-D converter manufactured by Analog
Devices, One Technology Way, Norwood, Masschusetts 02062-9106.
Advantageously, the dynamic range and sampling rate
capabilities of current commercially available A-D converters,
such as that referenced above, are sufficiently high (e.g. the
sampling rate may be on the order of 25 megasamples/sec.) to
enable downstream digital signal processing (DSP) components,
including a digital Discrete Fourier transform (DFT)
channelizer 111, to be described below with reference to Figs.
4 through 8, to process signals within any of the (400 - 30
RHz) channels of the system and output such signals onto
respective channel links to the carrier interface (e.g. Tl
carrier digital interface) of the telephony network.
Fast Fourier Transform (FFT) channelizer 111 is operative
to process the output of A-D converter 103, which is coupled
thereto by way of a digital in-phase/quadrature (I/Q)
translator 107. I/Q translator 107 outputs respective I and Q
channel (i.e. complex) digitally formatted signals over I and
h~ .~ED SHEEi
r - -
CA 022~0~4 1998-10-29
-- 19 --
Q llnks 107-I and 107-Q, respectlvely. FFT channellzer
extracts, from the composlte digltlzed multlchannel (I/Q)
signal, respectlve narrowband channel slgnals representatlve
of the contents of respectlve ones of the (30 Khz)
communlcatlon channels recelved by wldeband recelver 101. The
respectlve channel slgnals are coupled vla N output llnks
(e.g. N = 400 ln the present example) to respectlve dlgltal
recelver processlng unlts 113-1...113-N, each of whlch ls
operatlve to demodulate and perform any assoclated error
correctlon processlng embedded ln the modulated slgnal, ~ust
as ln the conventlonal trancelver unlt of Flg. 1. For thls
purpose, each of dlgltal 10 recelver processlng unlts 113 may
comprlse a Texas Instruments~ TMS320C50 dlgltal slgnal
processor. Texas Instruments~ ls a trademark of Texas
Instruments, Inc. of Dallas, Texas. The demodulated slgnals
derlved by dlgltal recelver processlng unlts 113 are coupled
over respectlve channel llnks 115-1...115-N to a telephony
carrler lllterFace (e.g. Tl carrler dlgltal lnterface) of an
attendant telephony network (not shown).
Transmltter sectlon 200 lncludes a second plurallty
of dlgltal slgnal processlng unlts, speclflcally transmltter
slgnal processlng unlts 121-1...121-N, that are coupled to
recelve respectlve ones of a plurallty of channel dlgltal
volce~data communlcatlon slgnals to be transmltted over
respectlvely dlfferent narrowband (30 Khz) frequency channels
of the multlchannel network. Llke dlgltal recelver processlng
unlts 113 ln recelver sectlon 100, a respectlve dlgltal
70571-26
CA 022~0~4 1998-10-29
- l9a -
transmltter processlng unlt 121 may comprlse a model TMS320C50
dlgltal slgnal processor manufactured by Texas Instruments.
Transmltter signal processlng units 121 are operatlve to
modulate and perform pretransmlssion error correctlon
processlng on respectlve ones of the plurallty of lncomlng
communlcatlon slgnals and to supply processed ones of the
narrowband communlcatlon channel slgnals at respectlve output
ports 121-1...123-N.
From output ports 121-1...123-N of the transmltter
slgnal processlng unlts 121, the modulated narrowband channel
slgnals
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CA 022~0~4 1998-10-29~_
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IPEA/VS ~8 NOV ~995
-20-
are coupled over channel links 125-1 ...125-N to respective
input ports of an inverse FFT-based multichannel combiner unit
131, to be described below, which outputs a combined signal
representative of the contents of a wideband signal which is a
s composite of the respective narrowband communication channel
signals processed by digital transmitter signal processing
units 121. The output of multichannel combiner unit 131 is
coupled to an I/Q translator unit 132. I/Q translator receives
respective in-phase and quadrature signal components from
combiner 131 on links 131I and 131Q and provides a combined
output signal to a digital-to-analog (D-A) converter 133.
Digital-to-analog (D-A) converter 133, like high speed A-D
converter 103 in receiver section 100, preferably comprises a
currently commercially available unit, such as a model AD9712A
D-A converter manufactured by Analog Devices. The output of D-
A converter 133 is coupled to a wideband (multichannel)
transmitter unit 141, which is operative to transmit a wideband
(multichannel) communication channel signal containing the
composite signal output by inverse fast Fourier transform-based
combiner unit 131. The output of transmitter unit 141 is
coupled to an antenna 39 for transmission.
One of the features of the present invention that reduces
the amount of hardware required to provide broad coverage for
an increased (full spectrum) capacity cellular transceiver site
iS the application of convolutional - decimation spectral
analysis techniques to each of a wideband multichannel signal
extraction architecture (channelizer 111) and a wideband
multichannel signal combining architecture (combiner 131).
Because all of the channels of the operational communication
band available to the service provider can be processed using
digital processing components which operate at very high data
rates that accommodate the substantial bandwidth of present day
wireless communication systems, it is no longer necessary to
either construct a separate narrowband signal processing unit
for each channel, nor is it necessary to limit the number of
channels per site to less than the full capacity of the
network.
kMEN~)ED SHEET
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IPEA/~S ~S~NOV ~9y~
--2 1--
More particularly, the present invention makes it possible
to significantly reduce the size and hardware complexity of a
wireless communication network transceiver site by the u~e of
either overlap and add or polyphase channelizer and combiner
5 architectures, the fundamental signal processing
functionalities of which are mathematically detailed in Chapter
7 of the text ~Multirate Digital Signal Processing,~ by
R.E.Crochiere et al., and published by Prentice-Hall, Inc.
Since the algorithms for each of these two types of filter
transform functions are rigorously set forth in the Crochiere
text, they will not be repeated here. For a more detailed
description of overlap and add and polyphase signal processing,
per se, involved, attention may be directed to the Crochiere
text, per se. The description to follow will detail practical
15 embodiments of both overlap and add, and polyphase,
implementations of each the channelizer and combiner employed
in the inventive transceiver apparatus, for real-time wide band
wireless IF signal processing, which performs frequency
translation and channelization of a plurality of individual
20 narrow baseband signals.
OVERLAP AND ADD CHANNELIZER (Figs. 4, iA, 4B and 4C)
The channelizer implementation of Figs. 4, 4A, 4B and 4C
provides full programmable control of the system parameters by
5 way of a standard VMEbus interface, and channelized data
distribution over a custom, time division multiplexed (TDM)
data bus. For purposes of providing a non-limiting
illustrative example, both a 400 channel, 30 kHz system (which
may be employed in a North American Digital Cellular (NADC), as
30 defined by the Electronics Industries Association and
Telecommunications Industry Association standard TIA/EIA IS-54)
cellular system and a fifty channel, 200 kHz system (which may
be employed with the Pan-European Groupe Speciale Mobile (GSM)
cellular standard) will be described, in order to facilitate an
35 appreciation of the relationship between system parameters
(channel bandwidth, number of channels, sampling and processing
kMEN~D StlEET
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--22--
rates, etc.) and the control parameters of the channelizer
itself. For the 400 channel, 30 kHz channel system, a sample
rate of 50 kHz is assumed. For the 200 kHz system, a 300 kHz
sample rate is assumed. Channelized data is output by the
s channelizer as analytic baseband signals, and the channel
sample rates will depend upon the channelizer's filter design,
as will be described.
As pointed out above, the raw data upon which the
channelizer is to operate is derived from wideband receiver 101
o (Fig. 3). The sampling rate of the receiver's associated A-D
converter (103) is controlled by a sample rate clock signal
supplied over link 401 from a buffer/driver interface 403 under
the control of a control unit 405. Control unit 405 preferably
i8 comprised of a set of combinational logic and flip-flops
that are driven by associated clock sources 407, so as to
implement a state machine sequence control function to~be
described. The input sampling clock rate is determined by the
number of channels being received and the bandwidth Qf the
received channels.
Clock signals for the filter system, FFT processor and
output TDM bus, to be described, are derived from a high rate
(e.g. 200 MHz) reference oscillator 412 and associated down
counters 414 and 416.
Since the channelizer 111 is FFT-based, the total number
of channels must be a power of two. Due to characteristics of
the anti-aliasing filter contained in the wideband receiver,
channels that are near the edges of the band are typically not
useful. In order to process 400 30 kHz channels, the size of
the FFT channelizer must be a 512 point processor. To process
50 200kHz channels, a 64 point FFT processor is required.
The total input bandwidth that is to be sampled is N times
the channel bandwidth, where N is the size of the FFT
processor. The channelizer algorithm requires an input
sampling rate equal to 2*N*channel bandwidth, which is the
sample rate equal to the minimum rate required by the Nyquist
sampling theorem.
kM~ D SHEE~
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-23-
Thus, for a 30 kHz channelizer, the minimum clock rate is
25.62 MHz, while the filter minimum clock rate for the 200 kHz
~ channelizer is 19.05 MHz. In the present example, in order to
accommodate each of these sampling rates, clock unit 407 may
' contain respectively dedicated oscillators 407-1 and 407-2, as
shown. Which oscillator is employed may be determined during
initialization by a system controller (e.g., a CPU (not shown)
attached to a system VmEbus 410).
For 30 kHz channels, a 512 point FFT channelizer covers a
o bandwidth of 15.36 MHz, while 400 30 kHz channels cover 12 MHz.
The receiver must center the 400 30 kHz channels in the center
of the 15.36 MHz band, thereby providing 56 channels or 1.68
MHz of guard bands on both ends of the band to allow for
aliasing. Similarly, for 200 kHz channels, a 64 point FFT
channelizer covers a bandwidth of 12.8 MHz. Centering 50
channels provides 7 channels or 1.4 MHz guard band spacing on
both ends of the band to allow for aliasing.
The digitized data samples output by the receiver~s high
speed A-D converter are sequentially clocked over link 411
through buffer/driver interface 403 and loaded into a rate
buffer FIFO (first-in, first-out) memory 413, via control
signals on bidirectional link 415 from controller 405. As the
data is fed to rate buffer FIFO its two most significant bits
are monitored by logic circuitry 416 which serves as an
s amplitude monitor unit for the purpose of providing gain
control for the input signals and ensuring full utilization of
the dynamic range of the A-D converter. The output of unit 416
is fed back to the wideband receiver to control an attenuator
(not shown) that is upstream of the A-D converter.
When the FIFO rate buffer 413 contains a block, of M
samples, it signals the control unit 405 to begin processing
the block of data. These M samples are then clocked out of the
FIFO 413 over link 417 to a half band filter 419 in bursts at a
rate higher than the input sample clock rate in order to
3s accommodate the size of the FFT processor, which requires N
samples. As will be explained in detail below, N>M implies
AMENO~D SHEET
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t~TNS 9~ 1 5
IPEA/US O~NOV ~995
-24-
that the overlap and add filter must operate at a clock rate
faster than one-half the input sample rate.
Half-band filter 419 performs real-to-complex conversion
of the input data and also decimates the data by a factor of
s two, thereby dividing the clock rate in half. These complex
data value~ are clocked over link 421 to a shift register 422
employed within an overlap and add filter 420. Filter 420
comprises two real low pass filters with a cutoff frequency of
one-half of the channel bandwidth. The overall length of
o filter 420 is given by:
filter length = N~number of filter taps.
Shift register 422 is preferably implemented by cascading
sets of delay memory units 431 with interleaved 'feedback'
multiplexers 433, as shown. A respective tap stage 430 of
filter 420 is formed of memory elements 431A and 431B, a
feedback multiplexer 433, a coefficient memory 435 and a
multiplier 437. Each coefficient memory 435 stores a
respective set of filter coefficients, the number of which
corresponds to the size of the FFT processor. During
20 initialization, the coefficients are downloaded to the
coefficient memory by a system controller via the VMEbus 410.
In the illustrated embodiment, there are four tap stages
430-1...430-4. The outputs of multipliers 437 of the
respective tap stages are summed together via ~ummation stages
432, 434, 436. Thus, as functionally illustrated in Fig. 5,
shift register 422 may be considered to be formed of a set of J
cascaded K-stage shift registers (J is equal to four in a
preferred embodiment), or a single shift register which is J*K
stages in length, to which the digital data sample outputs are
supplied. The overall length (J~K) of shift register 422 is
given by the desired (time domainj window length of a
convolutional filter, so that the longer (greater the number of
stages of) the register, the sharper the characteristic of the
filter. For the 30 kHz channelizer of the present example, a
512-point FFT with a 50 kHz channel sample rate must be
produced every 20 microseconds, while for a 200 kHz channelizer
kMEND~D StlEET
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-25-
with a 300 kHz sample rate, a 64-point FFT must be generated
every 3.333 microseconds. For the 200 kHz channelizer, which
employs a 64 point FFT processor, filter 420 has an overall
length of 256 stages.
As shown in Figs. 4 and 4A and Fig. 5, the basic
architecture of an overlap and add filter 420 is similar to
that of a finite impulse response (FIR) filter. However, the
filter of the invention differs from a conventional FIR filter
by the use of feedback multiplexers 433 and long delay line
o elements (memories 431) between filter taps. The lengths of
memories 431 are configured by the system controller during
initialization and a determined in accordance with the filter~s
decimation rate M, referenced above.
The decimation rate is defined as:
M round (input sample rate/2*channel sample rate).
For the 30 kHz channelizer example, the decimation rate is
therefore
M = 3.072*10 /(2f5.0*10 ) = 307.
For the 200 kHz channelizer example, the decimation rate is
M = 2.56*10 /(2*3*10 )= 43.
Within memories 431, the length of memory 431B is the
decimation rate M; the length of memory 43lA, which represents
the filter 'overlap' i8 equal to N-M, where N is the size of
the FFT processor. Therefore, for the example of the 30 kHz
channelizer, the length of a respective memory 43lA or
'overlap' is 512-307=205 samples, while, in the case of 200 kHz
channels, the overlap length of memory 43lA is 64-43=21
samples.
As pointed out above, input data is processed in 'blocks'
of M samples of data, which are clocked out of FIFO 413 in
bursts at a rate higher that the input sample clock rate, in
order to accommodate the size of the FFT processor, which
requires N samples. Namely, N>M implies that the overlap and
add filter must operate at a clock rate faster than one-half
the input sample rate. The minimum clock rate of the filter
may be defined as:
filter-sampling rate = input sample rate*N/(2*M).
CA 022snss4 1998-1~-29 ~E;9 94 / 1 1 8 1 5
Thus, for the 30 kHz channelizer, the minimum sampling
rate i8 25.62 MHz, while the minLmum sampling rate for the 200
kHz channelizer is 19.05 MHz.
In order to process each block of M input samples, N clock
s ~ signals are re~uired to supply the FFT processor with a
sufficient number of data samples for FFT processing. During
the first M of the N clock signals, M samples are clocked
through rate buffer 413 and half band filter 419 and into shift
register 422. During this time frame, a state machine-
implemented filter control unit 440 applies a select controlsignal over link 442 to the select input port 433-5 of
multiplexer 433 to select its upper port 433-1 and a clock
signal via link 444 to the delay memories 431, so that data is
shifted from left to right through each of the delay memories
15 431. For the remaining N-M ones of the N data samples, gate
control unit 440 causes each multiplexer 433 to select its
lower port 433-2, so that data is not clocked out of rate
buffer memory 413 and there is no shifting of data through the
delay memories 431B. Namely, data is not shifted from left to
20 right through the ~hift register, as only the memories 431A are
clocked. This clocking of the memories 43lA is the mechanism
used to effect filter overlap diagrammatically illustrated in
the functional flow of Fig. 5.
More particularly, during the N clock times, the outputs
5 of the delay memories 43lA are multiplied by the filter
coefficients stored in coefficient memories 435 of the four tap
stages 430-1...430-4. The first N coefficients are stored in
the coefficient memory 435 of tap stage 430-1; the second N
coefficients are stored in the eoefficient memory 435 of tap
30 stage 430-2; the third N coefficients are stored in the
coefficient memory 435 of tap stage 430-3; and the fourth N
coefficients are stored in the coefficient memory 435 of tap
stage 430-4. It should be observed that the number of tap
stages is not limited to four or any other number. More stages
35 may be employed to increase the length of the filter, so as to
reduce allasing within the channel, increase channel
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selectivity and allow a reduction in channel sample rate.
Namely, the rate at which data is shifted into the
convolutional filter operator corresponds to the decimation
rate M of the filter and thereby controls the sharpness of
5 filter roll-off. Setting M for optimized system performance
depends upon FFT processing capability and the available
sampling rate of the digitizing 5 components (A-D converter
103).
OVERLAP AND ADD FFT PROCESSOR
As the four sets of coefficient-weighted data samples
generated by filter stages 430-1... 430-4 are summed together
via summation stages 432, 434 and 436 they produce an N sample
aliased convolved data sequence which is stored in a dual port
RAM 451 comprised of RAM sections 45lA and 45lB, so that it may
be applied to an FFT processor 460. The addressing of dual
port RAM 451 and the operation of the FFT processor are
controlled by a state machine, preferably implemented as a
logic gate array 468.
The processing rate of the FFT processor is defined as:
FFT rate = l/(channel sample rate).
For the 30 kHz channelizer example under consideration,
generation of a 512-point FFT with a 50 kHz channel sample rate
requires 20 microseconds, while the rate at which a 64-point
FFT must be generated for a 200 kHz channelizer with a 300 kHz
sample rate is 3.333 microseconds. Since currently available
typical FFT devices do not operate at these speeds, then in
order to maintain throughput, FFT processor 460 contains a
plurality of FFT engines (e.g., three - 461, 462, 463 in the
illustrated example) that have ~een programmed with the proper
FFT size associated with the signal processing parameters of
interest. Implementing the FFT processor with three engines
decreases the FFT revisit time for the 512 point FFT processor
to 60 microseconds, and 10 microseconds for the 64 point FFT
processor and allows the FFT processors to maintain real time
data throughput with currently available integrated circuits.
AMENDED SHEET
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--2 8--
In accordance with a preferred embodiment, the FFT engines
employ a radix-4 (block floating point) algorithm having FFT
- sizes that are a power of 4. For a 512 point FFT processor,
production of all 512 frequency bins is carried out by using
~ two 256-point FFTs that are preceded by a decimation-
infrequency radix-2 butterfly. To generate the even bins of an
N-point FFT using an N/2 point FFT, it is necessary that:
X[2k] = FFT(xln]-+ x[n+N/2]),
where x[n] i8 the N-point input sequence of the FFT, k is the
o FFT bin number and X[k] is an FFT bin sample. For the case of
a 512-point FFT, the samples are read out of dual port RAM 451
and supplied to arithmetic logic unit (ALU) 453, which, under
the control of FFT control logic unit 468 sums the data samples
x[n] and xln+N/2]. During this time a downstream numerically
controlled oscillator, modulator 455, the input of which is
driven by the output of the ALU 453, is disabled by FFT control
logic gate array 468. The sum value is supplied to FFT
processor 460 which generates the FFT of the even frequency
bins, i.e. X[2k] = FFT(x[n] + x[n+N/2]), set forth above.
. For generating the odd bins of an N-point FF~, the
following equation is employed:
X[2k+1] = FFT((x[n] - x[n+N/2] )*WN
where
W =e-j~2~n/N
In order to generate a 512-point FFT for the odd bins, as
odd bin data samples are read out of dual port RAM 451,
arithmetic logic unit (ALU) 453 is controlled by FFT control
logic unit 468 to take the difference between the data samples
x[n] and x[n+N/2]. This difference is multiplied by WN by the
numerically controlled oscillator, modulator 455 and clocked
into FFT processor 460, which generates the FFT of the odd
frequency bins, i.e. X~2k+1]=FFT((x[n] - x[n+N/2])*WNn).
In the case of a 200 kHz channelizer, which employs a 64-point,
power-of-four FFT engine, neither ALU 453 nor oscillator 455 is
required, so they are disabled by FFT control logic unit 468.
As described earlier, the FFT engines 460 employ a block
floating point algorithm, outputting a four bit scaling factor
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--2 9--
with the complex FFT data. This scaling factor is fed to a
scaling logic circuit 466 to control a barrel shift circuit
~ 471, to which the output of the FFT engine is coupled. Barrel
shift circuit 471 adjusts the data as it is read out from the
5 ~ FFT engines in order to ensure that consecutive FFTs are
aligned to the same scale. The output of barrel shift circuit
471 i8 coupled to a dual port RAM 473.
As described in the above-referenced Crochiere text, the
output of the Fourier transform operator (here the FFT engines
of processor 460) is multiplied by a complex exponential WN
where M is the decimation rate, k is the FFT bin number, and m
is the F~T (block) number (i.e. for the first FFT generated,
m=O; for the next FFT, m=l; for the third FFT, m=2; etc.). The
decimation rate M is programmed into the FFT's control logic
15 unit during initialization. To execute an equivalent
operation, the channelizer of Figs. 4 through 4C uses the
following identity:
x[((n-r) )N] = FFT(WN *X[k]),
where x[n] is the FFT input sequence, as set forth above, and
20 X[ ( (n-r) )N] iS the circular shift of x[n] by r modulo N. In
the illustrated embodiment of Figs. 4 through 4C, r is equal to
NM.
Rather than perform the complex multiplication downstream
of the FFT, control logic unit 468 controllably addresses dual
5 port RAM 473, so as to access processed data values in an order
that effects a circular shifting of the FFT's input data
sequence.
Once FFT-processed data for each channel (frequency bin)
has been written into dual port RAM 473, FFT control logic unit
30 468 signals an attendant time division multiplexed (TDM) bus
interface circuit 475 to assert the data onto TDM bus 480 so
that it may be applied to attendant processors 113 (Fig. 3) on
the TDM bus. Such processors correspond to processors 113,
referenced previously, and may comprise digital signal
35 processors which are operative to demodulate and extract voice
or data from the channel data.
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Data on the TDM bus 480 is divided into a plurality of
time slots (e.g. 400 time slots per TDM frame). The TDM bus
may be driven by a 20 Mhz clock, which allows a single time
slot to be used to output a single channel of data up to a 50
kHz sample rate. If a higher channel sample rate is required,
multiple time slots may be assigned to a single channel. For
example, a 300 kHZ sample rate would be allocated six time
slots. Time slots may be allocated dynamically by the system
controller, which configures the channelizer with all active
o time slots. If data is available in dual port RAM 473 and the
time slot is active, the channelizer outputs the data via
buffer unit 481 and a data available signal on TDM bus 480.
All digital signal processors collecting data from that time
slot will read data from the TDM bus. The bus connected
~5 processors are synchronized to the TDM bus by a conventional
framing signal, so that the processors 113 (Fig. 3) will know
the correct time slot from which to read data.
OVERLAP AND ADD COMBINER (Figs. 6, 6A, 6B and 6C)
Figs. 6 through 6C diagrammatically illustrate the signal
processing architecture of a multichannel combiner 131, which
is complementary to the wideband channelizer having the overlap
and add filter structure of Figs. 4 through 4C, described
above. As in the case of the channelizer, the signal
processing functionality of the multichannel combiner
essentially corresponds and is functionally equivalent to the
signal processing flow diagram shown in Fig. 9, which
corresponds to Figure 7.20 of the above referenced Crochiere
text.
Like the overlap and add channelizer shown in Figs. 4
through 4C, described above, combiner unit 131 employs a
practical implementation that allows real-time processing of
multiple digital voice or data signals, and performs frequency
translation and signal combining to an IF (intermediate
frequency) output sample rate. The implementation of Figs. 6
through 6C provides fully programmable control of the system
AMENOFDSHE~
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_- parameters via a standard VMEbus interface 601, 603 and
channelized data collection over a custom, time division
multiplexed (TDM) data bus 605.
As in the above description of the channelizer of Figs. 4
through 4C, the overlap and add combiner of Figs. 6 through 6C
will be described for non-limitative examples of a 400
channel/30 kHz system which can be used in a NADC (TDMA)
cellular system, and a 50 channel/200 kHz system which can be
used with the European GSM cellular standard. For 30 kHz
channels, a sample rate of 50 kHz is assumed. For 200 kHz, a
300 kHz sample rate is assumed. Channelized data is received
by the combiner as analytic baseband signals. Channel sample
rates depend upon the combiner's filter design.
The combiner architecture of Figs. 6 through 6C employs a
custom TDM bus 610 for collecting data for a large number of
channels at relatively high data rates, since the aggregate
data rate from all channels typically exceeds the bus bandwidth
of the VMEbus 605 and other standard bus protocols. TDM bus
610 has its clock set at 20 MHz, so as allow 400 time slots per
frame. Each time slot can transfer a single channel of data up
to the above-referenced 50 kHz sample rate. For higher rates,
multiple slots per frame can be assigned to a single source.
As noted above with reference to the TDM bus of the channelizer
of Figs. 4 through 4C, a 300 kHz sample rate would require six
s slots per frame, since each slot handles a sample rate of 50
kHz (and six times 50 kHz is 300 kHz).
The sources of the channelized data that are asserted onto
the TDM bus are DSP processors 113 (Fig. 3) that format (e.g.
to a cellular standard) and modulate incoming voice or data
signals from an attendant telephone network, thereby providing
a baseband analytic signal. Each data source is assigned one
or more time slots during which it will transfer a single
complex sample when requested by the combiner. No two sources
can be allocated the same time slot. Time slots are assigned
by a system controller (a separate CPU on VMEbus 605) during
system initialization. The system controller also programs t
combiner to specify all time slots that contain valid data.
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A sample from each DSP processor is requested via control
signals applied to TDM bus 610 from a TDM bus controller 611
(logic array-implemented state machine) and associated
buffer/driver~ 613. This sample is written into a dual port
s RAM buffer 615 via bus buffer unit-617. TDM bus control logic
unit 611 synchronizes addressing of RAM buffer 615 to framing
signals of the TDM bus, thereby insuring that each channel is
written to the proper address in dual port RAM 615. When the
combiner has collected data from all operative channels, the
TDM bus controller 611 couples control signals via link 612 to
an FFT control logic unit 620, causing FFT control logic unit
620 to initiate FFT processing. Like logic gate array 468 in
the channelizer, FFT control logic unit 620 is a state machine
preferably implemented as a logic gate array. Complementary to
the forward FFT processor functionality of the channelizer of
Figs. 4 through 4C, the combiner of Figs. 6 through 6C causes
an inverse FFT to be performed. In terms of a practical
implementation, however, generation of an inverse FFT is
effected using a forward FFT, as will be described.
FFT PROCESSOR
The FFT processor, shown at 630, is configured to have a
size equal to the next 'power of two' greater than the number
of channels to be combined. As noted above, four hundred (400)
30 kHz channels require a 512-point FFT, while fifty 200 kHz
'- channels require a 64-point FFT. FFT size is programmed into
the FFT engines during initialization. The channel rate also
specifies the FFT processing rate in accordance with the
equation:
FFT rate = l/(channel sample rate)
As explained previously, a 50 kHz sample rate for 30 kHz
channels requires that a 512-point FFT be generated every 20
microseconds, while a 300 kHz sample rate requires a 64-point
FFT every 3.333 microseconds. Since currently available
typical FFT devices do not operate at these speeds, to maintain
throughput, FFT processor 630 contains a plurality of FFT
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engines (e.g. three - 631, 632, 633 in the illustrated
example) that have been programmed with the proper FFT size
associated with the signal processing parameters of interest.
Implementing FFT processor 630 with plural engines reduces the
s FFT revisit time for the 512 point FFT processor to 60
microseconds, and 10 microseconds for the 64 point FFT
processor.
A 512-point inverse FFT requires 512 samples; however,
there are only 400 time slots. These 400 time slots are
centered in the 512 bin window of FFT processor 630. Control
logic unit 620 causes zeros to be written sequentially into an
FFT engine for the first 56 bins. For the next 400 bins, data
may be read from dual port RAM 615 for the active channels. If
the channel is not an active channel, control logic unit 620
lS will write a zero into that bin. The identities of those
channels that are active are programmed into control logic unit
620 during system initialization. For the last 56 bins, zeros
are written into those bins. (For a 64-point FFT, zeros are
written into the first and last seven FFT bins allowing fifty
20 200 kHz channels.)
To provide built-in-test capability, test data may be
written into one or more bins via VMEbus 605. For this
purpose, a first-in-first-out (FIFO) memory 635, dedicated for
test capability, is coupled to bu~ 605 via transceiver unit
5 601, so as to allow a CPU on the VMEbus to write a test signal
~ to the combiner. In addition, the system controller can
program FFT control logic unit 620 to read data from FIFO
memory 635 rather than dual port RAM 615 for specific bins.
Test data may be written into the first and last seven FFT
30 bins, thus leaving fifty 200 kHz channels available for
incoming active data channels.
In order to generate an inverse FFT using a forward FFT,
the following identity is used:
x[n] = K*FFT(X[((-k))~]),
35 where x[n] is the inverse FFT of X[k], n is the sample number,
k is the FFT bin number, K is the FFT size, and X[((-k))~]
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represents a sequence having the reverse of the order of the
sequence X[k], by modulo K. By generating a mirror of the
input data to the FFT about bin number 0, the forward FFT
becomes an inverse FFT scaled by the FFT size. Control logic
unit 620 addresses the input dual port RAM 615 in a reverse
order when writing data into the FFT engines.
As in the channelizer implementation of Figs. 4 through
4C, to generate a 512-point FFT in the combiner architecture of
Figs. 6 through 6C, the FFT engines employ a radix-4 (block
floating point) algorithm having FFT sizes that are a power of
four. To generate the even bins of an N-point FFT using an NX2
point FFT, it is necessary that:
X[k] = G[k] + H[~]*WN
where X[k] i9 the N-point FFT of an input sequence x~n], k is
the FFT bin number, N is the FFT size (512), G[k] is the N/2-
point FFT of the even samples of x[n], H[k] is the N/2-point
FFT of the odd samples of x(n], and:
- j ~2 ~ n~N
WN=e
As in the channelizer of Figs. 4 through 4C, a 512-point FFT
for the combiner is generated from two 256-point FFTs.
The N/2-point FFTs are generated from even and odd samples
of the 512-point input sequence. In the architecture of Figs.
6 through 6C, a first (upper, as viewed in the Fig. 6A) FFT
data dual port RAM 641 stores G[k]. A second FFT data dual
s port RAM 642 stores Htk]~WN . Multiplication of H[k] and WN
i~ performed by a numerically controlled oscillator, modulator
(NCOM) 651 for k = 0 to 255. To process the first 256 bins of
a 512-point FFT, the output of RAM 641 is summed with the
output of RAM 642 by means of an arithmetic logic unit (ALU)
655. Since
WNk = _WN , for k = 256 to 511,
the output N of RAM 642 is subtracted from the output of RAM
641 for the remaining 256 bins of the 512-point FFT.
In order to accommodate the propagation delay through NCOM 651
3s and ensure that the proper pair of samples are processed by ALU
655, a set of delay registers 657 are coupled in the output
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path from dual port RAM 641 to the ALU. (For the 200 k~z
channels, a 64-point FFT is used. Since 64 is a power of 4,
-
NCOM 651, dual port RA~ 642, and ALU 655 are not necessary and
are disabled by control signals from control unit 620.)
As described in the above-referenced Crochiere text, the
combiner algorithm requires the input sequence of the inverse
FFT be multiplied by the complex exponential, WR , where k
equals the input frequency bin number, K is equal to the
inverse FFT size, m is the inverse FFT number (i.e. for the
first inverse FFT generated, m=O; for the next FFT, m=l; etc.
), R is the combiner's interpolation rate, and WK=e j
Using a mathematical identity, this multiplication
operation can be effected by a circular rotation of the output
samples of the inverse FFT, i.e.:
x[((n-r))k] = inverse FFT (WK ~X[k]),
where r is equal to -mR. By rotating the inverse FFT output
samples by -mR, the phase shift of the complex exponential is
generated. ThiS rotation is performed by the FFT output
addressing logic in FFT control logic gate array 620. The
amount of rotation is preprogrammed during initialization of
the combiner.
As noted earlier, the FFT engines generate FFTs using a
block-floating point algorithm. The block-floating point FFT
provides a scaling factor which depends upon the
characteristics of the input data. Since the two 256-point
FFT~ used to generate a 512-point FFT may not have the same
scaling factor or consecutive FFTs may not have the same
scaling factor, barrel shifting circuits 658, 659 are coupled
in the signal flow input paths to ALU 655. As described
previously in connection with the operation of the channelizer
of Figs.4 through 4C, the barrel shifters adjust the FFT data
to the same scale to properly align the data for subsequent
processing.
OVERLAP AND ADD FILTERING
As in the channelizer of Figs. 4 through 4C, the overlap
and add filter of the combiner of Figs. 6 through 6C, shown at
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660, comprises four filter tap stages 660-1, 660-2, 660-3 and
660-4. The FFT size and the number of stages set the overall
; length of the filter, which is defined by:
Filter Length = N*number of stages,
' where N is the FFT size.
Filter 660 is designed as a real low pass filter with a
cutoff frequency equal to one half the channel bandwidth. It
should be observed that the filter is not limited to a four
stage filter; more stages may be employed, if desired, which
o will increase channel selectivity, reduce aliasing within the
channel and can decrease the channel sample rate. A respective
stage 660-i of filter 660 is formed of one or both of memory
elements 631A and 631B, a feedback multiplexer 633, a
coefficient memory 635 and a multiplier 637. Each coefficient
memory stores a respective set of N filter (weighting)
coefficients, the number of which corresponds to the size of
the FFT processor. The coefficients are downloaded to the
coefficient memory 635 via the VMEbus 605 during
initialization. Address inputs for the coefficient memories
are ~upplied via links 629 from a (gate array logic-
implemented) filter control state machine 670, while data
inputs are coupled via data links.
The first N coefficients are loaded into the coefficient
memory 635 of the first or left-most stage 660-1; the second N
coefficients are stored in the coefficient memory 635 of tap
stage 660-2; the third N coefficients are stored in the
coefficient memory 635 of tap stage 660-3; and the fourth N
coefficients are stored in the coefficient memory 635 of tap
stage 660-4. The output of the FFT processor from ALU 655 is
distributed via link 656 to multipliers 637 of all filter
stages and multiplied by the coefficients of each stage
simultaneously. The outputs of multipliers 637 are coupled to
adders 639, to be added to data being accumulated and shifted
through the delay memories.
As in the filter of the channelizer of Figs. 4 through 4C,
the delay memory of each stage, with the exception of the first
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stage 660-1, is divided into two memory sections 631A and 631B.
The first filter tap stage 630-1 does not require a delay
~ memory section 631B, since zeros, supplied via link 632 to
multiplexer 633, are shifted into the first filter stage. The
' length of each delay memory is determined by the filter
interpolation rate, which is defined in accordance with the
channel and output sample rates. The output sample rate of the
combiner is given bys
Output sample rate = N*channel bandwidth.
o For 30 kHz channels, the output sample rate is 3.0*104
*512 = 15.36 MHz. For 200 kHz channels, the output sample rate
is 2.0*10 *64=12.8 MHz. The filter interpolation rate, R, is
the nearest integer of the following quotient:
R = round (output sample rate/channel sample rate)
As noted above, for the example of using 30 kHz channels
with a 50 kHz channel sample rate, the interpolation rate is
R=307; for 200 kHz channels with a 300 kHz channel sample rate,
the interpolation rate is R=43. The length of each of delay
memory sections 631A is R, while the length of delay memory
section 63lB, also known as the filter overlap, is given by:
overlap = (N-R).
Thus, for 30 kHz channels, the filter overlap is 205; for
200 kHz channels the filter overlap is 21. The interpolation
rate R also specifies the required signal processing rate of
the overlap and add filter. The minimum clock rate the filter
must process data to maintain throughput is given by:
filter processing rate = output rate*N/R.
For a 30 kHz channel system the minimum rate is 25.62 MHz.
For a 200 kHz channel system, the rate is 19.05 MHz.
For every N samples output by the inverse FFT processor,
overlap and add filter 660 outputs R samples. For the first R
samples of each inverse FFT, filter control state machine 670,
selects, via select control link 671, a first or upper input
port 633-1 through the multiplexer~ 633. During this time, all
data is shifted or clocked via clock control link 669 from left
to right, as viewed in Figs. 6 through 6C, and summation values
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produced by adder 639 in the last stage 630-4 of the filter are
input to a half band filter 672.
For the remaining N-R samples, a second or lower port 633-
2 of each multiplexer 633 is selected, and the outputs of
adders 639 are fed back via links 638 to the delay memory
sections 631A. During this time memory sections 631B are not
shifted and the data at the last stage 660-4 is not clocked
into the half band filter. Again, as in the channelizer
filter, the feedback of the last N-R samples provides the
filter overlap.
HALF BAND FILTER AND RATE BUFFER
The output of filter 660 is coupled to a half band filter
672, since RF transmitter exciters typically require a real
signal rather than a complex one. Half band filter 672 is
configured as an integrated circuit that provides complex to
real data conversion, which doubles the output sample rate.
Although the entirety of the combiner of Figs. 6 through 6C
could be implemented as a completely real system, this would
require all sample rates, processing rates and FFT sizes to be
doubled, increasing complexity and cost. A rate buffer FIFO
memory 674 is coupled to the output of half band filter 672 to
allow a continuous flow of data from the combiner. Data stored
in FIFO memory 674 i8 coupled via output driver unit 675 to an
output data link 690 for application to D-A converter 133 (Fig.
3) of the transmit side of the transceiver site.
A~ noted earlier, overlap and add filter 660 provides a
burst of R samples every N clock cycles, and the output of FIFO
674 provides a continuous flow of data at the real output
sample rate. Additionally, a half full flag from the FIFO is
supplied over a control signal line 673 to a control logic
circuit, to indicate to the TDM bus interface unit 611, via
control links distributed among the respective state machines,
when to request data. When the quantity of data stored in FIFO
674 falls to less than half the capacity of the FIFO, the flag
becomes inactive, which signals the TDM bus interface to
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request channel data from its active channels and being
processing to maintain the continuous flow of output data.
; As in the channelizer architecture of Figs. 4 through 4C,
respective oscillators are provided for each output sample rate
' required. For the present example of a combiner capable of
processing either 30 kHz or 200 kHz channels, respective 30 . 72
MHz and 25.6 MHZ (2*output sample rate) clocks 676 and 677 are
provided. During initialization of the combiner by the system
controller, the proper oscillator is selected by an associated
control logic unit 678.
An additional set of logic circuits is included to
generate additional clock signals employed by the combiner. As
in the channelizer architecture of Figs. 4 through 4C, the
clock output of a high rate (approximately 200 MHz) oscillator
681 is divided down by counters 682 and 68 3 to generate the
necessary filter processing clock, TDM bus clock, and FFT
engine system clock.
CHANNELIZER USING POLYPHASE FILTERS (Figs. 7, 7A, 7B and 7C)
A second embodiment of the wideband channelizer of the
present invention is configured as a polyphase filter
structure, which is functionally expressible by the signal
processing flow diagram shown in Figure 7.15 of the above
referenced Crochiere text. Again, since algorithms for each of
the filter transform functions (respectively employed by
polyphase implementations of the filter structure contained in
channelizer 111 and combiner 131 of Fig. 3) are rigorously set
forth in the Crochiere text, they will not be repeated here;
for a more detailed description of the signal processing
relationships involved attention may be directed to the
Crochiere text.
As in the overlap and add channelizer embodiment of Fig. 4
through 4C, the architecture of an FFT-based polyphase filter
bank analysis (channelizer) system of Fig. 7 accepts real-time
wide band IF (intermediate frequency) signals and performs
frequency translation and channelization to a number of
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individual narrow baseband analytic signals. The polyphase
filter channelizer provides full programmable control of the
- system parameters via a standard VmEbus interface and
channelized data distribution over a custom, time division
~ multiplexed (TDM) data bus. (Keeping with the foregoing
examples, the description of the polyphase filter embodiment to
follow will address specifics of a 400 channel/30 kHz system,
and a 50 channel/200 kHZ system.)
A characteristic of the polyphase channelizer architecture
is that the input sample rate is an integral multiple of the
channel sample rate. This implies that the channel sample rate
must be a multiple of the channel bandwidth. In the present
description the channels are oversampled by a factor of two;
therefore, a 60 kHz sample rate for 30 kHz channels is assumed,
and a 400 kHZ sample rate for 200 kHz channels is assumed.
Channelized data is distributed by the channelizer as analytic
baseband signals.
HALF BAND FILTER, AND AM~LITUDE MONITORING
The channelizer's input interfaces via a buffer/driver
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logic circuit 706, under the control of a filter control state
; machine 707, is coupled to oscillators 702, 704. During
initialization, a system controller (a CPU on VMEbus 710)
configures the channelizer to select the proper oscillator.
s The oscillator clock is also divided down to generate a clock
on output clock link 712 to drive the channelizer's shift
register delay memory, to be described. The input samples on
data link 703 are clocked into a half band filter 711, which is
configured as a finite impulse response (FIR) filter that
o performs a real-to-complex conversion of the input data. Half
band filter 711 also decimates by two, reducing the clock rate
of the data by half. The complex samples are then fed into a
shift register 713 of a polyphase filter 715. In particular,
the output of half band filter 711 is clocked into a delay
memory 721 of a shift register 713 of a first filter stage 715-
1 of filter 715. The length of each delay memory 721 is equal
to the FFT size in the channelizer. The output of each delay
memory 721 is applied to coefficient multipliers 723.
Coefficient multipliers 723 and other hardware components
operate at a rate that is I times the clock rate of shift
register 713, where I is the oversampling factor. As mentioned
above, the oversampling factor equals two. This implies that
each sample at the output of the delay memories is multiplied
to two (I=2) filter coefficients, prior to being clocked into
the next delay memory.
In the filter architecture of Fig. 7 through 7C, polyphase
filter 715 consists of four filter stages 715-1, 715-2, 715-3
and 715-4. The FFT size, oversampling factor, and the number
of stages establish the overall length of the filter. The
length of the filter is:
Filter Length = I*N*S
where S is the number of filter taps. As noted earlier, more
filter ~tages increase channel selectivity and reduce aliasing
within the channel. Filter coefficients are downloaded to
coefficient RAMs 725 by way of filter control gate array 707,
as supplied via bus transceivers 731 from VMEbus interface 710.
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The RAM 725 of each 3stage 715-i store~s N coefficients. The
; filter coefficients are decimated by the number of taps (here -
four) when loading coefficient RAMs 725 in accordance with the
following decLmation equation:
Ca[n] = ctS~n+a], for n = 0 to N*I-l
where c(n) i~ the sequence of filter coefficients, a i3s the tap
number (a = O to S-l), and ca[n] are the coefficients to be
loaded into the a tap. For example, coefficient RAM 725 of the
first filter tap stage 715-1 is loaded with the following
coefficients3:
C0[n] = {c[o], C[4], c[8], C[12] ... c[I*N-S]~
The outputs of coefficient multipliers 723 are then summed by
way-of adders 732, 734 and 736 and written into a dual port RAM
740, which comprises memory sections 741 and 742.
FFT PROCESSOR
The FFT processor of the polyphase combiner has
effectively the same configuration and operates in
sub~tantially the same manner as the FFT processor of the
overlap and add channelizer of Figs. 4 through 4C, described
above. After N samples have been written into dual port RAM
740, filter control unit 707 couples control signals over link
719 to (gate array logic-implemented state machine) FFT control
unit 735 to begin FFT processing. Within FFT processor 750, a
set of three FFT engines 751, 752, 753 have previously been
programmed with the proper FFT size during initialization.
AE3 in the overlap and add channelizer of Figs. 4 through
4C, the FFT engines employed in the polyphase combiner use a
radix-4 algorithm and generate FFT sizes that are a power of
four. In the architecture of Figs. 7 through 7C, all 512 bins
of the FFT are produced by using two 256-point FFTS preceded by
a decimation-infrequency radix-2 FFT butterfly.
In the course of generating the even bins of the FFT, data
samples are read from dual port RAM 740 and fed into arithmetic
logic unit (ALU) 743. ALU 743 sums the values of x[n] and
x[n+N/2] and couples the sum directly to the FFT processor, as
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a numerically controlled oscillator, modulator (NCOM) 745 is
disabled during even bin processing. For odd bin processing
FFT control logic unit 735 configures ALU 743, via control link
744, to take the difference of x[n] and x[n+N/2]. This
s difference value is multiplied by WN by NCOM 745 and clocked
into an FFT engine, which produces odd bins of the 512-point
FFT. (For a 200 kHz channelizer, which requires a 64-point FFT
as a power of four, ALU 743 and NCOM 745 are not necessary and
are disabled by FFT control unit 735.)
As previously described, FFT engines 751, 752, 753 use a
block floating-point algorithm and output a four bit scaling
factor with complex FFT data. The scaling factor is used to
control a donwstream barrel shifter 761 under the control of a
scaling logic circuit 762. Again, the barrel 10 shifter is
lS employed to adjust the data as it is read from the FFT engines,
in order to insure that data from consecutive FFTs are aligned
to the same scale. From the barrel shifter 761, the data is
written into a dual port RAM memory 765.
As noted above, the channelizer algorithm requires that
the output of the FFT processor be multiplied by a complex
exponential, WN , where H = decimation rate, k = FFT bin
number, and m = FFT (block) number (i.e. m=O, for the first
FFT generated; m=l for the next FFT generated; etc.). Namely,
using the following identity:
s x[((n-r) )N] = FFT(WN *X~k])
~~ where x[n] is the FFT input sequence, and x[((n-r) )N] iS the
circular shift of x[n} by r modulo N, the channelizer performs
an equivalent operation. Here, mM = r. Rather than multiply
the complex exponential downstream of the FFT processor, the
channelizer's FFT control logic unit 735 controllably addresses
dual port RAM 765, 80 as to access processed data values in an
order that effects a circular shifting of the FFT's input data
sequence.
Once FFT-processed data for each channel (frequency bin)
3s has been written into dual port RAM 765, FFT control logic unit
735 signals an attendant time division multiplexed (TDM) bus
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interface circuit 767 to assert the data onto TDM bus 770, so
that it may be applied to attendant digital signal processors
on the bus, which are operative to demodulate and extract voice
or data from the channel data.
s The polypha~e channelizer can also be configured to write
one or more channels of data into a test FIFO memory 771. FIFO
memory 771 allows a CPU on VMEbus 710 to collect and analyze
channel data without interfacing to custom TDM bus 710.
Once data from each channel has been written into dual
port RAM 765 from the FFT engines, the FFT control Iogic unit
735 signals TDM bus interface logic circuit 767 to distribute
the data to digital signal processors on the bus, which are
operative to demodulate and extract voice or data from the
channel data. A bus buffer unit 775 is coupled between dual
port RAM 765 and TDM bus 770. Data on the TDM bus may be
divided into 400 time slots per frame supplied by a counter
circuit 781, as driven by a high speed reference oscillator
782, thereby allowing a single time slot to be used to output a
single channel of data up to a 60 kHz sample rate. If a higher
channel sample rate is needed, multiple time slots may be
assigned to a single channel. For example, as described above,
a 400 kHz sample rate would be allocated seven time slots.
Time slots may be allocated dynamically by the system
controller. The channelizer is configured by the controller
with all active time slots. If data is available in the dual
port RAM and the time slot is active, the channelizer outputs
the data and a data available signal on TDM bus 770. All
processors collecting data from that time slot will read data
from the TDM bus. The processors are synchronized to the TDM
bus 770 by a framing signal, so that the processors will know
the proper time slot(s) from which to read data.
POLYPHASE COMBINER ( Figs. 8, 8A, 8B and 8C)
Figs. 8 through 8C diagrammatically illustrate the signal
processing architecture of a polyphase implementation of
combiner 131, which is complementary to the wideband
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channelizer having the polyphase filter structure of Fig. 7,
described above. A characteristic of the polyphase combiner is
that the output sample rate is an integer multiple of the
channel sample rate. This implies that the channel sample rate
must be a multiple of the channel bandwidth. In the present
description the channel is oversampled by a factor of two;
therefore, a 60 kHz sample rate for 30 kHz channels is assumed,
and a 400 kHz sample rate for 200 kHz channels is assumed.
Channelized data is received by the polyphase combiner as
o analytic baseband signals.
Like the overlap and add channelizer shown in Figs. 8
through 8C, described above, the polyphase combiner employs a
practical implementation that allows real-time processing of
multiple digital voice or data signals, and performs frequency
translation and signal combining to an IF (intermediate
frequency) output sample rate. The implementation of Figs. 8
through 8C provides fully programmable control of the system
parameters via a standard VmEbus interface 801, 803 and
channelized data collection over a custom, time division
multiplexed (TDM) data bus 805.
Again, as in the previous description of the channelizer,
the polyphase will be described for non-limitative examples of
a 400 channel/30 kHz system which can be used in a NADC (TDMA)
cellular system, and a 50 channel/200 kHz system which can be
used with the European GSM cellular standard. For 30 kHz
channels, a sample rate of 60 kHz is assumed. For 200 kHz, a
400 kHz sample rate is assumed. Channelized data is received
by the combiner as analytic baseband signals. Channel sample
rate~ depend upon the combiner~s filter design.
The combiner architecture of Figs. 8 through 8C employs a
custom TDM bus 810 for collecting data for a large number of
channels at relatively high data rates, since the aggregate
data rate from all channels typically exceeds the bus bandwidth
of the VMEbus 805 and other standard bus protocols.
3s To implement a transceiver system employing the polyphase
combiner (and channelizer) it is convenient to set the TDM bus
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810 clock equal to 24 MHz, 80 as to allow 400 time slots per
frame, with each time slot transferring a single channel of
data up to the above-referenced 60 kHZ sample rate. This clock
rate differs from the TDM bus clock rate of the overlap and add
combiner/channelizer embodiment of the transceiver system which
has been given as an example of a 50 kHz channel sample rate.
The clock rate iB not limited to this value but has been
selected in order to provide a simplified example of an
implementation of a transceiver system.
o For higher rates, multiple slots per frame can be assigned
to a single source. As noted above with reference to the TDM
bus of the channelizer of Figs. 8 through 8C, a 400 kHz sample
rate would require seven slots per frame.
The sources of the channelized data that are asserted onto
the-TDM bus are-DSP processors that format (e.g. to a cellular
standard) and modulate incoming voice or data signals from an
attendant telephone network, thereby providing a baseband
analytic signal. Each data source is assigned one or more time
slots during which it will transfer a single complex sample
when re~uested by the combiner. No two sources can be allocated
the same time slot. Time slots are assigned by a system
controller (a separate CPU on VMEbus 805) during system
initialization. The system controller also programs the
combiner to specify all time slots that contain valid data. A
sample from each DSP processor is requested via control signals
applied to TDM bus 810 from a TDM bus controller 811 (logic
array-implemented state machine) and associated buffer/drivers
813. This sample is written into a dual port RAM buffer 815 via
bus buffer unit 817. TDM bus control logic unit 811
synchronizes addressing of RAM buffer 815 to framing signals of
the TDM bus, thereby insuring that each channel is written to
the proper address in dual port RAM 815.
When the combiner has collected data from all operative
channels, the TDM bus controller 811 couples control signals
via link 812 to an FFT control logic unit 820, causing FFT
control logic unit 820 to initiate FFT processing. FFT control
.
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logic unit 820 is a state machine preferably implemented as a
logic gate array. Complementary to the forward FFT processor
~ functionality of the channelizer of Figs 7 through 7C, the
polyphase combiner of Figs. 8 through 8C causes an inverse FFT
5 ' to be performed. As in the overlap and add combiner of Figs. 6
through 6C in terms of a practical implementation, however,
generation of an inverse FFT is effected using a forward FFT,
as will be described.
FFT PROCESSOR
The FFT processor, shown at 830, i8 configured to have a
B ize equal to the next 'power of two' greater than the number
of channels to be combined. As noted above, four hundred 30 kHz
channels specify a 512-point FFT, while fifty 200 ~Hz channels
15 require a 64-point FFT. FFT size is programmed into the FFT
engines during initialization. The channel rate also specifies
the FFT processing rate in accordance with the equation:
FFT rate = l/(channel sample rate)
As explained previously, a 60 kHz sample rate for 30 kHz
20 channels requires that a 512-point FFT be generated every
16.667 microseconds, while a 400 kHz sample rate requires a 64-
point FFT every 2.5 microseconds. Since currently available
typical FFT devices do not operate at these speeds, to maintain
throughput, FFT processor 830 contains a plurality of FFT
engines (e.g. three - 831, 832, 833 in the illustrated example)
that have been programmed with the proper FFT size associated
with the signal processing parameters of interest. Implementing
FFT processor 830 with three engines reduces the FFT revisit
time for the 512 point FFT processor to 50 microseconds, and
7.5 microseconds for the 64 point FFT processor.
As described previously, a 512-point inverse FFT requires
512 ~amples; however, there are only 400 time slots. These 400
time slots are centered in the 512 bin window of FFT processor
830. Control logic unit 820 causes zeros to be written
Bequentially into an FFT engine for the first 56 bins. For the
next 400 bins, data may be read from dual port RAM 815 for the
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active channels. If the channel is not an active channel, ~FT
control logic unit 820 will write a zero into that bin. The
identities of those channels that are active are programmed
into control logic unit 820 during system initialization. For
the last 56 bins, zeros are written into those bins. (For a 64-
point FFT, zeros are written into the first and last seven FFT
bins allowing fifty 200 kHz channels.)
To provide built-in test capability, test data may be
written into one or more bins via VMEbus 805. For this
purpose, a fir~t-in-first-out (FIFO) memory 835, dedicated for
test capability, is coupled to bus 805 via transceiver unit
801, 80 as to allow a CPU on the VMEbus to write a test signal
to the combiner. In addition, the system controller can
program FFT control logic unit 820 to read data from FIFO
memory 835 rather than dual port RAM 815 for specific bins.
Test data may be written into the first and last seven FFT
bins, thus leaving fifty 200 kHz channels available for
incoming active data channels.
To generate an inverse FFT using a forward FFT, FFT
control logic unit 820 addresses the input dual port RAM 815 in
a reverse order when writing data into the FFT engines.
As in the overlap and add combiner implementation of
Figs. 6 through 6C, to generate a 512-point FFT in the combiner
architecture of Figs. 8 through 8C, the FFT engines employ a
radix-4 (block floating point) algorithm having FFT sizes that
are a power of four. As in the combiner of Figs. 6 through 6C,
a 512 point FFT for the combiner is generated from two 256-
point FFTs. The N/2-point FFTs are generated from even and odd
samples of the 512-point input sequence.
In the architecture of Figs. 8 through 8C, a first (upper,
as viewed in the Figure) FFT data dual port RAM 841 stores
holds Gtk]. A second (lower as viewed in the Figure) FFT data
dual sport RAM 842 stores H[k]. Multiplication of H[k] and WN
i~ performed by a numerically controlled oscillator/modulator
(NCOM) 851 for k = 0 to 255. TO process the first 256 bins of
a 512-point FFT, the output of RAM 841 is summed with the
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output of RAM 842 by means of an arithmetic logic unit (ALU)
855. Since
: WNk = _W~k N~2, for k = 256 to 511,
the output of RAM 842 is subtracted via the NCOM from the
~ output of RAM 841 for the remaining 256 bins of the 512-point
FFT.
In order to accommodate the propagation delay through NCOM
851 and ensure that the proper pair of samples are processed by
ALU 855, a set of delay registers 857 are 20 coupled in the
output path from dual port RAM 841 to the ALU. (For the 200
kHz channels, a 64-point FFT is used. Since 64 is a power of
4, NCOM 851, dual port RAM 842, and ALU 855 are not necessary
and are disabled by control signals from control unit 820.)
As pointed out above, with reference to the Crochiere
text, the combiner algorithm requires the input sequence of the
inverse FFT be multiplied by the complex exponential, WKkmR,
where k i~ equal to the input frequency bin number, K is the
inverse FFT size, m is the inverse FFT number, R is the
combiner~s interpolation rate, and
- j ~2 ~n/k
Using a mathematical identity, this multiplication
operation can be effected by a circ~lar rotation of the output
samples of the inverse FFT, i. e.:
xt((n-r))~] = inverse FFT (WR-rk *X[k]),
where-r is equal to -mR. By rotating the inverse FFT output
samples by -mR, the phase shift of the complex exponential is
generated. This rotation is performed by the FFT output
addressing logic in FFT control logic gate array 820. The
amount of rotation is preprogrammed during initialization of
the combiner.
Again, the FFT engines generate FFTs using a block-
floating point algorithm, which provide a scaling factor that
depends upon the characteristics of the input data. Since the
two 256-point FFTS used to generate a 512-point FFT may not
have the same scaling factor or consecutive FFTS may not have
the same scaling factor, barrel shifting circuits 858, 859 are
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coupled in the signal flow input paths to ALU 855. As
described previously in connection with the operation of the
combiner of Fig. 6, the barrel shifters are operative to adjust
the FFT data to the same scale to properly align the data for
subsequent processing.
POLYPHASE FILTER
The output of the FFT, as supplied by ALU 855, is clocked
into a delay memory 861 of a shift register 863 of a first
filter stage 865-1 of a filter 865. The length of each delay
memory 861 is equal to the FFT size. The output of each delay
memory 861 is applied to a respective coefficient multiplier
869. Coefficient multipliers 869 and other hardware components
operate at a rate that is I times the clock rate of shift
register 863, where I is the 10 oversampling factor. As
mentioned above, the oversampling factor equals two. This
implies that each sample at the output of the delay memories is
multiplied by two (I=2) filter coefficients, prior to being
clocked into the next delay memory.
In the filter architecture of Figs. 8 through 8C,
polyphase filter 865 consists of four filter stages 865-1, 865-
2, 865-3 and 865-4. The FFT size, oversampling factor, and the
number of stages establish the overall length of the filter.
The length of the filter i8:
Filter Length = N~S
where S is the number of filter taps. As noted earlier, more
filter stages increase channel selectivity and reduce aliasing
within the channel. Filter coefficients are downloaded to
coefficient RAMs 867 by way of filter control gate array 871,
as supplied via bus transceivers 801 from VMEbus interface 803.
The RAM 867 of each stage 865-i stores N coefficients. The
filter coefficients are decimated by the number of taps (here~
four) when loading coefficient RAMs 867 in accordance with the
following decimation equation:
ca~n] = ctS~n+a], for n = 0 to N-l
where c(n) is the sequence of filter coefficients, a is the tap
number (a = ~ to S-l), and c~[n] are the coefficients to be
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loaded into the a tap. For example, coefficient RAM 867 of the
; first filter tap stage 865-1 i~ loaded with the following
coefficients:
cO[n] = {c(O], c14], c[8), ctl2]...c[N-S]}
The outputs of coefficient multipliers 869 are then summed
by way of adders 872, 874, 876 and applied to a half-band
filter 877.
HALF BAND FILTER AND RATE BUFFER
o As in the combiner of Figs. 6 through 6C, half band filter
877 is employed, since RF transmitter exciters typically
require a real signal rather than a complex one. Half band
filter 877 is configured as an integrated circuit that provides
complex to real data conversion, which doubles the output
sample rate. Although the entirety of the combiner of Figs. 8
through 8C could be implemented as a completely real system,
this would require all sample rates, processing rates and FFT
sizes to be doubled, increasing complexity and cost.
The output of half band filter 877 is coupled via output
driver unit 874 to an output data link 866 for application to
D-A converter 133 (Fig. 3) of the tr~nsmit side of the
transceiver site. As in the combiner architecture of Figs. 6
through 6C, respectivé oscillators are provided for each output
sample rate required. For the present example of a combiner
capable of processing either 30 kHz or 200 kHz channels,
respective 30.72 MHz and 25.6 MHz (2*output sample rate) clocks
876 and 877 are provided. During initialization of the
combiner by the system controller, the proper oscillator is
selected by an associated dontrol logic unit 878.
An additional set of logic circuits is included to
generate additional clock signals employed by the combiner. As
in the combiner architecture of Figs. 6 through 6C, the clock
output of a high rate oscillator (approximately 200 MHz) is
divided down by counters 882 and 883 to generate the necessary
filter processing clock, TDM bus clock, and FFT engine system
clock.
- kMEND~DS~E~
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As will be appreciated from the foregoing description, the
limited channel capacity and substantial hardware requirements -
associated with signal processing architectures currently
employed by multichannel wireless communication (e.g. cellular)
5 service provider~ are successfully obviated by the multichannel
transceiver apparatus of the present invention, which reduces
the amount of hardware required to provide broad coverage for
an increased (full spectrum) capacity cellular transceiver site
by applying convolutional - decimation spectral analysis
o techniques to each of a wideband multichannel signal extraction
architecture and a wideband multichannel signal combining
architecture. Since all of the channels of the operational
communication band available to the service provider can be
processed using digital processing components which operate at
15 very high data rates that accommodate the substantial bandwidth
of present day wireless communication systems, it is no longer
necessary to either construct a separate narrowband signal
processing unit for each channel, nor is it necessary to limit
the number of channels per site to less than the full capacity
20 of the network. The compact design of the invention allows it
to be readily physically accommodated at a variety of
installation sites, such as above the drop ceiling in an office
building or on an electric utility pole, while having the
capability of providing multichannel communication service that
3 spans the entire channel capacity offered by the service
provider, rather than only a subset of the available channels.
While we have shown and described several embodiments in
accordance with the present invention, it is to be understood
that the same is not limited thereto but is susceptible to
30 numerous changes and modifications as known to a person skilled
in the art, and we therefore do not wish to be limited to the
details shown and described herein but intend to cover all such
changes and modifications as are obvious to one of ordinary
skill in the art.
kMEND~D SHEET
