Note: Descriptions are shown in the official language in which they were submitted.
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Ev1ULATING NARROW BAND PHASE-LOCKED LOOP
BEHAVIOR ON A WIDE BAiND PHASE-LOCKED LOOP
BACKGROUND OF THE INVENTION
1. Field of the Invention.
The present invention relates generally to phase-locked loop circuits, and
more particularly to a phase-locked loop circuit which exhibits a tightly
controlled
capture range for locking an output signal to a data signal, while also
providing a wide
frequency capture range for initially pulling the output signal within a
wider,
predetermined frequency range.
2. Description of Related Art.
Digital data transmission has become increasingly important in the m.odern
communications era. The importance of modern digital data transmission drives
the
search for more efficient and effective phase-locked loops that are used in
data
communications systems.
EP 0 402 113 discloses a VCO frequency control circuit. A phase error
generator generates a digital phase error signal from an input signal. The
phase error
signal is converted to a digital frequency error signal by a digital
integrator. The error
signals are added and the result is supplied to a DAC in the phase-locked loop
for
providing an analog output indicative of PLL frequency error. Outputs from two
DACs are summed and the resultant current is used to adjust the VCO frequency.
WO 96 17435 discloses a steered frequency phase-locked loop. The loop
comprises phase and frequency detectors, receiving an output from a VCO. The
outputs from the detectors are individually gained and filtered, and fed to a
summer.
The frequency of the signal produced by a VCO deviates from a free-running
frequency depending on the input from the summer.
US 5,546,433 discloses a digital phase-locked loop having frequency offset
cancellation circuitry. A phase comparator generates phase error signal
samples from
a digital data signal. A phase/frequency detector 50 generates either UP or
DOWN
output pulses depending on whether an output from a frequency synthesizer
leads or
lags a clock signal from a VCO. A phase error clock signal is generated by a
logic
circuit, and fed to a counter which integrates the phase error in the signal.
The
secondary frequency offset value is converted to an analog signal and combined
with
signals from the phase comparator to generate an analog oscillator control
signal.
AMENDED SHEET
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U.S. 5,525,935 discloses a high-speed bit synchronizer with multi-stage
control structure. An output signal from a phase comparator is fed to a phase
difference output controller. The output from a frequency comparator is fed to
a
frequency synchronous signal detector. The phase difference output controller
receives either a synchronous or an asynchronous signal from the frequency
synchronous signal detector, whereupon the phase difference output controller
transfers, or does not transfer, respectively, its output to an integrator.
Fig. 1 illustrates a prior art phase-locked loop (PLL) 10 feedback circuit.
The
PLL 10 is a feedback circuit that is often used to reduce an error term toward
zero. In
the case of the PLL, the error term is the phase difference between an input
signal and
a reference signal. The basic component building blocks of a PLL are a phase
comparator 12 and a voltage-controlled oscillator (VCO) 14. The PLL
incorporates
the VCO 14 in the feedback loop. A VCO is an oscillator whose output frequency
is a
function of its input voltage. The phase comparator 12 compares the phase of
the
input signal on line 16 to the phase of the signal at the output of the VCO on
line 18.
If the phase difference between these two signals is non-zero, the output
frequency of
the VCO 14 is adjusted in a manner which forces this difference down to zero.
The
output signal on line 20 is fed back to the VCO 14 to provide a signal
proportional to
the phase difference between the signals on lines 16 and 18.
As is appreciated by those skilled in the art, such a PLL feedback system is
often used to extract a baseband signal from a frequency modulated carrier in
a
communications system. Phase-locked loops are also widely used in
communication
systems for coherent carrier tracking, and threshold extension, bit
synchronization and
symbol synchronization. The PLLs as used in the data communications system of
the
present invention are used to lock to a receive signal and to subsequently
provide the
receive clock for that signal. Typically, the PLL lock information generated
from a
data signal is poor, and is therefore not capable of pulling the PLL very far
in
AMENDED SNSET
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frequency. Often the frequency range of the PLL is wider than this narrow
"capture"
range. Under these circumstances, the oscillation frequency of the PLL must
somehow be brought close enough to the data signal frequency for the PLL to
lock to
the data signal. This can be done, as shown in Fig. 1, by first locking the
PLL 10 to
the frequency of a reference signal on line 22, which is close in frequency to
the data
signal on line 24. When the PLL 10 is locked to the reference signal on line
22, the
input of the PLL 10 is switched over to the data signal on line 24. Although
this
procedure works, it requires control circuitry 26 to switch from the reference
signal on
line 22 to the data signal on line 24, and then back again if phase lock is
lost.
There is a need, therefore, for a phase-locked loop which has a wide frequency
capture range for pulling the PLL within a predetermined frequency range, yet
has a
well-controlled and narrow frequency capture range for locking to the actual
data
signal, without the use of switching control circuitry such as control
circuitry 26.
SUMMARY OF THE INVENTION
To overcome the limitations in the prior art described above, and to overcome
other limitations that will become apparent upon reading and understanding the
present specification, the present invention discloses a phase-locked loop
that exhibits
a tightly controlled capture range for locking an output signal to a data
signal, while
also providing a wide frequency capture range for initially pulling the output
signal
within a wider, predetermined frequency range.
In one aspect there is provided a phase-locked loop (PLL), comprising:
frequency compare means (102) for detecting a frequency difference
between at least one reference signal (110, 112) and a PLL output signal
(108),
and for generating a frequency error signal in response thereto; wherein the
frequency error signal comprises a dominating frequency error signal and said
frequency compare means comprises means for generating a dominating
frequency error signal when the frequency difference is outside of a
predetermined frequency range, wherein the dominating frequency error signal
overdrives the phase error signal;
phase error detection means for detecting a phase difference between a
received input signal (114) and the PLL output signal, and for generating a
phase error signal in response thereto;
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signal summing means (122), coupled to the phase error detection
means and the frequency compare means, for combining the phase error signal
and the frequency error signal to form a combined error signal; and
a voltage-controlled oscillator (118) having an input terminal coupled to
receive the combined error signal and an output terminal to output a variable
frequency PLL output signal in response thereto.
In another embodiment of the present invention, a multiple-stage phase-
locked loop (PLL) has an inherently wide actual signal capture range and a
narrow effective signal capture range. The PLL includes a multiple-stage phase-
locked loop (PLL) having an inherently wide actual signal capture range and a
narrow effective signal capture range, the phase-locked loop comprising:
first detection means (102) for detecting first phase differences between
at least one reference signal (110, 112) and an output signal (108), and for
generating a first phase error signal when the first phase differences fall
outside
of a predetermined frequency range;
second detection means (104) for detecting second phase differences
between a received input signal(114) and the output signal, and for generating
a
second phase error signal in response thereto;
signal summing means (122), coupled to the first detection means and
the second detection means, for combining the first phase error signal and the
second phase error signal, and for overdriving the second phase error signal
with the first phase error signal when both the first and second phase error
signals are active, wherein said first detection means comprises means for
generating a dominating error signal by increasing an amplitude of the first
phase error signal, wherein said signal summing means comprises means for
combining the dominating error signal and the second phase error signal, and
for overdriving the second phase error signal with the dominating error
signal;
and
voltage-controlled oscillation means (118), coupled to the signal
summing means, for controlling the frequency of the output signal in response
to
the first and second phase error signals.
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In yet another embodiment of the invention, a method is provided for phase-
locking an output signal to a data signal. A frequency error signal is
generated where
a first frequency difference, measured by the frequency difference between a
reference
signal and the output signal, is outside of a predetermined frequency range. A
phase
error signal is generated for a second frequency difference measured by the
frequency
difference between the data signal and the output signal. Where the first
frequency
difference is outside of the predetermined frequency range, the frequency
error signal
overdrives the phase error signal. The frequency of the output signal is
controlled
with the phase error signal and the frequency error signal.
These and various other advantages and features of novelty which characterize
the invention or point out with particularity in the claims annexed hereto and
form a
part hereof. However, for a better understanding of the invention, its
advantages, and
the objects obtained by its use, reference should be made to the drawings
which form
a further part hereof, and to accompanying descriptive matter, in which there
is
illustrated and described specific examples of an apparatus in accordance with
the
invention.
BRIEF DESCIZTPTION OF THEDRAWINGS
Referring now to the drawings in which like reference numbers represent
corresponding parts throughout:
Fig. 1 illustrates a prior art phase-locked loop feedback circuit;
Fig. 2 is a general block diagram of one embodiment of the phase-locked loop
of the present invention;
Fig. 3 is a block diagram of a second order phase-locked loop of the present
invention;
Fig. 4 is a block diagram of one embodiment of the frequency comparator;
Fig. 5 is a general diagram of the transfer function of the frequency
comparator; and
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Fig. 6 is a diagram of the transfer function of the frequency comparator with
respect to the preferred reference signals.
DETAILED DESCRIPTION OF THE INVENTION
In the following description of the preferred embodiment, reference is made to
the accompanying drawings which form a part hereof, and in which is shown by
way
of illustration the specific embodiment in which the invention may be
practiced. It is
to be understood that other embodiments may be utilized and structural changes
may
be made without departing from the scope of the present invention.
The present invention provides a phase-locked loop circuit which exhibits a
tightly controlled capture range for locking to a data signal, while also
providing a
wide frequency capture range for pulling the PLL within a wider frequency
range.
Fig. 2 is a general block diagram of one embodiment of the invention. The
PLL 100 of Fig. 2 includes a frequency comparator 102 and a phase error
detector 104
at the inputs of the PLL 100. The frequency comparator 102 compares the
frequency
of one or more reference signals to the frequency of a signal to be
controlled. The
signal to be controlled in Fig. 2 is the output signal, labeled F(CK) on line
106. The
F(CK) signal is fed back to the frequency comparator 102 via line 108 to be
compared
to one or more reference signals. In the preferred embodiment, two reference
signals
are provided, labeled F(CENT) on line 110 and F(REF) on line 112. PLL 100
compares the frequency of the F(CK) signal on feedback line 108 to a
combination of
the reference signals on lines 110 and 112. The reference signal combination
will be
described in more detail in the ensuing description.
The purpose of the frequency comparator 102 is to provide a mechanism for
pulling the output of the PLL 100 within a first frequency range from which
the phase
error detector 104 can then tightly lock to the input signal on line 114. The
frequency
comparator 102 outputs a frequency error on line 116 that is proportional to
the
frequency difference between the combination of the reference signals on lines
110,
112, and the F(CK) signal on feedback line 108. Where the frequency of the
F(CK)
signal on feedback line 108 is greater than a combination of the reference
signals
F(CENT) and F(REF), a negative frequency error signal will be generated on
line 116
to ultimately cause the VCO 118 to decrease the frequency of the F(CK) signal.
Where the frequency of the F(CK) signal on feedback line 108 is less than a
combination of the reference signals F(CENT) and F(REF), a positive frequency
error
signal will be generated on line 116 to ultimately cause the VCO 118 to
increase the
frequency of the F(CK) signal.
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The frequency comparator 102 and the phase error detector 104 operate
concurrently, however the frequency comparator 102 overrides the phase error
detector 104 while the frequency error on line 116 is active. The frequency
error is
active when the frequency difference, between the F(CK) signal on feedback
line 108
5 and the combination of the reference signals F(CENT) and F(REF) on lines 110
and
112 respectively, is outside of a predetermined frequency range.
This predetermined frequency range is bounded by a cutoff frequency,
F(cutoff), above or below the combined reference signal frequency. When the
frequency difference is within the predetermined frequency range, the phase
error on
line 120 is recognized by the VCO 118, which then adjusts the output signal
F(CK) on
line 106 according to the frequency difference between the F(CK) signal on
feedback
line 108 and the input signal on line 114. In sum, the frequency comparator
102 first
pulls the PLL 100 output signal F(CK) on line 106 to a frequency range defined
by
the reference signals F(CENT) and F(REF) on lines 110 and 112 respectively.
Then,
when the F(CK) signal is within the predetermined frequency range, the phase
error
detector locks the PLL 100 output signal F(CK) to the input signal on line
114.
As previously described, the frequency comparator 102 overrides the phase
error detector 104 when the frequency comparator 102 is generating a frequency
error
signal on line 116. The amplitude of the frequency comparator 102 output on
line 116
is selected to be large enough to overdrive the phase error signal on line
120.
Therefore, when the frequency difference between the F(CK) signal and the
combination of the reference signals F(CENT) and F(REF) is outside of the
predetermined frequency range, the frequency comparator 102 provides an
amplified
error signal which is recognized at the input of the VCO 118.
When this frequency difference is within the predetermined frequency range,
the amplified frequency error signal on line 116 is reduced to a near zero
value, and
the phase error detector 104 then provides the error signal to the input of
the VCO
118. Using such an amplified frequency error signal, both the frequency error
signal
and the phase error signal, on lines 116 and 120 respectively, can be
concurrently
generated, while allowing only one of the signals to be significantly
recognized.
The frequency error signal the phase error signal on lines 116 and 120 are
added together at the summing device 122. This allows both the frequency error
signal and the phase error signal to be generated concurrently, while
providing a
single input signal to the VCO 118.
Referring now to Fig. 3, the PLL 200 includes a circuit 202 for changing the
order of the phase-locked loop. The PLL 200 is similar to PLL 100 of Fig. 2,
as it
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includes the frequency comparator 102, the phase error detector 104, the
summing
circuit 122 and the VCO 118. However, these components can be applied to any
order PLL. PLL 200 is a second order phase-locked loop, as the circuit 202
includes
an integrator 204 and a summing circuit 206. As will be appreciated by those
skilled
in the art, the inclusion of circuit 202 results in a transfer function having
two poles,
thereby providing a second-order PLL. Regardless of the order of the PLL, the
resulting signal is inputted into the VCO 118 to control the frequency of the
output
signal F(CK) on line 106. The output signal F(CK) is also fed back into both
the
frequency comparator 102 and the phase error detector 104. This feedback
provides
the control signal necessary for the frequency comparator 102 and the phased
error
detector 104 to lock in on the frequency of the input signal on line 114. Any
order
PLL can be constructed using the teachings as herein disclosed without
departing
from the scope and spirit of the invention.
Fig. 4 is a general block diagram of one embodiment of the frequency
comparator 102. The preferred frequency comparator 102 is an up/down counter
300
with input signals F(CENT), F(REF) and F(CK) on lines 110, 112 and 114. One
possible implementation is a 16-bit counter having four outputs on lines 302,
304, 306
and 308. On the positive edge of an F(CENT) pulse, the counter executes one
count
towards its center (i.e., it decrements the count if the count is greater than
eight, and
increments the count if the count is less than eight). On the positive edge of
an
F(REF) pulse the counter increments, and on the positive edge of an F(CK)
pulse the
counter decrements.
When the count is greater than 12, the frequency comparator 102 outputs a
positive error signal proportional to the amount by which the count is greater
than or
equal to twelve (hexadecimal C). When the count is less than 4, the frequency
comparator 102 outputs a negative error signal proportional to the amount by
which
the count is less than four.
Other circuitry in the frequency comparator 102 converts the up/down counter
300 value to a signal that can be recognized by the VCO 118. For instance, the
boundary logic 310 receives the count value on lines 302 through 308, and
determines
whether the count is less than four, between four and eleven, or greater than
or equal
to twelve. If the count is between four and eleven, the boundary logic 310
outputs a
binary null value to ultimately generate a near zero frequency error signal on
line 116.
If the count is less than four, or greater than eleven, the boundary logic
passes the
value to a digital-to-analog (D/A) converter 312 that generates a proportional
frequency error signal on line 116.
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It can be shown that the up/down counter 300 counts down and therefore
produces a negative frequency error signal when F(CK)-F(REF) > F(CENT), which
would indicate that the F(CK) signal is oscillating at a faster rate than the
F(REF) and
F(CENT) reference signal combination. The up/down counter 300 counts up and
therefore produces a positive frequency error signal when F(CK)-F(REF) <
F(CENT), which would indicate that the F(CK) signal is oscillating at a slower
rate
than the F(REF) and F(CENT) reference signal combination. The up/down counter
300 counts toward the center and therefore produces zero output when IF(CK)-
F(REF)j < F(CENT). This indicates that the zone where the frequency comparator
102 no longer overdrives the phase error signal on line 120 is within the
predetermined frequency range defined by F(REF)-F(CENT) to F(REF)+F(CENT).
Since F(REF) and F(CENT) are crystal controlled clocks in the preferred
embodiment, the capture range is tightly controlled and can be made very
narrow.
This result is independent of the exact counter details implemented.
Referring now to Table 1, the frequency comparator 102 output, i.e., the
frequency error signal on line 116, is shown for each count of a 16-bit
up/down
counter 300. As can be seen, a negative frequency error signal, labeled -ERR,
is
generated for binary values of 0 to 3. The -ERR signal is proportional to the
amount
by which the count is less than four. The +ERR signal is proportional to the
amount
by which the count is greater than or equal to twelve. Where the count is
between
four and eleven, the frequency error signal, shown as ERR, is approximately
equal to
zero.
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TABLE I
COUNTER OUTPUT FREQUENCY COMPARATOR
OUTPUT
0 0 0 0
0 0 0 1 -ERR a(4-COUNT)
0010
0 0 1 1
0 1 0 0
0101
0 1 1 0 ERR=0
0111
1000
1001
1 0 1 0
1011
1100
1 1 0 1 +ERR ac (COUNT-12)
1110
1111
Fig. 5 is a diagram of the transfer function of the frequency comparator 102
of
Fig. 4. Fig. 5 illustrates the frequency error signal on line 116 as plotted
against the
frequency mismatch of the reference signals and the VCO 118 output. As is
evident
from Fig. 5, where the reference signals and the VCO output are relatively
close in
frequency, no error signal is generated by the frequency comparator 102 within
the
predetermined frequency range 400. It is within this frequency range 400 that
the
frequency error on line 116 does not dominate the phase error signal on line
120, and
the phase error signal allows the input signal on line 114 to be locked as the
F(CK)
signal on line 106. The lower range of the frequency mismatch is shown in Fig.
5 as
the minus cutoff frequency, -F(CUTOFF), and the upper range of the frequency
mismatch is shown as the positive cutoff frequency, +F(CUTOFF). These cutoff
frequencies define the boundaries of the predetermined frequency range outside
of
which the frequency error signal controls. At mismatch frequencies below the
minus
cutoff frequency, it can be seen that a negative error signal is generated
which is
proportional to the magnitude of the frequency mismatch. Likewise, frequency
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mismatches above the positive cutoff frequency increase linearly as the
frequency
mismatch increases beyond its upper range.
For the frequency comparator 102 as shown in Fig. 4, the up/down counter
300 will decrement the count when the F(CK) signal is greater than the sum of
the
reference signals as shown in Equation 1 below.
F(CK) > F(REF) + F(CENT) [EQUATION 1]
When the F(CK) signal is greater than the sum of the reference signals, the
operating
point moves to the left on the transfer function of Fig. 5 until a negative
error signal
occurs, which is proportional to the magnitude of the frequency mismatch, as
seen by
line 402.
The up/down counter 300 will increment the count when the F(CK) signal is
less than the difference of the F(REF) and F(CENT) signals as shown in
Equation 2
below.
F(CK) < F(REF) - F(CENT) [EQUATION 2]
When the F(CK) signal is less than the difference of the F(REF) and F(CENT)
signals, the operating point moves to the right on the transfer function until
a positive
error signal occurs, which is proportional to the magnitude of the frequency
mismatch,
as seen by line 404.
When the magnitude of the difference between the F(CK) and F(REF) signals
is less than the frequency of F(CENT), as shown in Equation 3 below, the
operating
point stays within the predetermined frequency range 400.
F(cENT) > IF(cK) - F(REF)I [EQUATION 3]
It will be readily recognized by those skilled in the art that counters larger
or smaller
than a 16-bit counter may be used without departing from the invention, and
only the
precise location of the -F(CUTOFF) and the +F(CUTOFF) will be affected.
Referring now to Fig. 6, a diagram of the transfer function of the frequency
comparator 102 is shown having the frequency cutoff values as determined by
Equations I and 2. The -F(CUTOFF) frequency, shown at point 500, can be
represented by F(REF)-F(CENT), as shown in Equation 2. The +F(CUTOFF)
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frequency, shown at point 502, can be represented by F(REF)+F(CENT), as shown
in
Equation 1. Therefore, the capture range is set by controlling the frequencies
of the
F(REF) and F(CENT) signals. By using crystal controlled signals, this range
can be
tightly controlled.
5 The foregoing description of the preferred embodiment of the invention has
been presented for the purposes of illustration and description. It is not
intended to be
exhaustive or to limit the invention to the precise form disclosed. Many
modifications
and variations are possible in light of the above teaching. It is intended
that the scope
of the invention be limited not by this detailed description, but rather by
the claims
10 appended hereto.
