Note: Descriptions are shown in the official language in which they were submitted.
CA 02283892 1999-09-16
w WO 98/45944 PCT/CA98/00294
Title: Extended Fre~uencv Range Relaxat~n" c~SC.;llatnr with Im rn owed
~.a
GELD OF TfIE IN~~
The present invention relates to the fields of analog and
digital communication, data communication, clock recovery, phase locked
loops, voltage controlled oscillators {VCOs), multivibrators, relaxation
oscillators, and monolithic oscillators. Specifically the present invention is
a relaxation oscillator with an extended linear voltage/current to
frequency characteristic which is suitable for use in high speed clock
recovery systems and which has a wide frequency acquisition range.
BACKGROUND OF TI3E IN .N~rrn~r
A relaxation oscillator, such as a relaxation voltage/current
controlled oscillator, is an oscillator circuit which has its frequency of
oscillation determined by the time to charge and / or discharge a capacitor
{or other reactive element) to a threshold level.
In United States Patent 4,977,381, Main discloses a relaxation
oscillator in which a capacitor is placed in a differential configuration
between a first and a second current supply means. The direction in which
the capacitor is charged or discharged is controlled by a differential pair of
transistor switches which are turned on and off by a bistable circuit
element such as a latch. A control signal which gates the bistable element
is inverted when the voltage across the capacitor is at opposite polarities of
a particular threshold. The bistable element eliminates sudden voltage
jumps at switching times and thereby avoids saturation of the collector-
emitter conduction paths of the transistor switches when they are
suddenly turned on. A circuit responsive to the dynamic terminal voltages
of the capacitor controls either the first current supply means or the second
current supply means to maintain the DC (direct current) voltage of the
capacitor terminals at a constant, predetermined value. As a result, the
slew rate of the voltages at the terminals of the charging capacitor remains
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substantially constant for a given frequency of operation.
While the relaxation oscillator disclosed by Main desensitizes
the oscillator to the effects of the inherent stray capacitance and improves
the accuracy of the output frequency, it is susceptible to certain drawbacks.
Generally, in relaxation oscillator circuitry the charging current through
the capacitor must be reversed once the capacitor voltage reaches a
threshold value. However, there is a delay associated with this toggling.
During this delay, the capacitor continues to charge, and its voltage exceeds
the threshold level during the period until the direction of current is
effectively switched. As a result, the frequency of oscillation is also
reduced.
As the frequency of oscillation increases, this delay becomes
more and more problematic and causes the frequency to cease to depend
linearly on the charging current. A further consequence of this non-
linearity is that the maximum frequency, and therefore the frequency
range, for practical operation of the relaxation oscillator is reduced. Also,
since the delay is dependent on temperature and process, the oscillator
becomes overly sensitive to variations in these factors.
United States Patent No. 5,489,878 to Gilbert discloses a
sinusoidal quadrature oscillator with two gm/C integrator stages
interconnected in a feedback loop. Each gm/C stage includes a differential
pair of transistors, a capacitor, and a tunable current source. The input and
output terminals of each stage are cross-coupled to one another to produce
the necessary phase inversion between the inputs of each stage and thereby
produce oscillation. An optional start-up circuit provides a negative
resistance whose absolute value is equal to or greater than the input
reistance of the other or next gm/C integrator stage. The negative
resistance is used to compensate for the input reistance of the next stage
and by doing so, the start-up circuit ensures that oscillation can initially
occur at start-up. Because the oscillator operates based on a small signal
model (i.e. the oscillator works for signals about an operating point), the
transistors in each pair do not completely switch on and off. Rather both
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transistors in each stage remain on with the amount of current flowing
through the collectors of each transistor being determined by the
differential input between their base terminals. Since during oscillation
the input voltage of each stage modulates the current through the
charging capacitor, this current is not of constant magnitude (i.e. it is not
a
square wave with constant charging and discharging currents).
While other prior art oscillator circuits do generate
charging/discharging currents through the capacitor which are of constant
and equal magnitude, these typically include a common mode feedback
circuit and require complementary transistor devices to do so. Therefore,
yet another drawback of prior art relaxation oscillator circuits is that they
require common mode feedback circuitry and high quality complementary
transistors.
It is therefore an object of the present invention in one aspect
to provide an improved relaxation oscillator with an extended linear
frequency range. In another aspect, it is an object of the present invention
to provide a relaxation oscillator capable of generating equal charging and
discharging currents through a capacitor without requiring common mode
feedback circuitry and high quality complementary transistors.
SUMMARY OF THE INVENTION
The present invention in one aspect provides an oscillator
circuit, for generating an oscillating signal of a certain frequency,
comprising: a capacitance coupled between a first terminal and a second
terminal and adapted to have a voltage swing thereacross; a current supply
2.~ circuit coupled to said capacitance for providing a current through said
capacitance, the magnitude of said current being proportional to said
frequency and the polarity of said current being reversible; a switching
circuit coupled to said current supply circuit and responsive to one or
more control signals, for controlling the polarity of said current through
said capacitance; a DC shift providing circuit coupled to said capacitance for
providing a DC shift value in response to the voltage at said first terminal,
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the voltage at said second terminal, and a predetermined value; and a
control circuit coupled to said capacitance and said DC shift providing
circuit for generating said one or more control signals in response to said
voltage at said first terminal, said voltage at said second terminal, and said
DC shift value so as to maintain the voltage swing across said capacitance
substantially constant.
In another aspect the present invention provides a method
for generating an oscillating signal of a certain frequency, said method
comprising the steps of: (a) providing a current through a capacitance, said
capacitance being coupled between a first terminal and a second terminal
and said capacitor being adapted to have a voltage swing thereacross, the
magnitude of said current being proportional to said frequency and the
polarity of said current being reversible; (b) establishing the polarity of
said
current through said capacitance in response to one or more control
signals; (c) generating a DC shift value in response to the voltage at said
first terminal, the voltage at said second terminal, and a predetermined
value; and (d) generating said one or more control signals in response to
said voltage at said first terminal, said voltage at said second terminal, and
said DC shift value so as to maintain the voltage swing across said
capacitance substantially constant.
In yet another aspect, the present invention provides an
oscillator circuit for generating an oscillating signal of a certain
frequency,
said oscillator circuit comprising: (a) a capacitance coupled between a first
terminal and a second terminal; (b) a current supply circuit for providing a
?5 current through said capacitance, the polarity of said current being
reversible, Said current supply circuit comprising a DC power supply, a first
resistance coupled between said DC power supply and said first terminal, a
second resistance coupled between said DC power supply and said second
terminal, the resistance across said second resistance being equal to the
resistance across said first resistance, a negative resistance coupled between
said first terminal and said second terminal, the magnitude of the
resistance across said negative resistance being equal to the sum of the
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magnitude of said first resistance and the magnitude of said second
resistance, and a current source for generating a sink current out of a third
terminal, the magnitude of said sink current being proportional to said
frequency; and (c) a control switching circuit coupled to said current
supply circuit for controlling the polarity of said current through said
capacitance by alternately coupling either said first terminal to said third
terminal or said second terminal to said third terminal, such that the
magnitude of the current through said capacitance is substantially equal to
one half the magnitude of said sink current.
BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings which illustrate a preferred
embodiment of the invention:
Fig. 1 is a typical differential relaxation oscillator according to
the prior art.
Fig. 2 shows the voltage waveform for the oscillator of Fig. 1
at a terminal of the capacitor .
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Fig. 3A illustrates how the Automatic Swing Control (ASC)
feedback of the present invention linearizes the current-frequency
characteristic of the oscillator of Fig. 1.
Fig. 3B illustrates how the ASC feedback of the present
invention maintains the capacitor voltage swing of the oscillator of Fig. 1
constant.
Fig. 4 is a block circuit diagram of the preferred embodiment
of the present invention.
Fig. 5 is a more detailed circuit diagram for the circuit of Fig.
4.
Fig. 6A is a simulation result of how the ASC feedback of the
present invention linearizes the current-frequency characteristic of the
oscillator of Fig. 5.
Fig. 6B is a simulation result of how the ASC feedback of the
present invention maintains the capacitor voltage swing of the oscillator
of Fig. 5 constant.
_DETAILED DESCRIPTION OF THE INVENTION
Fig. 1 shows a typical prior art circuit for a differential
relaxation oscillator 10. Note that oscillator 10 is a voltage controlled
oscillator (VCO), whose frequency of operation is controlled by the V~ontrol
signal 12 which is converted to a charging current supply 16 by voltage-to-
current (V/I) converter 14.
The operation of oscillator 10 is based on alternately charging
and discharging the terminals of capacitor C between two threshold
voltage levels. In a differential realization, the two opposite phases of the
capacitor voltage can be alternately compared with one threshold voltage.
Charging current supplies 16 and 18 provide a reference current I across
the capacitor, the direction of which depends upon the configuration of
switch 20. Switch 20 may comprise a pair of voltage or current controlled
switches, such as a differential pair of transistors whose bases each receive
a controlling bias voltage. As shown in Fig. 1, when the voltage at the first
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capacitor terminal V~1 reaches the threshold voltage, as determined by
comparator 22, a bistable circuit such as SR latch 26 has its output 28 set.
When the voltage at the second capacitor terminal V~2 reaches the
threshold voltage, as determined by comparator 24, the output 28 is reset.
The output 28 of SR latch 26 controls the state of switch 20 so that once the
appropriate threshold is reached the polarity of the current through the
capacitor is reversed. The voltage swing at each terminal of the capacitor is
the total variation in the level of the voltage at that terminal (i.e. the
difference between the maximum voltage level and the minimum voltage
level at the terminal).
A common-mode feedback (CMFB) circuit 30 maintains the
average or common-mode value of voltages V~1 and V~Z equal to a
constant predetermined reference value VIM, i.e. VIM = (Vcl + Vc2)~2.
This is accomplished by CMFB control signal 32 which keeps the value of
charging current supply 18 equal to one-half the value of charging current
supply 16. The voltage at each terminal of the capacitor swings about the
voltage VIM between two levels: VS and -VS where VS = Vth - Vcivt and is
the maximum difference of a capacitor terminal voltage away from VIM.
Thus, VS is the amplitude of the capacitor terminal voltage swing, as
illustrated at 34 in Fig. 2 which shows the voltage waveform at one of the
capacitor terminals (i.e. V~1 or V~2). As a result, the differential voltage
across the capacitor C (i.e.. V~1 - V~2 or V~2 - Vcl) swings between two
levels: 2VS and -2V5, so that 2VS is the amplitude of the differential
capacitor voltage. The differential voltage across the capacitor can be taken
as the double-ended output of the oscillator circuit 10, or alternatively a
capacitor terminal voltage may be taken as a single-ended output with
respect to a ground or reference voltage.
Assuming that the reference current through C is constant in
the circuit of Fig. 1, the current can then be expressed as
I = C TS (1)
8
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(where T is the period of oscillation) so that the frequency of oscillation is
given by
_ I , (2)
SCVS
which varies linearly with I. Practically, however, there is a delay, Ta (see
Fig. 2), between the time a capacitor terminal voltage reaches the threshold
level and the time the switch 20 changes state and reverses the direction of
the current through capacitor C. During this time, the differential voltage
across the capacitor continues to rise (or fall) in the same direction by the
amount
ITd (3)
°VS C
so that the effective amplitude of the differential capacitor voltage swing
becomes 2VS, eff~ where
° V 5 ITd (4)
VS.~(I) = VS + 2 - VS + 2C
and, as a result, the frequency of oscillation drops to
_ I _ 1 (5)
8CVS,~(I) 8CV
I S +4Td
The reduction in frequency due to the time delay Td is also illustrated
graphically in Fig. 2 by capacitor voltage waveform 36.
As a result of the delay Td, the frequency as expressed in
equation (5) is no longer a linear function of the current, as the voltage
swing is limited to ~2VS, eff and not ~2VS. Also, as I is increased, the
frequency slowly approaches its maximum limit f maX = 1 / (4Td). Operation
of the circuit of Fig. 1 at or near f max is impossible in practice because it
requires too much current in addition to an unreasonably large voltage
swing handling capability. In addition, because Td is dependent on both
temperature and process, the oscillator 10 is overly sensitive to these
effects.
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In the present invention, the peak value of the capacitor
voltage swing is extracted and employed in a feedback loop which
dynamically alters Vth (i.e. the level of V~1 or V~2 at which the polarity of
the charging/discharging current across the capacitor is reversed) to keep
VS, eff constant and equal to a reference swing amplitude voltage VS, ref' As
a
result, the I-f characteristic becomes linear and operation at or near the
maximum frequency of oscillation f max becomes practically achievable
when the feedback loop forces VS to zero (or equivalently Vth to equal
VIM). Fig. 3A shows an example of how the automatic swing control
(ASC) feedback linearizes the I- f characteristic of the oscillator of Fig. 1,
with Td = 300 ps and C = 1 pF arbitrarily chosen. In Fig. 3A, the I- f
characteristic without ASC feedback is shown at 38 and the I- f
characteristic with ASC feedback is shown at 38'. Fig. 3B illustrates how the
automatic swing control (ASC) feedback maintains the capacitor voltage
swing of the oscillator of Fig. 1 constant, for those same arbitrary values.
In Fig. 3B, the current-voltage swing characteristic without ASC feedback is
shown at 39 and the current-voltage swing characteristic with ASC
feedback is shown at 39'.
Fig. 4 shows an implementation of a relaxation oscillator 40
with ASC feedback according to a preferred embodiment of the present
invention. Pull-up resistors 42 and 44 which are of equal value (denoted as
R) are used instead of current supply 18 (shown in Fig. 1) which eliminates
the need for high performance PNP or PMOS current sources. This
implementation is advantageous since it obviates the need for a CMFB
circuit to control the amount of current sourced as well as the need to use
complementary transistor devices to generate charging/discharging
currents of equal magnitude and opposite polarity. The negative resistance
46, which is twice the magnitude of the pull-up resistors 42 and 44,
compensates for current variations across resistors 42 and 44 due to
changes in voltage across them. As is well understood in the art, a
negative resistance can be obtained from a device in which an increase in
the applied voltage increases the resistance and thereby produces a
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CA 02283892 1999-09-16
proportional decrease in current (examples include tunnel diodes and
silicon unijunction transistors). This implementation is equivalent to
having an infinite time-constant in the RC network, and as a result, the
capacitor C is charged and discharged with a current of constant magnitude
I, such that
I = V cc ' VcM (6)
R
where Vcc is the reference voltage connected to resistors 42 and 44 and R is
the value of the resistance across resistor 42 and resistor 44. As indicated
by
Equation (6), the common-mode voltage VIM decreases linearly with the
magnitude of the charging/discharging current I (and therefore also with
the frequency of oscillation f ). This is in contrast to the prior art circuit
of
Fig. 1 where the value of VIM remains constant and is independent of the
magnitude of the charging/discharging current I.
Referring still to Fig. 4, the effective amplitude of the voltage
swing VS, eff is extracted in circuit 52 by subtracting the average value of
the
V~1 and V~2 voltage signals from the peak value of the V~1 and V~2
voltage signals. Alternatively, the oscillator 40 could be configured to
extract some other characteristic value, such as the root-mean-square
(RMS) value, from the V~1 and V~2 voltage signals which also enables the
determination of a value proportional to the voltage swing VS, eEf- ~ Fig. 4,
circuit block 52 comprises RC-averaging and peak detector circuitry, both of
which are well known in the art. The difference signal, VS, eff~ output by
circuit 52 is compared at 54 with reference voltage VS, ref. The error or
difference outputted by comparator 54 is amplified and filtered by low pass
filter 56 before being fed to DC level shifting circuits 58 and 60 which
adjust
or shift the DC level of the signals 66 and 68 respectively. The ASC
feedback loop provides the necessary DC level shift adjustment to provide
a constant voltage swing across capacitor C which is independent of the
magnitude of the current. By adjusting the DC level shift VS in this
manner and by having a sufficiently large DC gain in the ASC feedback
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loop, VS, eff is forced to equal the constant reference VS, ret~ and the
frequency becomes a linear function of the current
_ I _ 1
~ max -
8C V s. ref ~ 4T d
The average or common-mode voltage of the capacitor
terminals (VIM = (Vcl + Vc2)/2) serves as the threshold voltage for the SR
latch 64. Signals 66 and 68, which are respectively the capacitor C terminal
voltages V~l and V~2 DC level shifted downward by VS, are used to set and
reset the latch 64. The Q and Q outputs of latch 64 control the state of
switching transistors 48 and 50 respectively (which form a differential pair)
and therefore the direction of the charging/discharging current through
capacitor C. As in Fig. 1, the charging/discharging current and therefore
the frequency of oscillation may be controlled by a control voltage or
current signal, as illustrated in Fig. 4 by the V~ontrot signal 12 and the
voltage to current (V/I) converter 14. Note that if the differential
oscillator
output is taken between the base terminal of transistor 48 and the base
terminal of transistor 50 (or alternatively between one of these base
terminals and a reference terminal, such as ground), the output waveform
will be a square wave, as opposed to the triangular capacitor voltage
waveform shown in Fig. 2.
In an alternate embodiment of the present invention (not
shown), the V~1 and V~2 voltage signals may be used to set and reset the
SR latch, where the threshold voltage of the latch is the average or
common-mode voltage of the capacitor voltage terminals VIM shifted
upward by the DC shift value VS.
As already indicated, operation of the oscillator of the present
invention at or near the maximum frequency of oscillation f max becomes
practically achievable as the feedback loop forces VS to zero. When this
occurs, the voltage swing VS, eff is equal to the voltage developed during
the charging of the capacitor C over the period Td. Since VS, eff is forced to
equal the reference VS, ref this implies that Vs, ref should equal the value
of
o V S at the maximum frequency of operation, i.e.
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V s, rei - D V s 8)
f max
Fig. 5 shows a detailed
circuit diagram for the oscillator 40 of Fig. 4. Given the above description,
the operation of the circuit of Fig. 5 is well understood by those skilled in
the art and so is only described briefly here. Referring to Fig. 5,
transistors
Q3 and Q4, whose bases and collectors are cross-coupled, and resistor R3
form the negative resistance 46, where resistor R3 is twice the magnitude
of the pull-up resistors 42 and 44 (respectively R1 and R2 in Fig. 5). Since
transistors Q3 and Q4 are configured as voltage followers, the voltage
difference between the collector of Q3 and the collector of Q4 will be
approximately equal to the voltage difference between the emitter of Q4
and the emitter of Q3 (i.e. across resistor R3). A negative resistance of -2R
is
therefore generated between the collectors of Q3 and Q4. Alternatively, this
negative resistance circuit can be improved by adding a first diode-
connected transistor between the collector of Q3 and the V~1 node and a
second diode-connected transistor between the collector of Q4 and the V~2
node. Such an improvement is described in Lee, T.H. and Bulzacchelli, J.F.,
"A 155-Mhz Clock Recovery Delay -- and Phase-Locked Loop", IEEE
Journal of Solid-State Circuits, Vol. 27, No. 12 (December 1992) p. 1736,
which is incorporated herein by this reference.
Referring still to Fig. 5, resistors R6 and R~, and capacitor C2
extract the average value of the capacitor C voltage signal, with transistor
Q 9 acting as a buffer, which is then fed to the SR latch consisting of
resistors R4 and R5 and transistors QS and Q6, Q~, and Q8. Transistors Q~
and Q8 toggle (i.e. set and reset) the state of the SR latch. The peak value
of
the capacitor C voltage is extracted by transistors Ql8 and Q19 and capacitor
C4. The common mode voltage of the capacitor terminals is extracted by
transistors Q16 and Ql~, resistors R$ and R9, and capacitor C3. Note that
while the average and common-mode values of the capacitor C voltage are
theoretically equivalent, the circuit of Fig. 5 comprises separate circuitry
for
extracting these signals since the average detecting circuitry must include a
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buffer and the circuit for extracting the common mode voltage must be
compatible with the peak detection circuitry (i.e. transistors Q16 and Ql~
should match transistors Ql8 and Q19). Transistors Q2o, Q2n Q22~ and Q23
and resistors Rlo, Rm, R13, and R14 subtract the extracted or effective swing
voltage from VS, ref and amplify the resulting error signal. Transistors Q24
and Q25 and resistor R12 are in a positive feedback configuration which
enhances the voltage gain of the error amplification. The value of R1~ is
chosen so that the gain enhancement does not introduce hysteresis to the
error amplifier transfer characteristic. Capacitors CS and C6 and resistor R15
comprise a low pass filter and determine the dynamic behaviour of the
feedback loop including its settling time. After the ASC loop has settled,
the final value of the error signal, Ve - V e, determines the portion of the
tail current sources of transistor pairs Q28-Q29 and Q3o-Q3i which are
required to develop VS, the DC voltage drop across each of resistors Rlb
and Rl~.
The circuit of Fig. 5 can be designed to have a frequency sweep
range from the order of 10 MHz up to 1 GHz, with the upper frequency
limit dictated by the value of Td, equal to approximately 250 ps. Fig. 6A
shows a SPICE simulation of the circuit of Fig. 5 illustrating how the
automatic swing control (ASC) feedback linearizes the I- f characteristic in
comparison to the same circuit (designed so that it oscillates at 100 MHz
with the equivalent charging current and voltage swing) with the ASC
feedback loop disabled. In Fig. 6A, the simulated I- f characteristic without
ASC feedback is shown at 70 and the simulated I- f characteristic with ASC
feedback is shown at 70'. Fig. 6B shows a SPICE simulation of the circuit of
Fig. 5 illustrating how the ASC feedback maintains the capacitor voltage
swing constant, again in comparison to the same circuit with the ASC
feedback loop disabled. In Fig. 6B, the current-voltage swing characteristic
without ASC feedback is shown at 72 and the current-voltage swing
characteristic with ASC feedback is shown at 72'. As can be seen from Figs.
6A and 6B, the ASC loop successfully regulates the amplitude of
oscillations over virtually the entire frequency range of operation. As a
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result of this regulation, the frequency drop observed for the conventional
oscillator has been greatly overcome. In addition, because the negative
effect of Td on the oscillator is reduced in the present invention, the
oscillator also becomes less sensitive to the effects of temperature and
process (since Td is dependent on both of these).
It should be clear that the present invention is in no way
limited to collector-coupled oscillators and can also be applied to other
types of relaxation oscillators in which the switching or toggling delay (i.e.
the delay between the capacitor voltage reaching a threshold level and the
reversal of the polarity of the current through the capacitor) causes
undesirable increases in the capacitor voltage and decreases in the
frequency of oscillation.
While preferred embodiments of the present invention have
been described, the embodiments disclosed are illustrative and not
restrictive, and the scope of the invention is intended to be defined only by
the breadth and spirit of the appended claims.
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