Note: Descriptions are shown in the official language in which they were submitted.
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CONVERSION CIRCUIT FOR AN ELECTROMAGNETIC
FLOW TRANSMITTER
This is a division of co-pending Canadian
Application 2,066,571, filed September 13, 1990.
BACKGROUND OF THE INVENTION
The present invention relates to magnetic flow
meters, and in particular, to circuits for converting
sensed flow potential to an output.
In pulsed-DC electromagnetic flow meters, a
transmitter provides a low frequency (typically 3-40 Hz)
square wave current to coils on a flow tube to produce
a square wave magnetic f field in conductive f luid f lowing
through the flow tube. The magnetic field generates a
square wave potential having an amplitude proportional
to the flow according to Faraday's Law at electrodes on
the flow tube. The potential is coupled through a cable
back to the transmitter. The frequency of the square
wave excitation is selected high enough to avoid
interference from low frequency noise present in the
flowing fluid, but low enough so that capacitive loading
of the cable and inductive effects from the coils do not
substantially distort the amplitude of the square wave
potential. The flow transmitter converts the amplitude
of the square wave potential to an output representing
flow.
In the past a variety of conversion circuits
have been used. Typically, the square wave potential is
demodulated, providing a DC potential which, in turn, is
presented to a voltage controlled oscillator (VCO) which
provides a VCO frequency indicative of flow. Since a
demodulated DC potential is presented to the VCO for
conversion to a frequency, conversion accuracy depends
on the zero point stability of the VCO. Maintaining the
accuracy of the VCO at a desired level (0.1% of reading
over a 50:1 range of flow, for example) over a long
period of time with changes of temperature has been a
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problem. An arrangement is thus needed which does not
require a high accuracy VCO for conversion.
Various circuits have also been used to
convert the VCO frequency to an electrically isolated,
adjustably scaled 4-20 mA analog output. Typically, the
VCO frequency output is coupled to a divider which is
adjustable to provide scaling. The output of the
divider is fed through an optical coupler to a frequency
to current converter circuit which converts the scaled
frequency to a 4-20 mA output current. There is a
desire to also provide a scaling adjustment with a wide
range of adjustment, while providing a smooth, accurate
conversion to a 4-20 mA output current from the scaled
frequency.
SUMMARY OF THE INVENTION
In accordance with the present invention,
there is provided a digital-to-analog converter for
converting a representation of a quantity in the form of
a sequence of digital values received at a first input
thereof to corresponding analog signal values provided
at an output thereof, the converter comprising: a
digitally controlled signal generating means having an
output and having a first input serving as the converter
input, the digitally controlled signal generating means
being capable of providing an oscillatory output signal
at the output thereof having a variable frequency of
values which depend on corresponding ones of the digital
values provided at the first input; a switching means
having a control input electrically connected to the
digitally controlled signal generating means output and
having a current pass input, the switching means being
capable of drawing a selected current through the
current pass input thereof under direction of the
signals applied to the control input thereof; and a
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current controlled signal generating means having a
control input and an output, the current controlled
generating means being capable of providing an output
signal at the output thereof having values which depend
on values of current being drawn at its control input.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. lA and 1B together show a mixed block
and circuit schematic diagram of a flowmeter embodying
the present invention; and
FIG. 2 shows a timing diagram of electrical
signals from the circuit shown in FIGS. lA and iB.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
In FIG. lA, coil driver 15 generates current
I12 which flows through electromagnet 12. Reference
potential 15' coupled to coil driver 15 controls the
amplitudes of current I12. Current I12 is substantially
a square wave as shown in FIG. 2 having a low repetition
frequency controlled by sequencer 17. Sequencer 17 is
preset to a selected low frequency by the user.
Electromagnet 12 generates a magnetic field B transverse
to a f low of f luid 11 in f low tube 10 . Electrodes -13 ,
14 sense flow output Vll, a potential generated
according to Faraday' s Law in f luid 11. Flow output V11
has an amplitude proportional to square wave current I12
multiplied times the velocity of fluid il through flow
tube 10, but is subject to undesired noise and offset
potentials.
Amplifier circuit 18 receives flow output V11
and amplifies it in a temperature-stable manner, filters
some noise from it, and converts it to an amplified
output V18 which is referenced to DC common conductor
15". Filtering in amplifier circuit 18 can be various
forms of known analog filtering, or digital filtering
controlled by sequencer 17. Amplified output V1a is
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representative of flow, but is subject to noise and
offsets not completely eliminated by amplifier circuit
18.
Amplified output V18 is coupled to sample-and-
hold circuit 19 comprising hold capacitors 22, 23 and
solid state switches 20A, 20B, 21A, 21B controlled by
sequencer 17. The sequencer 17 closes switches 20A,
20B, 21A, 21B by applying positive levels of control
outputs V2oA, V2os~ V21A~ V2ls respectively in
synchronization with the square wave current I12 as
shown in FIG. 2. Switch 20A is closed during a time
interval near the end of a positive half cycle of
current I12, thereby coupling the amplified output V18
to capacitor 22 during a positive half cycle of current
I12. Switch 21A is closed during a time interval near
the end of a negative half cycle of current I12, thereby
coupling the amplified output V18 to capacitor 23 during
a negative half cycle of current I12. Switches 20A, 21A
are closed long enough during their respective half
cycles to permit charging the hold capacitors 22, 23 to
store substantially the potential of the amplified
output V18.
As shown in FIG. 2, switch 20B is closed to
couple the potential stored on capacitor 22 to sample
and-hold output V19 during one half of a cycle time of
the square wave current I12; during the other half of
each cycle time, switch 21B is closed to couple a
potential stored on capacitor 23 to sample-and-hold
output V19. Switch 20A is held open when switch 20B is
closed; and, switch 21A is held open when switch 21B is
closed so that noise spikes are not coupled from
amplified output V18 through the sample-and-hold circuit
19 to the sample-and-hold output V19. The sample-and-
hold output V19 thus alternates between two potentials,
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and the difference between these two potentials
represents the flow output V11. The sample-and-hold
circuit 19 modulates the sample-and-hold output V19 with
a low frequency square wave which has the same frequency
as the square wave modulation of the coil current I12~
The sample and hold output V19 is thus modulated rather
than demodulated.
Coil drive 15 full-wave rectifies current I12
to provide rectified current I12' through current
sensing resistor 16. The current flowing through
resistor 16 is thus substantially free of low frequency
modulation at the excitation frequency. Current sense
resistor 16 thus develops a single polarity output V16
which is representative of the amplitude of coil current
I12. The output V16 is coupled to a low pass filter
comprising switch 27, resistor 28, and hold capacitor 29
which filters out amplitude variations within a coil
drive cycle. The sequencer 17 provides a control output
V2~ which controls actuation of switch 27 as shown in
FIG. 2. Switch 27 samples the rectified (that is,
demodulated) output from current sensing resistor 16 and
stores the sampled potential through resistor 28 on hold
capacitor 29. The potential stored on capacitor 29 is
thus representative of average amplitude of the current
I12, but is relatively free of variations which occur
within an excitation cycle, such as asymmetry. Amplifier
amplifies the potential stored on hold capacitor 29
and couples an output V3o representative of current
amplitude through switch 31 and resistor 26 (FIG. 1B) to
30 supply current to correction output I26. The output V3o
is also coupled to a unity gain inverter comprising
operational amplifier 32 and resistors 33, 34. The
output of amplifier 32, which also represents the
current amplitude, but has a polarity opposite the
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polarity of the output of amplifier 30, is coupled
through switch 35 and resistor 26 (FIG. 1B) to supply
current to correction output I26.
In FIG. 1B, correction output I26 is coupled
to a negative or inverting input of an integrator
comprising amplifier 24 and capacitor 25. The sample
and-hold output V19 is coupled to a positive input of
the integrator comprising amplifier 24 and capacitor 25.
The integrator generates an integrator output V24 which
is an integrated difference between the sample-and-hold
output V19 and the correction output I26. Integrator
output V24 couples to the voltage sensing input of
voltage controlled oscillator (VCO) 36. VCO 36 generates
an oscillator output V36 which has a frequency F which
increases when the potential at the voltage sensing
input increases, but can be subject to drift due to
aging or temperature changes.
The oscillator output V36 is illustrated in
FIG. 2, however, the frequency is not shown at the same
scale as other portions of the timing diagram. The full
scale output frequency of the VCO is much higher than
the coil drive frequency, typically 100 to 10,000 times
higher, however, lower output frequencies are shown in
FIG. 2 merely for clarity of illustration. The
frequency of the oscillator output V36 is frequency-
modulated (FM) by the square wave potential V24 sensed
at the VCO input as shown in FIG. 2. The frequency of
the oscillator output deviates to upper and lower
deviation frequencies corresponding to the two levels of
3 0 the square wave f low output . The difference between the
upper and lower deviation frequencies is representative
of flow.
A clock 40 associated with microprocessor
system 39 provides a clock output V4o which provides a
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stable frequency reference, and is preferably crystal-
controlled.
The oscillator output V36 and the clock output
V4o are coupled to frequency-to-duty cycle converter
circuit 37. Converter circuit 37 provides duty cycle
control outputs V3~_1 and V3~_2 which are logical
complements of one another. The duty cycle control
output V3~_1 has a duty cycle which is directly related
to the frequency of the oscillator output V36. The duty
cycle control output V3~_2 has a duty cycle which is
inversely related to the frequency of the oscillator
output V36. Such frequency-to-duty cycle conversion
circuitry is known, for example, from U.S. Patent
4,309,909 to Grebe, Jr. et al.
Control output V3~_1 controls actuation of
switch 31 so that the closure time or duty cycle of
switch 31 is directly related to the frequency of
oscillator output V36. Control output V3~_2 controls
actuation of switch 35 so that the closure time or duty
cycle of switch 35 is inversely related to the frequency
of oscillator output V3s~
Operation of converter 37, switches 31, 35 and
amplifier 30, 32 complete a feedback loop from
oscillator output V36 back to the voltage sensing input
of VCO 36 which linearizes the frequency of the
oscillator output V36 with respect to integrated output
V24 and thus with respect to flow output V31 as well.
The sample-and-hold output V19 and the
correction output I26 both have amplitudes which are
directly proportional to the current I12. The
integrator amplifier 24 effectively subtracts these two
outputs so that the oscillator output V36 is
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substantially independent of variation of the amplitude
of the current I12~
The VCO's output potential V36, the clock
output V4o and a synchronizing output Vl~ from sequencer
17 are all coupled to counter 38. Counter 38 counts or
accumulates the number of oscillations of the oscillator
output V36 during a predetermined time interval
controlled by the clock output. Synchronizer output V1~
synchronizes counting in counter 38 with coil drive and
sample-and-hold operation, so that one count is
accumulated while the oscillator output V36 is at a
steady higher frequency level (corresponding to a
positive value of current I12) and a second count is
accumulated while the oscillator output V36 is at a
steady lower frequency level (corresponding to a
negative value of current I12). The counter 38 provides
the first and second counts to microprocessor system 39
as two digital words.
Microprocessor system 39 subtracts the first
count from the second count to calculate a difference
between the two counts. Since both counts are affected
in substantially the same way by DC offsets or zero
shifts in the sensed, amplified, and sampled flow
signal, the digital subtraction cancels the offsets.
Since microprocessor 39 performs the subtraction
digitally, offsets associated with analog subtraction
are not introduced. Microprocessor system 39
effectively digitally demodulates the flow signal, that
is, removes the square wave drive component from the
flow signal, without introducing additional offset.
Accuracy of measurement does not depend on zero point
stability in voltage controlled oscillator 36 or
integrator 24.
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The microprocessor system 39 also stores
correction constants in memory for further reducing non-
linearities. The microprocessor generates an output D39
comprising a digital word defining a division factor
proportional to the measured flow as calculated from the
two counts provided by counter 38. The division factor
is preferably a hexadecimal number with a integer and
fractional portion. The output D39 couples to a first
divider 41 which provides an output V41 which has a
frequency which is proportional or equal to the
frequency of the clock output V4o divided by the
division factor D3g. Digital frequency division by a
divisor having a integer and fractional part is known,
as shown for example in USA Patent 4,306,461 to Grebe,
Jr. The output frequency of first divider output V41 is
inversely proportional to the flow of fluid 11.
Output V41 of first divider 41 couples to an
optical coupler 42 which galvanically isolates, or
insulates circuitry referenced to the reference
potential 15" associated with the ground of flow tube 10
from a different reference potential 60 associated with
an isolated output circuit. Isolated output V42 of
coupler 42 provides the 'scaled frequency from the first
divider to second divider 43. Second divider 43 is a
divide-by-two circuit which provides output V44 and V4s
which are complementary flip-flop outputs, each having
a 50% duty cycle.
Outputs V44 and V45 actuate switches 44 and
45. When switch 45 is closed, amplifier 47 charges
capacitor 46 to the level of reference V61 coupled to
the amplifier 47. When switch 45 is opened and switch
44 is closed, the capacitor 46 is fully discharged
through a current limiting resistor in series with the
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switch 44. The frequency or rate of charging and
discharging is controlled by the frequency at the output
of the second divider which is inversely proportional to
flow. Current provided by amplifier 47 and output
potential V4~ are inversely proportional to flow.
The output V4~ of amplifier 47 provides a
current inversely proportional to flow through resistor
51 to a summing junction at an inverting input of
amplifier 50. Reference 61 provides a reference
l0 potential V62 to a non-inverting input of amplifier 50.
The output potential V5o of. amplifier 50 is
coupled through resistor 53 to a base of transistor 52.
Transistor 52 controls current in a two wire, 4-20 mA
loop energized at terminals 54, 55. Resistor 58
develops a potential proportional to current in the 4-20
mA loop, and the potential is coupled through a resistor
59 back to the summing junction to provide closed loop
control of the current in the loop.
A direct current power supply is coupled to
the loop at terminals 54, 55. A load device in the loop
represented by a resistor 56 receives the loop current
for monitoring or control.
Although the present invention has been
described with reference to preferred embodiments,
workers skilled in the art will recognize that changes
may be made without departing from the spirit and scope
of the invention.
