Note: Descriptions are shown in the official language in which they were submitted.
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TITLE OF THE INVENTION
PHASE-LOCKING OSCILLATOR WITH DUAL CHANNELIZERS
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates generally to phase-locking oscillators.
More particularly, the present invention pertains to phase-locking oscillators
that
can be channelized into small frequency increments, or steps, and that have
compare rates in the megahertz range.
Description of the Related Art
The frequencies of radio-frequency voltage-controlled oscillators (rf
VCO) have been controlled precisely by phase-locking a feedback signal from
the rf VCO to a crystal-controlled reference oscillator. A phase detector has
been used to determine the phase difference between the feedback signal and
the crystal-controlled reference frequency; an integrator has been used to
summate the phase differences, and the frequency of the rf VCO has been
varied in accordance with the phase difference.
Lautzenhiser, in U.S. Patent 5,091,706 which issued on 25 February
1992; in U.S. Patent 5,097,230 which issued on 17 March 1992; in U.S. Patent
5,311,152 which issued on 10 May 1994; in U.S. Patent 5,497,509 which
issued on 5 March 1996; and in U.S. Patent 5,802,462 which issued on 1
September 1998, teaches various methods for ac modulating, do modulating,
and channelizing the phase-locking oscillators.
These Lautzenhiser patents teach modulation of the feedback path by
swallowing pulses from the feedback path, or by preventing certain pulses from
progressing through the feedback path. This method of modulating changes the
number of pulses in the feedback path as an exact mathematical function of the
modulation frequencies.
Swallowing pulses in the feedback path while achieving exact
modulation has one limitation. Swallowing various ones of pulses in a stream
of equally-spaced pulses results in unequal spaces between pulses. Thus, the
output of the phase detector must be filtered sufficiently to prevent the
unequally-spaced pulses from causing incidental frequency modulation (IFM) in
the output frequency of the rf VCO.
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The result has been slower phase locking than is needed for some
applications. For instance, frequency-hopping oscillators may be required to
channelize and phase lock more rapidly than can be achieved in circuits that
utilize pulse-swallowing techniques.
S However, in all except the first of the above-listed references,
Lautzenhiser also teaches apparatus and method in which, rather than creating
an uneven flow of pulses in the feedback path by swallowing pulses, the
frequency in the feedback path is changed with the period of the wave form
remaining uniform. That is, the feedback frequency, as received from the rf
VCO, is changed in the feedback path as a function of a modulation frequency
to provide a new frequency with a uniform wave form. Thus, the amount of
filtration between the phase detector and the rf VCO can be reduced
drastically,
thereby greatly increasing the loop frequency.
The apparatus that is used to change the frequency in the feedback
path uniformly, as taught by Lautzenhiser, includes a quadrature-signal
generator and an image-rejecting mixer. A pair of bistable multivibrators are
used to form the quadrature-signal generator, also as taught by Lautzenhiser.
In the above-referenced patents, the compare rate has been 31.25 kHz.
However, for some applications a much faster compare rate is needed. The
present invention provides compare rates up to one MHz, or roughly 30 times
higher.
BRIEF SUMMARY OF THE INVENTION
In the present invention, small-step channelization of output
frequencies of a phase-locking oscillator is achieved by changing the
frequency
in the feedback path of the phase-locking oscillator at two different
locations,
and by different sizes of frequency increments.
In the first location and method, channelizing is by means of a
variable-modulus divider and a modulus controller in the feedback path, and by
counters associated with A and N inputs of an integrated chip, as taught in
handbooks, and the channelizing steps are relatively large.
In the second location and method, channelizing is done outside the
feedback path, and the channelizing steps are much smaller.
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By algebraically summing the smaller channelizing steps with the
feedback frequency, which is separately channelized as discussed above, the
present invention provides means for continuous-step channelization of a radio-
frequency band in small frequency increments.
In a first embodiment of the present invention, channelization into
small frequency increments is provided by a secondary phase-locking oscillator
and a second variable-modulus divider. A pair of bistable multivibrators
change
the small-step channelization frequencies to quadrature square waves, and a
pair of low-pass filters change the quadrature square waves to quadrature sine
waves.
In second and third embodiments, channelization into small frequency
increments is provided by a direct digital synthesizer (DDS), which preferably
is
of the type that produces quadrature outputs, and a pair of D/A converters
generate quadrature analog outputs from the quadrature digital outputs of the
DDS.
In a fourth embodiment, channelization into small frequency
increments is provided by cascaded binary-rate multipliers, or optionally, by
cascaded digital-rate multipliers. A pair of bistable multivibrators change
the
output of the cascaded devices into quadrature square waves, and a pair of low-
pass filters change the quadrature square waves to quadrature sine waves.
Channelization into small frequency increments is provided by any of
the means discussed above, and three optional means are used to develop
quadrature phases of the feedback frequency. In all four embodiments,
quadrature mixing is used to mix the small-step channelizing frequencies with
the frequency in the feedback path.
In the first and second embodiments, quadrature splitting is used to
develop quadrature phases of the feedback frequency. In the third
embodiment, a pair of bistable multivibrators and a pair of low-pass filters
are
interposed into the feedback path to develop quadrature phases. And in the
fourth embodiment, a quadrature phase shift keying mixer (QPSK mixer) is used
which is an image-rejecting mixer, and which develops its own quadrature
phases from an inputted frequency.
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Integrated quadrature phase shift keying mixers use an LC circuit for
quadrature splitting, and thus are frequency sensitive. And bistable
multivibrators will not operate as fast as quadrature splitters. Therefore,
quadrature splitters are preferred, because they have a wide bandwidth and are
capable of high frequency operation.
In all four embodiments, the compare rate of the primary phase-locking
oscillator is increased more than 30 times from 31.25 kHz to 1.0 MHz or
higher. Further, the compare rate of the secondary phase-locking oscillator in
the first embodiment, and the compare rate of the DDS in the second
embodiment is in the order of 600 nanoseconds.
Therefore, all four embodiments provide the advantages of small-
increment channelization combined with a high compare rate.
In a first aspect of the present invention, a method for producing
channelized output frequencies comprises: phase locking an output frequency
to a reference frequency; channelizing the output frequency into first
frequency
increments; separately channelizing the output frequency into second frequency
increments; and the separate channelizing step comprises phase locking a
second frequency, channelizing the second phase-locked frequency, and
quadrature mixing the channelized second phase-locked frequency with a
feedback from the output frequency.
In a second aspect of the present invention, a method for producing
channelized output frequencies comprises: phase locking an output frequency
to a reference frequency; channelizing a feedback from the output frequency
into first frequency increments; separately channelizing the feedback into
second frequency increments; and the separate channelizing step comprises
direct digital synthesizing the second frequency increments, and quadrature
mixing the second frequency increments with the a feedback from the output
frequency.
In a third aspect of the present invention, a method for producing
channelized output frequencies comprises: phase locking an output frequency
to a reference frequency; channelizing the output frequency into first
frequency
increments; separately channelizing the output frequency into second frequency
increments; and the separate channelizing step comprises cascaded fractional-
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rate multiplying a reference frequency into the second frequency increments,
and quadrature mixing the second frequency increments with a feedback from
the output frequency.
In a fourth aspect of the present invention, a channelizing oscillator
5 comprises: a first phase-locking oscillator; means, that is connected to the
first
phase-locking oscillator, for channelizing an output frequency of the first
phase-
locking oscillator by first frequency increments; means, that is connected to
the
first phase-locking oscillator, for separately channelizing the output
frequency as
a function of second frequency increments; and the means for separately
channelizing the output frequency comprises a second phase-locking oscillator
that is channelized into the second frequency increments.
In a fifth aspect of the present invention, a channelizing oscillator
comprises: a phase-locking oscillator; means, that is connected to the phase-
locking oscillator, for channelizing a feedback of the phase-locking
oscillator by
first frequency increments; means, that is connected to the feedback, for
separately channelizing the feedback as a function of second frequency
increments; and the means for separately channelizing the feedback comprises
a direct digital synthesizer that is connected to the phase-locking
oscillator.
In a sixth aspect of the present invention, a channelizing oscillator
comprises: a phase-locking oscillator; means, that is connected to the phase-
locking oscillator, for channelizing an output frequency of the phase-locking
oscillator by first frequency increments; means, that is connected to the
phase-
locking oscillator, for separately channelizing the output frequency as a
function
of second frequency increments; and the means for separately channelizing
comprises a plurality of cascaded fractional-rate multipliers that produce the
second frequency increments.
In a seventh aspect of the present invention, a channelizing oscillator
comprises: a phase-locking oscillator; means, that is connected to the phase-
locking oscillator, for channelizing an output frequency of the phase-locking
oscillator by first frequency increments; means, that is connected to the
phase-
locking oscillator, for separately channelizing the output frequency as a
function
of second frequency increments; and the means for separately channelizing
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comprises a plurality of cascaded binary-rate multipliers that produce the
second frequency increments.
In an eighth aspect of the present invention, a channelizing oscillator
comprises: a phase-locking oscillator; means, that is connected to the phase-
locking oscillator, for channelizing an output frequency of the phase-locking
oscillator by first frequency increments; means, that is connected to the
phase-
locking oscillator, for separately channelizing the output frequency as a
function
of second frequency increments; and the means for separately channelizing
comprises a plurality of cascaded digital-rate multipliers that produce the
second frequency increments.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
FIGURE 1 is a schematic drawing of a first preferred embodiment of the
present invention in which a feedback path of a primary phase-locking
oscillator is channelized by two methods, by channelizing the feedback path,
and by quadrature mixing, into the feedback path, small-step channelizing
frequencies provided by a secondary phase-locking oscillator;
FIGURE 2 is a schematic drawing of a second embodiment of the
present invention in which a primary phase-locking oscillator is channelized
by
two methods, by channelizing the feedback path, and by quadrature mixing,
into the feedback path, small-step channelizing frequencies provided by a
direct
digital synthesizer;
FIGURE 3 is a schematic drawing of a third embodiment of the present
invention, similar to that of FIGURE 2, except that a pair of bistable
multivibrators are used to convert the feedback frequency to quadrature form;
and
FIGURE 4 is a schematic drawing of a fourth embodiment of the
present invention in which either cascaded binary-rate multipliers, or
cascaded
digital-rate multipliers, provide small-step channelization.
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DETAILED DESCRIPTION OF THE INVENTION
Referring now to FIGURE 1, a channelizing oscillator 10 includes a
first, or primary, phase-locking oscillator 12. The primary phase-locking
oscillator 12 includes a voltage-controlled oscillator (VCO) 14, a divider 16
that
divides by 8, a dual-modulus divider 18 that selectively divides by P and P+1,
an integrated chip 20 with A and N inputs, a crystal 22, and an integrator 24.
The integrator 24 includes an operational amplifier 26, a capacitor 28,
and a lead resistor 30. The integrated chip 20 includes a reference oscillator
32, a phase detector 34, a variable-modulus divider 36, and a modulus
controller 38. Preferably, the integrated chip 20 is part no. 45152,
manufactured by Motorola. The reference oscillator 32 produces a frequency of
1.0 MHz that is crystal controlled by the crystal 22 which runs at 16.0 MHz.
The divisors of the dual-modulus divider 18 are 32 and 33.
In the preceding description, several components that lie between the
divider 16 and the dual-modulus divider 18 were omitted. The reason is, the
omitted components are not a part of the primary phase-locking oscillator 12.
That is, if the divider 16 were directly connected to the dual-modulus divider
18, the phase-locking oscillator 12 would be a complete phase-locking
oscillator, and an output frequency in an output conductor 40 could be
channelized by components and circuitry, as shown, and as will be discussed
subsequently.
The phase-locking oscillator 12 includes a forward path 42 and a
feedback path 44. The forward path 42 extends from the phase detector 34
and through a conductor 45 to the VCO 14. The feedback path 44 extends
from the VCO 14, through the divider 16 and the dual-modulus divider 18, to
the phase detector 34. As described, the phase detector 34 is not a part of
either the forward path 42 or the feedback path 44.
With regard to channelization, the modulus control line causes the
P/P+ 1 dual-modulus divider 18 to divide by P+ 1 for A times. The control line
then commands the dual-modulus divider to divide by P for the remaining N -
A times.
Continuing to refer to FIGURE 1, the channelizing oscillator 10 further
includes a secondary channelizer 46. The secondary channelizer 46 includes a
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second, or secondary, phase-locking oscillator 48, a divider 50, a quadrature-
signal generator 52, and low-pass filters, 54 and 56. The quadrature-signal
generator 52 will be describe in detail subsequently.
The channelizing oscillator 10 still further includes an image-rejecting
mixer, or quadrature mixer, 58 which will be described in detail subsequently.
The secondary phase-locking oscillator 48 includes a second voltage
controlled oscillator (second VCO) 60, a second integrated chip 62, and a
second integrator 64. The second integrator 64 includes a second operational
amplifier 66, a second capacitor 68, and a second lead resistor 70.
The integrated chip 62 includes a reference oscillator 72, a phase
detector 74, a variable-modulus divider 76, and an N input with its associated
counter. The secondary phase-locking oscillator 48 is channelized in a
conventional manner using the N input, its counter, and the variable-modulus
divider 76. Preferably, the integrated chip 62 is part no. 45152, manufactured
by Motorola.
Although a crystal 78 is shown in conjunction with the second
integrated chip 62, in practice only one crystal, 22 or 78, and one reference
oscillator, 32 or 72, would be used for both of the phase-locking oscillators,
12
and 48. Since only the N input of the second integrated chip 62 has been
used, the A input has been omitted from FIGURE 1, and since a modulus
controller in the integrated chip 62 is not used, it has been omitted from
FIGURE 1.
The quadrature-signal generator 52 includes a first bistable
multivibrator, or flip-flop, 80 and a second bistable multivibrator, or flip-
flop,
82 which are connected as shown in FIGURE 1. The first multivibrator 80 is
the in-phase or sine multivibrator; the second multivibrator 82 is the cosine
or
quadrature multivibrator. The bistable multivibrators, 80 and 82, produce
square waves that are in quadrature, as taught in detail in all except the
first of
the above list of Lautzenhiser patents.
The first bistable multivibrator 80 produces an I, or in-phase, signal in a
conductor 84, and the second bistable multivibrator 82 produces a Q, or
quadrature, signal in a conductor 86. The low-pass filter 54 receives the in-
phase signal as a square wave from the conductor 84, and produces an in-phase
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sine wave in an in-phase conductor 87. In like manner, the low-pass filter 56
receives the quadrature signal as a square wave from the conductor 86 and
produces a sine wave that is in quadrature in a quadrature conductor 88.
The image-rejecting mixer 58 includes a quadrature splitter, or
quadrature signal generator 90, an in-phase, or sine, mixer 92A, and a
quadrature-phase, or cosine, mixer 92B, and a combiner 94. FIGURE 1
indicates connections of rf, intermediate frequency, and local oscillator
terminals as RF, IF, and LO terminals, with the mixer 92A being the in-phase,
or sine, mixer, and the mixer 92B being the quadrature-phase, or cosine,
mixer.
The quadrature splitter 90 consists of rf line lengths on a substrate.
Although constructed in accordance with classic textbook design, since
quadrature splitters are frequency dependent, the quadrature splitter 90 is
designed for the frequencies that will be encountered. The combiner 94
includes a potentiometer 96 having an arm 98 and a resistance 100, and a pair
of resistors, 102A and 102B.
While filtration requirements for use with quadrature mixing are
minimal, the channelizing oscillator 10 requires a low-pass filter 104 and a
bandpass filter 106.
Continuing to refer to FIGURE 1, in operation, the VCO 14 of the
primary phase-locking oscillator 12 produces an output frequency in the output
conductor 40 that is phase locked to the reference oscillator 32. As a
practical
example, assume that the output frequency is in the 2.2 to 2.4 gigahertz band.
Further, for simplicity, assume that the output frequency is 2.4 Ghz.
The divider 16 divides the 2.4 Ghz by 8, reducing the frequency to
300 MHz, and the dual-modulus divider 18 divides alternately by 32 and 33,
so that a frequency a little lower than 10.0 MHz is delivered to the
integrated
chip 20.
It is important to remember that the compare rate of the phase detector
34 is 1.0 MHz. Thus the frequencies delivered to the VCO 14 can be adjusted
in 1.0 MHz frequency increments. However, the divider 16 divides the output
frequency of the VCO 14 by 8. Thus, a 1.0 MHz change in frequency in the
feedback path 44 after dividing by 8 requires that the VCO 14 change by 8.0
MHz to again achieve phase lock. Therefore the minimum channelizing step is
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8.0 MHz. However, as will be described subsequently, the secondary
channelizer 46 cooperates with the dual-modulus divider 18 and the modulus
controller 38, which function as a primary channelizer, to provide 1.0 MHz
steps.
5 The secondary phase-locking oscillator 48, as previously discussed, is
operating at a 1.0 MHz compare frequency. Thus, a minimum channelization
step at the output of the second VCO 60 is 1.0 MHz, and since the divider 50
divides by 2, the minimum channelizing step that can be delivered to the
bistable multivibrators, 80 and 82, of the quadrature-signal generator 52 is
0.5
10 MHz.
As taught in all but the first of the above-listed Lautzenhiser patents, the
signal generator 52, in addition to providing quadrature outputs, also divides
frequencies by 4, so that the minimum channelizing step, delivered to the
feedback path 44 by the quadrature-signal generator 52, is 125 kHz.
However, as previously discussed, the output frequency of the VCO 14
must change eight times as much as a channelizing step made in the feedback
path 44. Thus, it becomes apparent that 125 kHz channelizing steps made by
the secondary channelizer 46 result in 1.0 MHz channelizing steps at the
output of the VCO 14. It further becomes apparent that the secondary
channelizer 46 cooperates with the primary channelizing function of the dual-
modulus divider 18 and the modulus controller 38 to provide channelization
across an entire band in 1.0 MHz steps.
Referring now to FIGURE 2, a channelizing oscillator 110 includes
components which are like-named in accordance with reference numbers
shown on FIGURES 1 and 2 and the detailed description of FIGURE 1.
More particularly, the channelizing oscillator 110 includes the primary
phase-locking oscillator 12 of FIGURE 1, and the image-rejecting mixer 58.
The image-rejecting mixer 58 includes the quadrature splitter 90, the mixers,
92A and 92B, and the combiner 94, as shown in FIGURE 1 and as described
therewith.
Instead of using the secondary channelizer 46 of FIGURE 1, the
FIGURE 2 embodiment uses a secondary channelizer 1 12. The secondary
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channelizer 112 includes a direct digital synthesizer (DDS) 1 14 and D/A
converters 1 16A and 1 16B.
The direct digital synthesizer 114 is programmed to provide
channelizing frequencies in quadrature. In-phase and quadrature channelizing
frequencies are delivered in digital form to the D/A converters 1 16A and 1
16B,
respectively, by conductors 118A and 1 18B.
After conversion to analog form by the D/A converters 1 16A and 116B,
in-phase and quadrature channelizing frequencies are delivered to the mixers
92A and 92B, respectively, by conductors 120A and 120B. Quadrature mixing
is performed by the mixers 92A and 92B as described in conjunction with
FIGURE 1.
Referring now to FIGURE 3, a channelizing oscillator 130 includes the
primary phase-locking oscillator 12 of FIGURE 1 with like-named and like-
numbered components, and the secondary channelizer 112 of FIGURE 2.
1 5 However, instead of the quadrature splitter 90 of FIGURES 1 and 2, the
channeling oscillator 130 uses bistable multivibrators, or flip-flops, 132 and
134, and low-pass filters 136 and 138 to achieve quadrature splitting. The
first
multivibrator 132 is the in-phase or sine multivibrator; the second
multivibrator
134 is the cosine or quadrature multivibrator. Quadrature mixing is
accomplished by the mixers, 92A and 92B, which are included in the combiner
94, as taught in conjunction with FIGURE 1.
Therefore, the bistable multivibrators 132 and 134 and the low-pass
filters 136 and 138 cooperate to provide a quadrature splitter, or quadrature
signal generator 140. And, the quadrature splitter 140 and the combiner 94
cooperate to provide an image-rejecting mixer, or quadrature mixer, 142, which
replaces the image-rejecting mixer 58 of FIGURES 1 and 2.
Since quadrature splitting by use of bistable multivibrators has been
discussed in conjunction with FIGURE 1, it is not necessary to repeat it here.
However, it should be noticed that, in the FIGURE 3 embodiment, the bistable
multivibrators 132 and 134 are used to quadrature split the feedback
frequency,
rather than to quadrature split the small-step frequencies, as accomplished by
the bistable multivibrators 80 and 82 of FIGURE 1.
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The channelizing oscillator 130 uses the secondary channelizer 1 12 of
FIGURE 2, which includes the direct digital synthesizer (DDS) 114 and the D/A
converters 116A and 116B, which was discussed in conjunction with FIGURE
2, so no additional explanation for the secondary channelizer 112 is
necessary.
Referring now to FIGURE 4, a channelizing oscillator 150 includes the
primary phase-locking oscillator 12 of FIGURES 1, 2, and 3 with like-named
and like-numbered components. The channelizing oscillator 1 10 also includes
a QPSK (quadrature phase shift keying) mixer, quadrature mixer, or image-
rejecting mixer, 152 which combines the functions of the quadrature splitter
90,
the mixers, 92A and 92B, and the combiner 94 of FIGURES 1 and 2.
Although the QPSK mixer 152, which may be part no. QMC-100,
manufactured by Mini-Circuits Labs of Brookland, N.Y., combines the functions
of quadrature splitting and quadrature mixing, since it uses an LC circuit for
quadrature splitting, it is frequency sensitive, and so its bandwidth is
limited.
Therefore, use of the quadrature splitter 90 of FIGURES 1 and 2, together with
the combiner 94, is preferred.
Continuing to refer to FIGURE 4, the channelizing oscillator 150 of
FIGURE 4 includes a secondary channelizer 154. The secondary channelizer
154 includes a small-step signal generator 156 and the quadrature-signal
generator 52 of FIGURE 1.
The small-step signal generator 156 includes a reference oscillator 158,
and cascaded fractional-rate multipliers, 160A, 160B, and 160N which include
control inputs 162A, 162B, and 162N, where "N" represents the last of a
selected number N of cascaded devices.
The fractional-rate multipliers, 160A, 160B, and 160N may be either
binary-rate multipliers (BRM) or digital-rate multipliers (DRM). To reflect
the
optional use of BRM's and DRM's, they are labeled BRM/DRM 160A,
BRM/DRM 160B, and BRM/DRM 160N on FIGURE 4.
Although a separate reference oscillator, 158 has been shown and
described, in actual practice the reference oscillator 32 in the integrated
chip
20 would be used.
Binary-rate multipliers, part no. 14527, manufactured by Motorola, of
Scottsdale, Arizona, and digital-rate multipliers, part no. CD 4089,
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manufactured by RCA of Summerville, New Jersey, are suitable for use in the
embodiments of FIGURE 4 and can be cascaded in numbers greater than
shown herein, if smaller channelizing steps are desired.
Assuming that three digital-rate multipliers are used, such as are shown
and numbered herein, as opposed to using binary-rate multipliers, each of the
control inputs may be selectively set at any number from 1 to 9.
If the three control inputs, 162A, 162B, and 162N were set at 4, 8, and
2, respectively, the channelizing frequency would be equal to the frequency of
the reference oscillator 158, multiplied by (4/10 + 8/100 + 2/1000).
Therefore, it can be seen that each increase by one in the total number of
digital-rate multipliers will decrease the frequency increments of
channelizing
by a factor of ten.
Or, assuming that three binary-rate multipliers are used, such as are
shown and numbered herein, as opposed to using digital-rate multipliers, each
of the control inputs may be selectively set at any number from 1 to 16. If
the
three control inputs, 162A, 162B, and 162N were set at 11, 2, and 14,
respectively, the channelizing frequency would be equal to the frequency of
the
reference oscillator 158, multiplied by (11/16 + 2/256 + 14/4096).
Adding one additional binary-rate multiplier would reduce the
minimum frequency step of the secondary channelizer to the reference
frequency multiplied by 1/65,536, because each increase by one in the total
number of binary-rate multipliers will decrease the channelizing steps by a
factor of sixteen.
Finally, in the embodiment of FIGURE 4, the method includes cascade
multiplying; and cascade multiplying may be accomplished by cascading
binary-rate multipliers and/or digital-rate multipliers.
Referring again to FIGURES 2 and 3, any suitable direct digital
synthesizer may be used. For instance, components suitable for use in the
present invention are manufactured by QuaIComm Incorporated of San Diego,
California. Design data for direct digital synthesizers manufactured by
QuaIComm can be found in the Synthesizer Products Data Book 80-24127-1 A
8/97 supplied by QuaIComm. Direct digital synthesizers manufactured by
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QuaIComm do not include D/A converters. Therefore, separate D/A converters,
116A and 116B, have been shown and described.
Advantages of using the direct digital synthesizer 114 include high
speed operation and the ability to produce channelizing frequencies by 32 bit
conversion which allows frequency increments in the millihertz range. Of
course, rather extensive programming is required to produce complex functions,
such as selectively variable frequencies in quadrature.
One disadvantage of direct digital synthesizers is that, unless the
fidelity of the power supply is assured by battery backup, a power glitch can
result in the loss of programming information. And batteries can fail in
electronic devices stored for relatively long periods of time. Further, a loss
of
programming information might not become apparent until the occurrence of
disastrous malfunction, and loss of programming information might not be
subject to correction, even if loss of program information were to become
known.
In contrast, since the secondary phase-locking oscillator 48 of FIGURE
1 establishes phase lock without needing any programming information, not
only is it relatively unaffected by power glitches, but it will also recover
automatically from a momentary loss of power. Further, since the secondary
channelizer 154 of FIGURE 4 does not require extensive and volatile
programming, the channelizing oscillator 150 of FIGURE 4 is much more
reliable than the channelizing oscillators 110 and 130 of FIGURES 2 and 3,
respectively.
Referring now to both FIGURES 1-4, the four embodiments shown in
these drawings have, in common, the ability to channelize in small frequency
increments. In addition, all four systems have a 1.0 MHz compare rate.
As mentioned previously, some applications, such as frequency-
hopping oscillators, must have the ability to change to different channels
rapidly. These frequency-hopping oscillators must also be able to achieve
phase lock rapidly.
As mentioned above, swallowing pulses in a feedback path creates an
uneven flow of pulses, and this uneven flow of pulses requires rather severe
filtration to avoid incidental frequency modulation.
CA 02313132 2000-06-29
In contrast, quadrature mixing reduces the number of pulses while
retaining wave form and wave period integrity. Thus, by using quadrature
mixing, the amount of filtration between the phase detector and the rf VCO can
be reduced drastically, thereby greatly increasing the loop frequency.
5 When two sine waves are mixed by a conventional mixer, such as the
mixer 92A, the output includes two frequencies; one is the sum, and the other
is the difference of the two mixed frequencies. To select only one of the
frequencies, filtration must be used. However, for channelization, the small
difference between the sum and differences in frequencies are much too small
10 to successfully separate them by filtration.
In contrast, when two sine waves are mixed in quadrature, a sine wave
is produced whose frequency may be either the sum or the difference of the
sine waves that are mixed, as selectively determined.
A mixer operates by multiplying, so when two sine waves in
15 quadrature are mixed, the equations are: sina x sin~3 = 1/2 cos(a,Q) - 1/2
cos(a+,Q), and cosy x cos,Q = 1/2 cos(a,13) + 1/2 cos(a+~3). Therefore, when
the two products are algebraically summed, whether positively or negatively
summed, the unwanted term drops out.
Although, in a QPSK mixer the undesired one of the algebraically-
summed sine waves does exist, its power is down approximately 20 dB. Thus,
the problem of filtering to remove the undesired value is minimized, and a
higher loop frequency can be achieved without causing excessively-large
incidental frequency modulation (IFM) in the output frequency of a phase-
locking oscillator.
In quadrature mixing, to achieve maximum rejection of the unwanted
frequency, both the phase and amplitude of the mixed frequencies must be
matched closely.
With regard to phase matching, quadrature phase shift keying mixers
that are constructed as an integrated chip, such as the QPSK mixer 152 of
FIGURE 4, use an LC circuit for quadrature splitting, and thus are frequency
sensitive. Except when used at frequencies very close to the ones for which
they are matched, rejection of the unwanted signal is inferior to that of the
CA 02313132 2000-06-29
16
quadrature mixer 58 of FIGURES 1-3, since quadrature splitters, such as the
quadrature splitter 90, have wide bandwidths.
With regard to amplitude matching, the combiner 94 of FIGURES 1-3
includes means for amplitude balancing. In accordance with prior-art practice,
the combiner 94 would utilize four resistors, instead of using the two
resistors,
102A and 102B, and the potentiometer 96.
Use of the potentiometer 96, as opposed to using two resistors (not
shown) in series as a fixed voltage divider, allows individual-product
balancing,
or amplitude balancing, of the combiner 94, so that the unwanted signal is
down consistently by approximately 30 dB, several dB below that which can be
achieved without the amplitude matching that is provided by the potentiometer
96.
Since filtration requirements of quadrature mixing are minimal, the
channelizing oscillators 10, 1 10, 130, and 150 of FIGURES 1-4 may omit the
bandpass filter 106, especially when the image-rejecting mixer 58 of FIGURES
1-2, with both phase and amplitude matching, is used.
While only four embodiments have been shown, it should be
understood that a total of nine different channelizing oscillators are
included in
the present invention, since three secondary channelizers, 46, 112, and 154,
and three image-rejecting mixers, 58, 142, and 152, are taught herein, any one
of the three image-rejecting mixers, 58, 142, or 152, can be used with any one
of the three secondary channelizers, 46, 1 12, or 154.
While specific apparatus and method have been disclosed in the
preceding description, and while reference numbers have been included
parenthetically in some of the claims, it should be understood that these
specifics have been given for the purpose of disclosing the principles of the
present invention, and that many variations thereof will become apparent to
those who are versed in the art. Therefore, the scope of the present invention
is to be determined by the recitations of the claims.
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INDUSTRIAL APPLICABILITY
The present invention is applicable to phase-locking oscillators,
frequency-hopping oscillators, and both transmitters and receivers that use
phase-locking and/or frequency-hopping techniques.
