Note: Descriptions are shown in the official language in which they were submitted.
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ATM SWTTCH VOICE SERVER MODULE UTILIZING FLAG SIGNALLING
1. Field of the Invention
The present imrention relates broadly to the field of telecmnmunications. Mote
particularly, the present invention relates to a voice server module for an
asynchronous transfer
mode (ATM) switch or node which implements AALI, AAL2 and AALS adaptation as
well as
voice data processing. The AALI, AAL~, and AALS specifications (TTU-T
Recommendations
I363.1, I363.2 and I363.5) are hereby incorporated by reference herein in
their entireties.
2. State of the Art
Perhaps the most awaited, at~d now fastest growing technology in the field of
telecommunications in the 1990's is known as Asynchronous Transfer Mode (ATM)
technology. ATM is providing a ~chanism for removing performance limitations
of local arcs
networks (LANs) and wide area networks (WANs) and providing data transfers at
a speed of
on the order of gigabitsJsecond. The variable length packets of LAN and WAN
data are being
replaced with ATM cells which are relatively short, fixed length packets.
Because ATM cells
can carry voice, video and data across a single backbone network, the ATM
technology
provides a unitary mechanism for high speed end-to-end telecommunications
traffic.
In practice, ATM technology is presently being used primarily to pass data
according to
ATM adaptation layer (AAL) standards specification AALl (for serial data) and
specification
AALS (for packetized data such as LAN traffic) which have been completed for
some time. The
carrying of voice, on the other hand, has been limited because the Tl'CT
standanis specification
for AAL2 (for voice) has only recently been adopted.
While implementation of equipment for carrying out the standards with respect
to AAL2
is relatively straightforward, when the equipment is required to implement
more than just AAL2
(e.g., AAL1 and/or AALS in conjunction with AAL2), the complexity is increased
considerably. In addition, where voice processing (i.e., data compression)
such as ADPCM
(adaptive differential pulse code modulation) or silence removal is desired in
conjunction with
the implementation of AAL2, the complexity of the equipment is increased even
more. While
brute foire methods can be utilized to accomplish the desired complex tasks,
such solutions are
often too costly to be feasible. Thus, elegant techniques for implementing
voice processing in
ATM nodes implementing AAL2 ATM standards are needed, as well as elegant
techniques for
implementing ATM nodes which efficiently implement the AAL2 standard for voicx
and one ar
more of the AALl and AALS standards for data.
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SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a voice server module
for an ATM
switch.
It is another object of the invention to provide an ATM switch voice servo
module
which is capable of compressing voice data.
a is additional object of the invention to provide a voice server module for
an ATM
switch which implements both AALl and AAL2.
It is a further object of the invention to provide a flexible voice server
module for
processing data and voice information provided to an ATM switch on several El
or Tl lines
which carry numerous channels.
In accord with the objects of the invention, a voice server module for an ATM
switch is
provided and generally includes interface means for receiving and multiplexing
high speal
preprocessed data, voice processing means for compressing voice data which is
coupled to the
interface, adaptation layer processor means for receiving uncompressed data
arid comprised
data and for formatting the ur~ompr~essed data into ATM AALl format and the
compressod data
into ATM AAL2 format for sending to the ATM switch fabric, and management
processor
means for configuring the interface means, the voice processing means, and the
adaptation layer
processor means. Preferably, the interface means, the voice processing means,
and the
adaptation layer processor means of the voicx server module have reverse
functionality: i.e., the
adaptation layer processor means can take AAL2 and AALI formatted data and
generate
compressed and uncompressed data streams therefrom; the voice processing means
can take the
compressed data stream and generate an uncomprcss~ voice data stream
therefrom; and the
interface means can receive uncompressed data form both the adaptation layer
processor means
and the voice processing means and demultiplex the data for output.
Accaading to a first preferred aspect of the invention, the interface means
receives data
which originated from up to four E1 or Tl lines, and multiplexes the data into
a high spoed
serial data stream. The data stream is then sent both to the voice processing
means and to the
adaptation layer processor means, with the voice processing means ignoring all
but the voice
data portion of the data steam, and the adaptation layer processor means
ignoring the voice data
portion of the data stream. In this manner, AALl data is passed diroctly to
the adaptation layer
processor means without burdening the voice processing means, while data
destined to bec~ne
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AALZ type data is passed to the voice processing means for compression and
then forwarded in
a compressed foam to the adaptation layer processor means.
Acing to a second pmcferred aspect of the invention, the voice processing
mesas
comprises a series oaf arrays of digital signal processors (DSPs) in
conjunction with an array of
field programmable gate arrays (FPGAs); with each FPGA being assigned to an
array of DSPs.
Data cession between (to and from) the FPGAs and DSPs is according to a flame.
Thus,
the FPGAs are utilized to direct data rxeivod from the interface means and
from the adaptation
layer processor means to appropriate DSPs for pmcxssing. The DSPs are
preferably
pmogrammed to cxmduct various dssir~d voice processing algorithms, including
silence remo~ral
oc fnsertion, two- three- or four-bit ADPCM encoding and decoding, echo
cancellati~,
fax/modem torar detection, etc. Because of the nature of voice processing,
each of the DSPs
must be capable of significant processing power. At the same time, however,
power
ooasumption and costs must be considered. Thus, ding w the invention, DSPs are
selected which arc cable of processing two channels of voice simultaneously.
Acing to a third preferned aspect of the invention, data which is processed
and
oom~sod by the voice processing means is sent on a high speed serial bus to
the adaptation
~Ya P8 ~s in conjuncti~ with flags which are sent on another high spend serial
bus. In a first embodima~t of this aspect of the invartion, for each byte of
data (seat serially on
the high speed serial bus), at least one bit of flag data is sent on the flag
bus. In one
anaagement of this emboditrxnt, the flag ~t is used do indicate whether the
data on the high
speed data bus is valid ~ not (i.e., data or no data), tone detection, silence
removal, and the
type of encoding being utilized. In a second embodiment of this aspect of the
invention, ttar flag
bus is used both to synchronize the adaptation layer processing means and the
voice processing
means (preferably, acxording to a forty frame super&ame of five milliseconds)
as well as to
send control information. The control information includes a bit which
indicates whether the
data is comprtssod ac not, a bit to indicate silence, a bit- to indicate tone
detection, and a bit to
indicate an "out of data" indicat~n.
According to a fourth preferred aspect of the invention the management
processor means
utilizes a packet-type protocol in corresponding with the other elements of
the voice server
module. In additiosr, tlu management processor is configured to receive the
"D"-channels of
ISDN signals received by the voice server module interface, while the
adaptation layer
p~roc~ing mans is configured to format data according to the AALS format.
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According to additional preferred aspects of the voice server module, a
channel
associated signalling (CAS) processor is provided to process channel
associated signalling
(e.g., on-hook, off hook, ring, failure states, ete.) received by the voice
server module, while
the management processor is utilized to process D-channel signalling provided
with incoming
ISDN signals. Also, the management processor is provided access to all of the
DSPs in the
DSP arrays in order to configure the DSPs and obtain status information
therefrom. The DSPs
are preferably configured to provide one~or more of echo cancelling, silence
removal, data
compression and tone detection.
Additional objects and advantages of the invention will biome apparent to
those skilled
in the art upon reference to the detailed description taken in conjunction
with the provided
figures.
BRIEF DESCRIIrTION OF THE DRAWINGS
Figure 1 is a schematic diagram of an ATM switch incorp~ating the voice server
module of the invention;
figure 2 is a block diagram of the voice serve module of the invention;
figure 3 is a block diagram of the functional blocks of the interface means of
Fig. 2;
Figure 4 is a block diagram of the voice processing means of Figure 2;
Figure 4a is a block diagram of the functional blocks of each DSP of the voice
processing means of Figure 4;
Figure 5 is a block diagram of the functional blocks of the manage~nt
processor of
Figure 2; and
Figure 6 is a block diagram of the functional blocks of the CAS processor of
Figure 2.
DETAB.ED DESCRIPTION OF THE PREFERRED EMBODIMENTS
An ATM switch 10 such as the GDC APEX (a registered trademark of General
DataComm, Inc.) is seen in Fig. 1. The ATM switch 10 includes a mid-plane 14
having a
switch fabric card 15, a plurality of line interface modules (LIMs) 16a,
16b..., and a plurality of
c~trolleT cards (also called "slot controllers") 18a, 18b, .... The function
of each of the LIMB
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16 is to take incoming electrical or optical signal information from various
lines, such as data
channels, private networks, public networks, etc., to extract data and timing
information
therefrom, and to send a TTL digital signal representative of the data to an
associated controller
card 18. The controller cards include adaptation controllers and cell
controllers. The function
of the adaptation controller is to convert the TTL digital signals received
from LIMs receiving
legacy signals (e.g., Tl, E1) into an ATM signal (i.e., ATM adaptation). The
ATM signal is
then forwarded to the switch fabric for switching as desired. After switching,
the ATM signal
is pronrided to a cell controller which forwards the ATM signal to a LIM which
is couplod to the
ATM network (not shown).
According to the present invention at least one of the slot controllers 18 of
the ATM
switch 10 is a voice server module (VSM) which is configured to accept voice
data, as well as
other data from a LIM. In a preferned embodiment, each VSM slot controller
18VSM is capable
~ pmcessing data raxived from a LIM which is coupled to four El or Tl lines at
2.048
MbitsJsec or 1.544 MbitsJsec respectively. Where the LIM is coupled to Tl
lines, the LIM
performs a timing conversion such that the data presented to the VSM slot
controller 18VSM is
at the E 12.048 Ma/s rate.
Turning to Fig. 2, a block diagram of a voice server module 18VSM is soon. The
voice
server module 18VSM includes a multiplexerhnterface 20, a voice processing DSP
array 30 for
processing voice data, an adaptation layer processor 40, a management
processor 50, a channel
associated signaling (CAS) processor 60, and a LIM-management interface 70.
Broadly, in one
dirxti~, the interface 20 receives four 2.048 Mb/s PCM data from a LIM,
combines the data
into a single 8.192 Mb/s PCM highway for the voice processing DSP array 30 and
for the
adaptation layer processor 40, and extracts D-channel information for the
management
processor 50. The voice processing- DSP array 30 receives the data from the
interface 20, and,
under instruction fivm the management processor 50, processes only the voice
data portion of
the data stream. The proving of the voice data can include one or more of echo
cancellation,
silence detection and removal, fax/n~dem tone detection, and data compression
using any of
various voice compression techniques (e.g., LD-CELP (G.728 standard), CS-ACELP
(G.729
standard), ADPCM, etc.). The output of the voice processing DSP array 30 is
provided to the
adaptation layer processor 40 as a compressed data signal on an 8.192 MWs data
bus 74 in
conjunction with a 8.192 Mb/s flag bus 76 which is preferably synchronous with
the data bus
74. The adaptation layer pt~ocessor 40 (which is preferably implemented as a
RISC processor
and coprocessor available from Maker Communications Inc. under the chip
numbers MXT
3010 and MXT 3020) receives the compressed data signal from the DSP array 30,
as well as a
copy of the combined data from the interface 20 (via bypass bus 78), and on a
per-timeslot basis
selects between the two. More particularly, where the data is AALI type data,
the adaptation
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lays processor 40 accepts the data from the bypass bus 78; whereas where the
data is AAL2
type (voice) data, the adaptation layer processor 40 accepts the data from the
data bus 74 which
is sent in conjunction with flag bus information. The adaptation layer
processor 40 processes
the data into ATM cells with appropriate AAL1 and AAL2 formatting in
accaa~dance with TfIJ-T
Rec~nmendations I363.1 and I363.2, and passes the cells to the switch fabric
of the ATM
switch. As will be described in detail with reference to Fig. 4a, where
silence is detected and
indicated by the flags, no cell is generated by the adaptation layer processor
40.
a will be approciated that preferably, additional data (AALS in particular),
independent
of the adaptation layer processor 40, may be sent by the managenicnt processcx
50 to the switch
fabric via an ATM call multiplexcr 80 shown between the adaptation layer
processor 40 and the
ATM switch fabric. Also, if desired, data which is intended for AALS type
adaptation may be
sent from the management processor 50 to the adaptation layer
processes 40 for processing accot~ding to TfU-T Recommendation I363.5 and
forwarding to the
switch fabric.
Briefly, in the other direction, cells received from the switch fabric of the
ATM switch
are passed via the (de)multiplexer 80 to the adaptation layer procxssor 40 and
the management
processor 50. The cells received by the adaptation layer procxssor 40 are
typically disassembled
by the adaptation layer processor 40, with AAL2 related information being sent
via bus 74 (with
associated signaling on flag bus 76) to the DSP array 30, and AALl related
information being
sent via bypass bus 78 to the multiplexcr interface 20. The DSP array 30
decompresses and
otherwise pzncesses the AAL2 voice data as necessary, and provides an output
to the interface
20. Thus, the interface 20 revives data from both the voice processing array
30 and from the
adaptation layer processor 40, and, on a per-d~slot basis, selects between the
two, and
converts the result into four 2.048 MWs PCM highways for output to the LIM.
Before turning to details of each specific block of the voice server module
18VSM,
additional functionality is seen with reference to the chancel associated
signalling (CAS)
processor 60 and the DLSP interface 70. The CAS processor is provided to
process (e.g.,
filter, refresh, convert, and condition) channel associated signalling (e.g.,
on-hook, off hook,
ring, failure states, etc.) received by the voice server module from the LIM.
The processed
CAS information is provided to the adaptation layer processor 40. The DLSP
interface 70 is
used to communicate between the management pisocessor and the LIM.
Turning now to Figure 3, a functional block diagram of the interface 20 is
seen.
Functionally, the interface 20 includes a data conditioning ae~ loopback block
110, a D-channel
extractorfmserter 120, a multiplexer (highway combiner) 130, a per timcslot
demultiplexer 140,
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and a phase-locked-loop clock generator 150. In particular, a 2.048 MHz PCM
LIM clock is
received by the PLL clock generator 150, and four lines of data which
originated from four El
or Tl lines are noceived by the data conditioning and loopback block 110 from
a LIM. The LIM
clock is used by the PLL clock generator 150 to generate a high speed (e.g.,
8.192 MHz) 128-
channel highway clock 162, and a frame sync signal (at an 8 Khz frame rate for
identifying the
first time slot in the PCM frame) 164. The four lines of data are conditioned
by block 110 as is
known in the art. In addition, block 110,under control of the management
processor 50 (Fig.
2), can cause data to be directly looped back to the LIM. Data which is
conditioned by the data
conditioning and loop~ck block 110 is fcwwarded to the D-channel
extractarlmsater 120,
which extracts D-channels from ISDN signals (under control of the management
processor) and
forwards them to the managerrnnt processor 50. The remaining signal is
forwarded to a
highway combiner 130 which multiplexes the four lines together into a single
8.192 Mbit/sec
serial data stream. As indicated in Figures 2 and 3, the combined signal is
forwarded both to
the DSP away 30 and to the adaptati~ layer processor 40; although if desired,
a controller
switch could be utilized to send the appropriate data to each on a per
timeslot basis.
In the return direction (from the switch to the LIM), it will be appreciated
that data is
received at the per timeslot demultiplexer 140 from both from the DSP array 30
and the
adaptation layer processor 40. The demultiplexer 140, under control of the
management
processor 50, chooses on a pct timeslot basis which data is to be forwarded to
the LIM, and
then demultiplexes the data into four data streams. The four data streams are
forwarded to the
D-channel extractorlmserter, where D-channel data (if any) provided by the
management
processor 50 can be instrted into the data streams. The data stream is then
sent to the interface
conditioning block 110 which conditions the data as requirad for output as PCM
data to the
LIM.
Turning to Figures 4 and 4a, a block diagram and a functional diagram of the
voice
procxssing DSP array 30 of the invention are seen respectively. According to
the prefen~ed
embodiment of the invention, the voice processing DSP array 30 includes eight
field
programmable gate arrays 210x, 210b, 210c, ... 210h, and sixty-four DSPs 220a-
1 through
220a-8, 220b-1 through 220b-8, 220c-1 through 220c-8, ..., and 220h-1 through
220h-8.
Each FPGA 210 is coupled to the high speed highway clock 162 and to the frame
sync signal
164 provided by interface 110. In addition, each FPGA 210 is coupled to the
management
Visor SO via a management processor bus 225. Each FPGA 210a
- 210h is associated with an array of eight DSPs 220 which process the voice
data provided by
the specific FPGA.
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The DSPs are preferably ADSP2185 processors available from Analog Devices,
Inc.
which consume very little power, and which are able to process at least two
channels of voice
data in real time as discussed below. Each ADSP2185 processor has its own
2.048 Mb/s serial
input and output highways or buses 230 (e.g., 230a-la, 230a-lb, 230a-2a, 230a-
2b,... 230a-
8a, 230a 8b, 230b-la, 230b-lb,... 230h-8a, 230h-8b) for real time data, an
internal DMA
interface 232 (e.g., 232a-1, 232a-2, ... 232h-8), and an internal SOK memory
(not shown).
Data is forwarded from the FPGAs to the DSPs adding to a frame (discussed
below), and a
flame pulse is provide by the FPGAs to the DSPs as indicated in >~ig. 4.
The 8.192 Mb,/s data output of the interface 110 (one hundred twenty-eight
time slots of
64 Kbi/s data) is provided to each of the FPGAs 210 in the LIM-to-switch
direction. Two
additional 8.192 MbJs signals (a data signal, and a flag signal) are provided
to the FGPAs firm
the adaptation layer processor 40 in the switch-to-LIM direction. In both
directions, each
FPGA is prod by the manage~nt processor to only obtain those channels of data
which are to be processed by the eight DSPs 220 pertaining to that FPGA. The
data received
and aaxpted by each FPGA is written sequentially to a first FPGA buffer memory
245a-1
(through 245h-1) which is arranged to store an entire frame of data. While a
frame of data is
written into the first FPGA memory, another flame of data previously received
by the FPGA is
forwarded (read) from a second FPGA buffer memory 245a-2 (through 245h-2) to
the DSPs
for processing according to a flame. The frame is established in the
configuration lookup RAM
247a (d~~rough 247h) of the FPGA by the management processor which effectively
informs the
FPGA as to which DSP in its array is to handle each particular channel. Which
buffer memory
data is read from and which buffer memory data is written to is switched every
125
microseconds (i.e., at a 8 Khz rate).
Since each bus 230 carrying data between the FPGA and each DSP is a 2.048
Mb~ls bus,
the timing of each bus may be divided into thirty-two 64Kb,/s timeslots; i.e.,
thirty-two bytes
can be sent on each bus at an 8 Kbytes rate. Thus, according to a preferred
aspect of the
invention, the buses 230 are divided into eight sets of four timeslots, with
each four-timeslot set
comprising an unused byte, an uncompressed byte, a compressed byte and a flag
byte as seen in
Table 1.
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I I I I I i I I I i I I I I I I I I I
1 I 3 4 5 I 7I 9 I I I I I I I I I I I 31
0 11 13 15 17 19 21 23 25 27 29
2 6 8 1012 14 16 18 20 22 24 26 28 30
N U C F N U C FN U C F U F U F U F U F U F
N C N C N C N C N C
N = NOT USED U = UNCOMPRESSED C = COMPRESSED F = FLAG
TABLE 1
With this arrangement, up to eight bidirectional channels can be accoma~dated
on a single bus;
although acxordi~tg to the preferred embodiment of the invention, only two
bidirectional
channels are har~led by any DSP at a time. In particular, the uncompressed
byte of the four-
times~t-set is utilized in the L11VI-to-switch direction for sending on a bus
(e.g., 230a-lb)
uncoflapressed data received by the FPGA from the interface 20; while the
c~npresseti byte and
flag byte are used for the same channel in the switch-oo-LIM direction for
sending on the bus
230a-lb tlu compressed data and associated flag received by theFPGA fmm the
adaptation layer
processor 40. After the uncompressed data is processed by the DSP, the
resulting compressed
data and associated flags are sent in the compressed data byte and flag byte
to the FPGA on bus
230x-la for forwarding to the adaptation layer processor 40. Similarly, after
the compressed
data and flag byte are processed by the DSP, the resulting uncompressed data
is sent on bus
230a-la for forwarding to the multiplexerftnterface 20.
The processing tasks of the DSPs 240 are shown in Fig. 4a. In the LIM-to-
switch
dirocti~, A-law err ~,-law data received from the multiplexer/'tnterfaoe 20 is
decoded at 262 and
sent for fax/modem tone detection at 264, for silence/near-end speech
detection at 266, and far
echo cancellation at 268 which utilizes an echo filter coefficient update
block 270 in a feedback
loop. Data which is being compressed is then encoded by an encoder 272, and
the encoded data
is sent along with flag infonmation (as discussed below) to the FPGA. In the
switch-to-LIM
direction, compressed data is decoded at 274 and, in the case of silence,
silence fill 276 is
injected at multiplexer 277. The decoded, expanded data is used to update the
echo filter
coefficient update block 270, and is also provided to an encoder for A-law or
~,-law encoding at
278.
More particularly, data received via the FPGA from the IrIM is decoded by
decoder 262
and subjected to modem tone detection at 264, because it is possible for any
channel to change
from voice data to fax/modem data during a session. The fax/modan detection is
preferably
implemented either utilizing a phase locked loop or according to the Goertzel
Algorithm which
computes the DFT of the primary harmonic of the 2100 t 2lHz tone indicating a
fax or modem
transmission. A Hamming window is applied to the data to flatten the frequency
response. ff
the tone ie above a nrndefined level then a tone will be considered present.
In a preferred
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embodiment, and as seen in Fig. 4a, a flag is output to indicate tone
detection. In o~
embodiment, the flag is placed on bus 230 in the proper timeslot, and via the
FPGA 210 (Fig.
4), the flag bus 76 (Fig. 2) and the adaptation processor 40 (Fig. 2), is
provided to the
management processor 50. In turn, the management proc;cssor 50 generates
control signals
which turns off echo cancellarion and causes the ADPCM ~ CELP encode block 272
to pass
data without encoding, i.e., the mode changes from a compression mode to a non-
compression
mode. Alternatively, a control signal could be generated directly by the
fax/modem detector 264
for the echo cancellation block 268 to turn off echo cancellation and for the
compr~ion
encoder 272 to turn off compression.
The decoded data is also subjected to silcn~ denection by calculating at 266
the input
signal levels. Where the input signal level is indicative of silence, a flag
is generated which will
notify the adaptation layer pmoessor of the silence so that an ATM packet
transmission can be
suppressed.
The input signal level calculated at 266 is also used in the echo cancellation
block 268.
The echo cancellation algorithm utilizes an adaptive transversal filter
implementation which
reduces the mean-squared-error (MSE) of the echo and an estimate of the
replica. The two
functional blocks of the echo cancellation algorithm include the actual echo
cancellation 268 and
the adaptive filter coefficient update 270. Up to a twenty millisecond delay
can be cancelled
using a ono hundred-sixty tap FIR filter with an 8000 Hz sampling rate. The
maximum
processable echo delay can be adjusted by changing the number of taps. The
echo beang
removed consists of the far-end signal being rearmed as a dispersed signal
with attenuation
through the near end signal. The transfer function of the filter attempts to
match this impulse
response of the echo. This process is performed continuously for each channel.
A residual
error silence suppresser is also invoked when the redo of the cancelled signal
to the far-end
input signal is less than -24dB.
The coefficient update is performed during near-end silence and during far-end
speech.
It is assumed by recommendations 6.165 and G.lb8 that the echo of the signal
will be at least
6dB down from the original signal. Therefore, if the near-end signal is not
6dB (or other
configurable value) down from the far-end signal, then a near-end signal is
assumed to be
present. When near-end speech is detected, the filter coefficients will not be
updated. Since
this calculation involves calculating signal level values, the values are also
used in the silence
detection algorithm. The residual error suppresser is automatically
deactivated in the presence
of a near-end signal.
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After echo cancellation, the decoded signal is subjectal to compression by the
c~o~nession encoder 272. According to the preferred embodiment ofthe
invention, the encad~
272 is capable of performing several different compression algorithms under
control of the
management processor. In the preferred embodiment, encoder 272 is capable of
perfarnring at a
minimum 32 kbps ADPCM and LD-CF.LP. Other voice compression techniques include
CSA-
C~LP. It will lx appreciated that enter 272 is preferably capable of ADPCM
compression
f~ the data of one channel, while performing a different compression for a
different channel
Preferably, the signal of a particular channel will continually utilize a
single compressi~
technique after start-up; although,. as previously indicated, the compression
can be turned off
when a fax/modenn tone is detected by detector 264. In addition, flag
information relating to the
compression technique and/or data is generated by the DSP (by the ADPCM or
CELP encoder
272, the silence detector 266, the fax/modem tone detecwr 264) artd sent to
the FPGA in the
timeslot directly afner the data (as indicated in Table 1 ).
In the swish-to-LIM direction, data and flag information from the adaptation
layex
processor 40 are recxived (via data bus 74 and flag bus 76, and FPGAs 210 and
buses 230) by
the decoder 274. The decoder 274 decodes (expands) the data (e.g., ADPCM-type
or CELP-
type data). If the flag information indicates silence, the multiplexer 277 is
controlled to receive
data from the silence fill 276 indicative of silence (e.g., a scaled
background pseudorandom
noise pattern). If the flag information is not indicative of silence, the
multiplexer 277 passes the
data decoded by the decoder 274. The dscoded, expanded data is used to update
the echo filter
coefficient update block 270, and is also provided to an encoder for A-law or
p.-law encoding at
278. The A-law or ~-law data is then sent to the FPGA for forwarding to the
L1M as
pnwiously described. -
As previously mentioned, in the LIM-to-switch direction, the DSP generates
flag
information which relates to the data being processed and which is sent to the
FPGA directly
after the processed data. This flag data is provided to buffer memory in the
FPGA and then
combined using timeslot mapping for forwarding onto the 8.192 Mb/s flag
highway which
couples the voice processing means 30 to the adaptation layer processor 40;
while the processed
data is forwarded into the 8.192 Mb/s data highway which couples processors 30
and 40. The
compressed voice data and the flag data are preferably sent synchronously.
In a first embodiment of this aspect of the invention, for each byte of data
(sent serially
on the high speed serial bus), at least one bit of flag data is sent on the
flag bus. In the preferred
arrangement of this first embodiment, one or two bits are used to indicate
whether the data on
the data bus is valid or not; i.e., data or no data, one bit is used to
indicate fax/modem tone
detection, one bit is used f~ silence detection, and one or more bits are used
to indicate which
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type of encoding is being utilized. Thus, for example, for each byte of data
on the high spool
data bus the additional bits may be utilized to distinguish between 2-bit
ADPCM, 3-bit ADPCM,
4-bit ADPCM, 8-bit PCM, 6.728 LD-CELP, G.729a CS-ACELP, etc. Technically, with
n
bits, 2" different encoding schemes can be identified. Alternatively, if five
or fewer encoding
sch'ar» arc possible for the equipment, a single bit can be used as an ON-OFF
bit for each
encoding scheme (i.e., n bits for n encoding schemes) in order to indicate
which encoding
scheme is being utilized.
In a second, presently prefenrod embodiment of this aspect of the invention,
the flag bus
is usod both to synchronic the adaptation layer processing pans 40 a~ the
voice processing
means SO (preferably, according to a forty frame superframe of five
milliseconds) as well as to
send control information. The control information includes two bits to provide
a forty frame
synchronization signal, a bit which indicates whether the data is compressed
or not, a bit to
indicate silence, a bit to indicate tone detection, and a bit to indicate an
"out of data" indication
The presently prefernxl arrangement of bits is shown in Table 2.
BIT FUNCTION
0 synch and valid
flag
1 synch and valid
flag
2 compressed or
not
3 silence
4 tone detecoe~i
valid data or
resynch
6 out of data
7 future use
TABLE 2
In particular, in the prefsrrod embodiment of the invention, bit values of
"10" for bits 0 and 1
are used as synchronization bits to indicate the start of a forty frame
superframe, i.e., a
supcrhame of five milliseconds of data. The remainder of the bits arc
considered valid only
when the synchronizatia~n bits are at the preset value of "I O". In the LIM-to-
switch directi~,
bits 0 and 1 should be set to "10" every five milliseconds. In the switch-to-
LIM direction, in a
prefenned embodiment of the invention, a "10" i~ication is only provided if
data was received
by the adaptation processor, i.c., during a period of no silence.
Bit 2 is effectively generated by the encoder 272 (Fig. 4a) and is used to
indicate
whether the data is compressed or not; it being assumed that only one type of
compression is
being conducted by the voice processing pans (e.g., 4-bit ADPCM) for a given
channel.
Thus, when bit 2 is set (i.e., value = 1 ), compression is indicated; and when
bit 2 is not set
(i.e., value = 0), no compression has been conducted on the associated data
being sent over the
high speed data highway.
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Bit 3 is effectively set by the silence detexoor 266, a~xl when sct indicates
a five
millisecond period of silence such that the data being received over the high
speed data highway
can be ignored. In the LIM-to-switch direction, the silence bit is set every
five millisexonds in a
period of silence exceeding five milliseconds. In the switch-to-LINT
direction, in the preferred
embodiment of the invention, the silence bit 3 is only set once per period of
silence by the
adaptation processor, because only during a transition from no silence to
silence will the
synch/valid flag be set to "10".
Bit 4 is controllexi by the fax/modcm tone detector 264. When set, bit 4
indicates that a
none has been detected so that the adaptation processor 40 can notify the
management processor
50; which in turn can turn off echo cancellation and ADPCM or CELP encoding in
the LIM-to-
switch direction, and the ADPCM or CELP decoding in the switch-to-LIM
direction.
Bit 5 may be used, if desired, in c;onjunetion with the G.729a standard which
utilizes ten
millisecond block sins, with five milliseconds of valid data alternating with
five millisexonds of
~n-valid data. Alternatively, bit 5 may be used for resynchmnization should
the DSP array
and adaptation processor lose synchronization.
Bit 6 is used in the LIM-to-switch direction to indicate an out-of data
condition. The
~t-of-data condition can arise, e.g., where the adaptation processor 40 has no
data due to a lost
cell, and it therefore does not send a synch/valid flag. In that situation,
because thc; DSP stray
is expecting data (no silence flag having previously being sent) the DSP ansy
30 will have no
data to process, will insert silence, and send the out-of-data flag. Rexcipt
by the adaptati~
processor of an out-of-data flag permits the adaptation processor to reset its
buffer
pointers and send a message to the management processor. Bit 6 is not used in
the switch-to-
LIM direction.
Presently, bit 7 is not defined and can be used for additional functionality.
For example,
bit 7 can be used to redefine all or sonic of bits 0-6.
Turning now to Figure 5, a block diagram of the functional blocks of the
management
processor 40 is seen. The management processor 40 is sexn to include a
Motorola 68360 slave
processor 410, a 68040 master CPU 415, cell FIFOs 420, GPU (microprocessor)
bus buffers
430, an address decoder 435, a boot PROM 442, a flash RAM 444, a DRAM 446, a
base
control register 452, a base status register 454, a L,ED register 456, a
general purpose 1/O
register 458, a LIM 1/O register 462, and a board >D and revision register
464. The
manage~nt processor 40 generally provides hardware initialization and real
time control,
c~figuration, diagnostics, status, alarms, and call control for the voice
server module 18VSM.
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The address decode 435, boot PROM 442, flash memory 444 and DRAM 446 all
function as is
standard in the art. The base control register 452 permits the management
processor 40 to reset
elements of the module 18VSM independently of each other, while the board ID
and revision
register 464 keeps information regarding the hardware revision of the module
and the ID
number of the module. The base status register 454 keeps status infalmation
regarding the
various elements of the module 18VSM. The LED register 456 c~trols the
lighting of ttie fiont
panel LEDs (not shown). The general purpose 1/O register is provided for
general
communication with elements of the management processor 40. Information
intended for the
LIM is fed to the LIM 1/O register 462. The management processor 40
communicates to
the internal elements of the voice server module (shown with the "mgmt"
inputs) s»h as the
DSP array 30, the CAS procxssor 60, ctc., and to the LIM using the CPU bus
which is
buffered by buffers 430. The management processor 40 communicates to other
boards of the
switch 10 by generating ATM calls and passing them to the switch via the cell
FIFOs 420.
Preferably, the managec~nt processor 40 uses a packet-type protocol in those
communications.
In fact, the management processor 40 (and hence the voice server module as a
whole) is
preferably provided with an IP address so that it may be contacted by other
suitable means off
of the switch.
As previously mentioned, the slave processor 40 is used to process D-channel
information which was exu~acted firm an ISDN signal by the D-channel
extractor/inseroer 120
of the interface 20. As a result of processing the D-channel information, the
management
processor 50 performs necessary functions and sends necessary messages. The
messages can
be internal to the voice server module 18VSM or can be messages that are
formauod into AALS
format for transfer across the switch fabric, to another module and LIM and
out to the network.
Alternatively, or in addition, the managerrient processor 50 can generate
signals which are
provided to the adaptation processor 40 which formats them into AALS type
signals. The
management processor can also generate D-channel signals (in response to
external information)
for insertion at the D-channel extractor/inserter 120 into an outgoing ISDN
signal.
Turning to Figure 6, a block diagram is seen of the functional blocks of the
CAS
processor 60. The CAS processor, which may be contained on the chip or
chipsets
implementing other functions (e.g., the adaptation processor 40) includes
buffers 502, 504 for
the incoming and outgoing LIM signalling highways, an idlehelease and
transition detect logic
block 512, a refresh timer 516, a signalling conversion to AAL2 packets block
522, and a
signalling conversion from AAL.2 packets block 528. Channel associated
signaling from the
LIM with respect to any of the four Tl or El lines are received at the buffers
502. The
idlehelease transition detect block 512 a~nitors the incoming signaling in
order to deb a
change in state (e.g., off hook to on-hook), and based on the current state of
the line and the
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change in state, whether the rnanagemcnt processor needs to know of the
situation. Where the
management processor 50 needs to allocate resources as a result of the
incoming signals (e.g.,
~ set up an AAL.2 channel), the CAS processing block sends a message to the
resource
allocation event queue of the management processor 50. Oncx the resources have
been allocated
by the management processor 50, the management processor enables the signal
converter 522 to
pacbetize the incoming data (stored in buffers 502) into AAL2 type data for
forwarding to the
adaptation procxssor 40. In the prefennd embodiment of the invention, the
refresh timer 516
also suds data to the adaptation processor 40. In particular, every five
seconds, the refresh
timer 516 ascertains the present state of the channels (as scored by the
idle,/release uansition
detect logic block 512) and forwards that state to the signal converoer 522
for packetizing and
forwarriing as the adaptation processor.
In the switch-to-LIM dmction, AAL2 packets c~tsir>irtg CAS infon~ation are
pmwided
to the CAS processor 60 by the adaptation processor 40. The CAS infomation is
corrverted by
the signalling conversion block 528 into E1 or Tl type data and forwarded to
the buffers 504.
At the same tune, the CAS information is read by the idleJrelease transition
detect block 512 for
change of state information which might require action by the management
processor 50.
There have been described and illustrated herein a voice sewer module for' an
ATM
switch. While particular embodiments of ~e invention have been described, it
is not intended
that the invention be limited thereto, as it is intended that the invention be
as broad in scope as
the art will allow and that the specification be read likewise. Thus, while
the invention has bxn
described with reference to a particular ATM switch, it will be ~ that the
inventiotr
applies to different types of ATM switches. Also, while the invention has been
described with
reference to particular functional blocks, it will be appreciated that in many
cases the functional
blocks can be combined or divided while still maintaining the functionality of
the invention, and
also that various functional blocks are often preferably accomplished in
software. In addition,
while particular bus an~angements and speeds have been described, it will be
appreciated that
other bus arrangements could be utilized. For example, rather than having
separate high spend
data and flag buses linking the voice processing means and the adaptation
processor, an even
higher speed bus with interleaved voice and flag information could be
utilized, provided
appropriate circuitry and functionality is provided for multiplexing and
demultiplexing the two
streams. Further, while various novel aspects of the invention were described,
it will be
appreciated that each of the novel aspects stands independently of the others.
For example,
while a novel DSP array for' processing voice data is provided, it will be
appreciated that the
voice ptoc~sor/adaptation processor interface which utilizes separate flag and
data buses could
be utilized with a single voice data DSP. Similarly, the provision of the
alternative data paths
for the AAL2 and AALI data in the voice server module stands independently of
the separate
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flag and data bus arrangement and from the DSP array. It will therefore be
appreciated by those
stilled in the art that yet other modifications could be made to the prrnddod
invention without
deviating from its spirit and scope as so claimed.
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