Note: Descriptions are shown in the official language in which they were submitted.
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This application is a division of application Serial No.2,106,442
filed September 17, 1993.
1
SOUND PROCESSING APPARATUS
HACRGROUND OF THE INVENTION
The present invention relates to a sound processing
apparatus, and more particularly to a sound processing apparatus
used in a game computer system.
Traditionally, in a computer system, sound is produced
from waveform data, which is generated by a computer program
based process; however, the quality of the sound has been low.
For that reason, sound data (analog signals) now are converted
into digital signals so. that the sound waves may be synthesized
by an arithmetic operation.
In general, a game computer use a programmable sound
generator (PSG), which is small in size and capacity. In the
PSG, wave data supplied by a CPU are modulated in amplitude or
frequency in order to generate a sound wave. The PSG may
generate simple waves to intentionally produce noise. According
to the PSG, it is easy to control the output sound; however, it
is difficult to generate a variety of sounds.
For A/D conversion, a pulse code modulation (PCM)
method is used, by which an analog signal is sampled at
predetermined intervals, the sampled data are quantized, and
then, are transformed into binary data.
According to a difference PCM (DPCM) method, the
difference of the next two sampled data is quantized so that the
amount of output data is reduced. Further, according to an
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adaptive difference PCM (ADPCM) method, the quantizing process
is performed at a short pitch when the next two sampled data
have a great difference, and on the other hand, the process is
performed at a long pitch when they have a small dif ference . As
a result, the output data may be more compressed.
The PCM and ADPCM data are compatible with each other
by compression and extension processing, which is performed
based on conversion between scale value and scale level, and
between the ADPCM data, the changing amount and changing level
of the data.
In a game computer, ADPCM sound data stored in an
extra recording device are read by a CPU, and the data are
extended by an ADPCM decoder in accordance with a scale value
and a scale level, so that the original sound is reproduced.
The ADPCM decoder contains a synchronizing signal generating
circuit, which generates a transmission rate using a crystal
resonator. The PCM data are reproduced in accordance with the
transmission rate.
Recently, the game computer has become provided not
only with a sound source such as PSG and ADPCM controlled by the
CPU, but also an external audio device to realize high quality
sound reproduction. For example, in a game computer using a CD
( compact disk ) as recording medium, a CD player is directly used
as the PCM sound source to generate high quality sound.
Generally, the sound data are controlled in volume by
a volume control circuit, and output sound is supplied through
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a mixer circuit. Basically, two types of volume control
circuits, analog and digital types, are used in game computers.
According to the volume control circuit of the analog type,
volume of output sound is controlled by a voltage signal. The
volume control circuit of the digital type includes a D/A
converter, in which a conversion ratio is changed for each bit.
An attenuation amount (N) of a volume control circuit is given
by the equation "N ( Db ) - log ( I1/Io ) , " where I1 and Io represent
levels of input and output signals, respectively. Most volume
control circuits include registers holding values for specifying
attenuation values of sound data.
Fig. 1 shows the relation between register values and
attenuation values for a volume control circuit contained in a
conventional sound processing apparatus. As shown in this
table, an attenuation range of l2dB is divided into eight
levels, in which the first four values are set to have ldB
differences from each other, and the last four values are set to
have 2dB differences from each other. The attenuation levels -
ldB, -2dB, -3dB, -4dB, -6dB, -8dB, -lOdB and -~,2dB correspond to
register values 7, 6, 5, 4, 3, 2, 1 and 0, respectively.
In the conventional volume control circuit, the
difference values of attenuation are not constant, because it is
difficult to divide the total attenuation level (attenuation
range ) constantly, especially at the maximum and minimum levels .
According to the conventional volume control circuit, the
register values are determined to correspond to the attenuation
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levels one-to-one, and therefore, it is difficult for an
operator to adjust the sound volume to desired levels.
A conventional game computer contains a sound source
chip for sound processing. Most sound source chips include
sound sources for generating sound, and volume control circuits
for controlling volume of the sound supplied from the sound
sources. The volume control circuits are structured to be
adapted to the characteristics of sound to be reproduced and the
performances of amplifiers, speakers and the like.
When an external volume control circuit is provided
with the game computer to realize high performance sound
processing, a controller circuit is required to be built in the
system to control the external volume control circuit.
Recently, a plurality of sound sources are employed in
a game computer to treat a variety of sound, to produce special
sound and music effects. However, such a high performance
system is expensive for a game computer, because plural volume
control circuits having different performances must be
controlled properly.
Generally, a plurality of sound sources, such as PSG
and ADPCM, are contained in different sound chips individually,
and output sound of the sound chips are also supplied to an
external mixer circuit.
When an external sound source, such as a CD player
with no volume controller, is employed in the system, an extra
volume control circuit is necessary to be contained in the
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system to control volume of the player. As described above,
when a plurality of sound sources are employed in a system, the
circuitry in the system becomes complicated,'and as a result,
the cost of the system becomes high.
5 In the conventional game computer, volume and output
controlling by the volume and mixer circuits are performed in
accordance with values held in internal registers.built in the
volume control circuits, the register values being set by a CPU.
According to the conventional system, the circuitry in the
system becomes complicated because the CPU controls the sound
chips individually.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention
to provide a sound processing apparatus in which output volume
may be adjusted to desired levels easily by operators.
It is another object of the present invention to
provide a sound processing apparatus, which may be fabricated to
have a simple structure even if an external sound source is
employed therein.
It is still another ob ject of the present invention to
provide a sound processing apparatus, which may be fabricated to
have a simple structure even if a plurality of sound sources are
employed therein.
According to a first feature of the present invention,
a sound processing apparatus includes a volume control circuit
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for controlling volume of output sound, and a register for
holding plural values specifying attenuation levels. The
register values are determi:aed to linearly correspond to the
:rate of change of the a~.tenuation level.
According to a sect>rzc~ featuwe of tine present invention,
there is provided a sour:.d proces~~i.ng apparatus, which contains
a sound source ~~hip, cony~:r '_s inch
a sound source witrv.in the sound source chip for producing
sound data;
an external volume :control t~ix~cuit, whielu is placed out
of the sound sc>urce chid:;, arid is supplied with. the sound. data
from said sound. source ';::c:> c~.c:~ntrol vol.i~me of output sound.; and
an internal controller circ.~.uit, which is built in the sound
source chip, for supp_Ly:irag a control syc~r~al to said external
volume control circuit, end for c::o:~tro?.1 ing the output sound
when said external volume :~ontroi circuit does not opE:rate,
wherein:
said sound sourc::e electrically produces sound by
programming.
According to a third feature of the present invention,
a sound processing apparatus includes a sound source chip, and
an external sound source for generating external sound <iata.
'the sound source chip contains an internal sound source
generating internal sound data, and a mixer circuit for mixing
'the internal and external sound data to generate output sound.
According to a fourth feature of the present
invention, a sound processing apparatus includes a sound source
chip, and an external sound source for generating external wound
data. The sound source chip contains an internal sound source
generating internal sound data, a volume control circuit to
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which the internal and external sound data are supplied for
controlJ.ing voJ.ume of :ou.t.p~ut sauna, and a ni.ixer circuit to
generate output: sound in accordance with output data of the
volume control circuit.
According to a fourth featm:~e of tze present invention,
there is provided a sound processing apparatus, comprising:
a sound source ch:l.p _.i.r:crluding a.ra internal sound source
for producing sound date:.;
an external volume control circuit arranged apart from
said sound source chip and responsive_ to said sound data from
said internal sound sc:urce, far- controlling the volume of
output sound; and
an intern<~l volume ~::a:r~trol cJ.rcuit arranged within the
sound source chip for supplying a control signal to said
external. volurr~e contrc>l ci:rcuit:, and for controlling the
volume of output sound when said external volume control
circuit does not operate., said internal volume control circuit
including,
a plurality of registers, each storing at least one
register value representing an amplifier and attenuation step.
BRIEF DESCRIPTION OF THL DRAWINGS
FIG. 1 is a table showing a relation between values of a
register and attenuatic>ra :Levels in a volume control circuit
according to a conventional sound processing apparatus.
FIG. 2 is a block diagram showing a r_amputer system using
a sound processing apparatus according to the invention.
FIG. 3 i:~ a block diagram sh.owi.ng a sound data output
unit according to the irwention.
FIG. 4 is a table showing a relation between values of a
register and attenuatioru levels in a volume cantrol circuit
according to the invent i ~:~rn ,.
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FIC~. 5 is a d:iagr~=~m snowing the cartents of an operation
register according to t:.e invention.
FIG. 6 is a diagram showing the contents of a volume
register according to tt-_c:~ in~~ent::i_ .n.
FI!~. 7 is a diagrar~~ showing the contents of control
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registers according to the invention.
Fig. 8 is a diagram showing the contents of a PSG
operation register according to the invention.
Fig. 9 is a table showing a relation between a
register and addresses AO to A3 of the PSG according to the
invention.
Fig. 10 is a timing chart showing operation of the
rsound data output unit according to the invention. '
a:
Fig. 11 is a block diagram showing a sound source chip
with an internal volume control circuit according to the
invention.
Fig. 12 is a conceptual view showing an example of the
sound source chip according to the invention.
Fig. 13 is a table showing interrelationships among
register values, amplifier and attenuation steps, and adjusting
speed, according to the invention.
Fig. 14 is a block diagram showing a sound source chip
with an external volume control circuit according to the
invention.
Figs. 15 to 17 are conceptual views showing other
examples of the sound source chip according to the invention.
DETAILED DESCRIPTION OF THE INVENTION
Fig . 2 shows a computer system, which includes a game-
software recording medium 100 such as a CD-ROM, a CPU 102 of the
32-bit type, a control unit 104 for mainly controlling
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transmission of sound data and interfacing most devices to each
other, an image data extension unit 106, an image data output
unit, a sound data output unit 110, a video encoder unit 112, a
VDP unit 114 and a TV display 116.
CPU 102, control unit 104, image data extension unit
106 and VDP unit 114 are provided with their own memories M-RAM,
K-RAM, R-RAM and V-RAM, respectively.
Fig. 3 shows sound data output unit 110, shown in Fig.
2 . The sound data output unit includes , a 6 channel programmable
sound generator (PSG) 300, right and left channels ADPCM
decoders (#1 and #2) 302 and 304, a sound data output circuit to
which sound data are supplied from the CD-ROM (external sound
source ) , and a volume control circuit 306 for controlling output
of the ADPCM decoder and PSG.
Fig. 4 shows a relation between values set in the
volume register and attenuation values to be used. As shown in
this table, an attenuation range of l2dB is divided into eight
levels, in which the first four values are set to have 1dB
differences from each other, and the last four values are set to
have 2dB differences from each other. The attenuation levels -
ldB, -2dB, -3dB, -4dB, -6dB, -8dB, -lOdB and -l2dB correspond to
register values 11, 10, 9, 8, 7 and 6, 5 and 4, 3 and 2, and 1
and 0, respectively. Each register value corresponds to 1dB
(changing rate). If the total attenuation values -lOdB and -
l2dB are changed to -lOdB and -lldB, register values 3 and 2,
and 1 are set to correspond to the attenuation values of -lOdB
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and -lldB, respectively.
According to the invention, it is easy for operators
to adjust output volume to desired levels by their sense,
because the register values linearly correspond to the relative
5 difference value (1d8) of attenuation levels. Especially, the
invention is useful for ittusic produced by a program, in which
sound volume is required to be monitored in accordance with
register values.
Sound data supplied from the ADPCM decoder are
10 buffered in the R-RAM and are transmitted by the control unit.
Bascally, the ADPCM decoder uses a sampling frequency of
31.47kHz; however, 15,73kHz, 7.87kHz and 3.98kHz are available.
The ADPCM sound data are defined by 4 bits, in which the first
bit represents a code, and are transmitted for each byte.
In the computer system, sound volume and sampling
frequency of the ADPCM decoder, soft-reset, and operation of the
PSG are controlled by the CPU using registers.
The registers contained in the ADPCM decoder are now
explained in conjunction with Figs. 5 and 6.
Fig. 5 shows an operation register for specifying
operations of the ADPCM decoder. A sampling frequency of the
ADPCM decoder is specified using 2 bits.
Fig. 6 shows a volume register for specifying sound
volume of the ADPCM decoder. Each channel of the ADPCM decoder
is controlled in volume for right and left. When each of the
registers D5 to DO is set at "3F (hexa)," the maximum volume is
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obtained. One register value corresponds to an attenuation
amount of -1. 5dB, and the register value "1C ( hexa ) " corresponds
to the maximum attenuation amount -52.5dB. When the register
value is set at 1B to 00, no sound is obtained.
Fig. 7 shows control registers contained in the
control unit for controlling the operation of the ADPCM decoder.
Fig. 7(1) shows a reproduction mode register for
holding data that specify a sampling frequency and a start
timing for data transmission.
Fig. 7(2) shows a data buffer control register for
holding data that specify an interrupt operation and a condition
of a memory storing sound data to be transmitted to the ADPCM
decoders #1 and #2.
Fig. 7(3) shows a start address register for holding
data that specify a start address of data to be read from the
memory.
Fig. 7(4) shows an end address register for holding
data that specify an end address of data to be read from the
memory.
Fig. 7(5) shows a half address register for holding
data that specify an address for an interrupt operation.
Fig. 7(6) shows a status register for holding data
that specify conditions of data transmission from the ADPCM
decoders.
The PSG employs a waveform memory system, by which
waveforms are generated for each channel in accordance with the
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contents of a waveform register, a waveform of each period being
formed by 5 bits x 32 words.
Fig. 8 shows a register unit for holding data that
specify the operations of the PSG.
Fig. 8(1) shows a channel select register RO for
holding data that specify a channel address.
Fig. 8(2) shows a main volume register R1 for holding
data that specify the whole volume of sound generated by mixing
sounds of all the channels. In response to r,MAr. and RMAL, left
and right outputs are controlled, respectively. Each of the
LMAL and RMAL is defined by 4 bits, and has the maximum volume
when "F (hexa)" set thereat. A value 1 corresponds to an
attenuation width of -3dB.
Fig. 8(3) shows a register R2 for holding data that
specify an amount for fine adjustment of a frequency.
Fig. 8(4) shows a register R3 for holding data that
specify an amount for rough ad justment of the frequency, so that
the output frequency is specified in accordance with values held
in the last four bits of the registers (4) and in the register
(3).
Fig. 8(5) shows a register R4 for holding data that
specify the operation of the PSG. At the first bit, data for
controlling output of the channel and writing operation of data
to a waveform register R6 are held. At the second bit, data for
controlling a direct D/A mode are held. When "1" is set at the
first bit, output operation (mixing) of the sound of the channel
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is performed. When "0" is set at the first bit, no output sound
is supplied, and data are able to be written into the waveform
register R6. When "1" is set at the second bit, an address
counter of the waveform register R6 is reset, and a data signal
is directly supplied to a D/A converter. When "1F (hexa)" is
set at the last 5 bits, the maximum volume is obtained. Each
register value corresponds to an attenuation width of -3dB.
Fig. 8(6) shows a volume register R5 for holding data
that specify sound volume.of the right and left channel. The
first and last four bits LAL and RAL are used for sound volume
of the left and right channels, respectively. When "F (hexa)"
is set at LAL and RAL, the maximum volume is specified for the
channel. Each register value corresponds to an attenuation
width of -3dB
Fig. 8(7) shows the waveform register R6 for holding
a waveform for one period of the channel. The register holds
waveform data of 32 words (5bit/word) for one channel.
Fig. 8(8) shows a register R7 for holding data that
specify whether noise or music is selected to be used and a
frequency of a clock signal to be supplied to a noise generator.
The noise enable and noise frequency data are held at the first
bit and the last five bits, respectively.
Fig. 8(9) shows a register R8 for holding data that
specify a frequency of an LFO (Low Frequency Oscillator) for
frequency modulation. .
Fig. 8(10) shows a register R9 for holding data that
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specify whether the LFO is set or reset and a modulation degree
of the frequency modulation using the LFO.
The registers shown in Fig. 8 are provided for each
channel. The registers R2 to R7 are addressed by AO to A3 and
the register R0; however, the registers R0, R1, R8 and R9 are
addressed only by AO to A3.
Fig. 9 shows a relation between the registers RO to R9
and the address values AO to A3.
The PSG employs a dynamic range (D range) of 45dB.
Therefore, when the total amount of attenuation level of the
register R1 (LMAL/RMAL), register R4 (AL) and register R5
(LAL/RAL) is less than -45dB, no sound is reproduced because the
amount -45dB is in practice equivalent to -~dB.
The operations for writing data by the CPU into the
registers, shown in Figs. 7 and 8, are now explained in
conjunction with Fig. 10.
Fig . 10 shows voltage levels at input terminals of the
sound data output unit. In this figure, -CS, AO to A4, -WR and
D7 to DO represent a chip select signal, a write address signal,
a write signal and a data input signal, respectively. Input
data are supplied from the CPU through the bus of D7 to DO to
the sound data output unit. In a write mode when the write
signal -WR is low, data are written through D7 to DO to the
registers specified by the chip select and address signals from
the CPU. Each time when the write signal -WR rises to a high
level recovery mode (shown by broken line), the data are
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latched, and then the latched data become effective at the next
falling edge of a sampling clock pulse. When data are written
more than two times in one sampling period, the following data,
which have been written just before the previous data, become
5 effective.
Fig. 11 shows a sound data output unit (sound source
chip) of a second preferred embodiment. This unit includes a
volume control circuit 406 containing right and left VCAs
(Voltage Control type Amplifier) , VCAR and VCA1,, for controlling
10 sound volume of the PCM sound signal supplied from the CD-ROM.
The sound data output unit is provided with VCA input terminals
VCARIN and VCALIN. The input terminals are connected to output
terminals VCAROUT and VCAR, and VCALOUT and VCAL, respectively.
The output terminals VCAROUT and VCALOUT are used when volume
15 control circuit 406 is used as an internal volume control
circuit. The output terminals VGAR and VCAL are connected to an
external volume control circuit so that circuit 406 is used as
a controller circuit.
In this embodiment, volume control circuit 406 is used
as the internal volume control circuit, and therefore, the
output terminals VCAROUT and VCALOUT are connected through
terminals LINER and LINEL to mixer circuits 408 and 410,
respectively. In this unit, four sound signals are supplied
from two channels of ADPCMs 412 and 414 and six channels of PSG
416 and PCM to each mixer circuit. The VCAs include volume
registers R15 and R16 for specifying an attenuation level to
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control output sound volume.
Fig. 12 shows a sound source chip 500 of the second
preferred embodiment, which is a conceptual view of the sound
data output unit shown in Fig. 11. The sound source chip
includes a sound source 502, an internal volume control circuit
504 and a mixer circuit 506. Other sound sources, and other
volume control circuits for plural sound sources, may be
R contained in the sound source chip.
Fig . 13 shows the characteristics of the VCA, register
values, amplifier and attenuation steps, and adjusting speed.
Output of the unit shown in Fig. 11 having the characteristics
shown in Fig. 13 is now explained.
When the register is rewritten "3F" to "00", the
volume level is changed by "20 log (0 / 1023) - -~dB", and the
necessary time T is given by the following equation.
T = 1.49 x 512 + 2.98 x 256 + 5.96 x 128 + 11.92 x 64
+ 23.84 x 32 + 47.68 x 16 + 2956.16 = 7.53ms
when the register is rewritten "3D" to "3F", the
volume level is changed by "20 log (1023 / 991) - 0.27dB", and
the necessary time T becomes 47.68~s = 49 x (1023 - 991).
Fig. 14 shows a sound source chip (sound data output
unit) according to a third preferred embodiment. This unit has
the same structure as that of the second preferred embodiment
shown in Fig. 11; however, an internal volume control circuit
406 operates as a controller circuit to control an external
volume control circuit 600. External volume control circuit 600
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is connected through VCAR and VCAL terminals to the internal
volume control circuit, so that volume registers R15 and R16 are
rewritten in accordance with direct voltage signals supplied to
the VCA input terminals VCARIN and VCALIN. In response to the
direct voltage signals, control voltage signals are generated to
be supplied to the external volume control circuit. The
external volume control circuit supplies sound data which have
been controlled in volume to the mixer circuits.
Fig. 15 shows a sound source chip 700 of the third
preferred embodiment, which is a conceptual view of the sound
data output unit shown in Fig. 14. The sound source chip
includes a sound source 702, a controller circuit (internal
volume control circuit) 704, and a mixer circuit 706 connected
to an external volume control circuit 708.
How to obtain the control voltage when the unit shown
in Fig. 14 has the characteristics, shown in Fig. 13, is now
explained. When 1.0V voltage is applied to analog ground, and
the register is rewritten "3D" to "3F", the output voltage V and
necessary time T are given by the following equations.
V = -1 x 1023 / 991 = -1.032V (analog ground)
T = 1.49 x (1023 - 991) - 47.68us
As described before, according to the second and third
preferred embodiments, the internal volume control circuit is
used as either the volume control circuit or controller circuit
for the external volume control circuit. Therefore, when the
external volume control circuit is employed, ari extra controller
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circuit is not necessary. Further, the internal mixer circuits
also operate for the external volume control circuit, and as a
result, internal and external sound may be mixed to generate
output sound.
Fig. 16 shows a sound source chip 800 of a fourth
preferred embodiment. The sound source chip includes a sound
source 802, a volume control circuit 804 connected to an
external sound source (not shown), and a mixer circuit 806.
Other sound sources, and~other volume control circuits for
plural sound sources may be contained in the sound source chip.
If the volume control circuit is not necessary, a sound signal
from the external sound source is supplied to.the mixer circuit
directly.
The mixer circuit contains not only an internal mixer
that mixes sound from a multi-channel sound source, but also a
mixer that mixes sound from a variety of sound sources.
Fig. 17 shows a sound source chip 900 of a fifth
preferred embodiment. The sound source chip includes an ADPCM
sound source 902, a PSG sound source 904, and a mixer circuit
906. Other sound sources, and volume control circuits, and two
channel mixer circuits may be contained in the sound source
chip.
As described before, according to the invention, an
extra external mixer circuit is not necessary, because a
plurality of sound sources such as PSG and ADPCM are connected
to the internal mixer circuits . Further, it easy to control the
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sound data output unit by the CPU, because the registers for
controlling sound output are contained in one chip.
